Power semiconductor device

Abstract

The utility model relates to a power semiconductor device. The power semiconductor device comprises a gate contact ring and at least one gate commutated thyristor. The gate commutated thyristor comprises a cathode region and a gate region which are independently arranged in the first base region, and the cathode region and the gate region are electrically connected through the first base region and the gate contact ring; the distances between at least one gate pole commutation thyristor and the gate pole contact ring are different, and the resistance of the gate pole region of each gate pole commutation thyristor is in negative correlation with the distance between the gate pole region and the gate pole contact ring, so that the voltage difference applied to each gate pole commutation thyristor by the gate pole contact ring is reduced, the voltage uniformity of the power semiconductor device is improved, and the reliability of the power semiconductor device is improved. And the turn-off uniformity of the power semiconductor device is improved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to a power semiconductor device. Background Art

[0002] Integrated Gate Commutated Thyristor (IGCT) is a new type of semiconductor switching device. IGCT device is formed by integrating gate drive circuit with gate commutated thyristor GCT. IGCT device is a megawatt-level, medium and high voltage switching device. IGCT device has the same high blocking capability and low on-state voltage drop as turn-off thyristor (GTO). IGCT device has similar switching performance as insulated gate bipolar transistor (IGBT). IGCT devices are widely used in voltage source inverters, current source inverters, choppers, static circuit breakers and many other topology circuits.

[0003] GCT chip is a whole wafer structure, such as Figure 1 A top view of a GCT chip is shown, wherein the GCT chip comprises a terminal region, an active region and a gate contact ring, wherein the terminal region surrounds the periphery of the active region, the active region comprises a plurality of parallel gate-commutated thyristors, the active region is displayed as a plurality of concentric cathode rings in the top view, each cathode ring is provided with a plurality of cathode emitter regions distributed radially, the cathode emitter region is an independently arranged island structure, the gate regions are connected to each other and surround the cathode emitter region, the cathode emitter region and the gate region are not connected, the gate contact ring is located inside the chip, the gate contact ring is connected to the gate regions, the gate contact ring is used to transmit gate signals and derive current from the cathode commutation of the gate-commutated thyristor to the gate when the gate-commutated thyristor is turned off.

[0004] The cross-section of a gate-commutated thyristor is shown in Figure 1. Figure 2 As shown, the gate-commutated thyristor includes a P+ emitter region, an N buffer region, an N-drift region, a P base region, a P+ short base region and an N+ emitter region arranged in sequence from the anode to the cathode, the P+ emitter region and the N buffer region form a PN junction J1, the N-drift region and the P base region form a PN junction J2, and the P+ short base region and the N+ emitter region form a PN junction J3. The anode electrode is arranged on the bottom surface of the P+ emitter region and is in ohmic contact with the P+ emitter region, the cathode electrode is arranged on the N+ emitter region and is in ohmic contact with the N+ emitter region, the gate electrode is arranged on the P+ short base region and is in ohmic contact with the P+ short base region, an insulating layer is arranged between the cathode electrode and the gate electrode, and the cathode electrode and the gate electrode are electrically isolated by the insulating layer. Wherein, the upper surface of the gate electrode and the insulating layer is covered by a passivation layer.

[0005] For the entire GCT chip, Figure 3 , Figure 4 As shown in Figure 2, when the GCT device is turned off, a negative bias voltage V is applied between the cathode electrode and the gate contact ring. GK , and then the gate contact ring transfers the negative bias to the gate electrode of each gate-commutated thyristor. The distance between the gate contact ring and the gate electrode located at different cathode rings is different, and the resistance R from the gate contact ring to the gate electrode located at different cathode rings is Mi The voltage drop caused by the negative bias voltage transferred from the gate contact ring to the gate electrode is different. The voltage V between the gate cathodes of the gate-commutated thyristors actually applied to each cathode ring is different. GKi After the gate contact ring transfers the negative bias voltage to the gate electrode of each gate-commutated thyristor, a resistance R is generated between the boundary of the gate electrode and the P+ short base region between the N+ emitter region because the gate electrode is connected to the P+ short base region and the cathode electrode is connected to the N+ emitter region. P+ , the N+ emitter region generates resistance R N+ , the electrical signal from the gate contact ring electrode to the gate electrode, the resistance R P+ , resistor R N+ A voltage drop will also occur, causing the voltage V actually applied to the gate cathodes of each gate-commutated thyristor to GKi , is the gate contact ring voltage V GK Subtract the voltage drop generated by the gate electrode, subtract the voltage drop generated by the P+ short base region between the gate electrode boundary and the cathode region, and then subtract the voltage drop generated by the N+ emitter region. Specifically, the farther away from the gate contact ring, the greater the resistance between the gate electrode and the gate contact ring, the greater the voltage drop generated by the gate contact ring transferring the negative bias to the gate electrode, and the voltage V applied to the gate cathode of the gate-commutated thyristor. GKi The smaller the gate-cathode voltage V GKi It is positively correlated with the removal speed of the cathode charge. Therefore, the charge of the cathode electrode of the gate-commutated thyristor close to the gate contact ring can be removed more quickly, and the gate-commutated thyristor close to the gate contact ring can be turned off quickly. The gate-commutated thyristor far from the gate contact ring is in the on state for a longer time and may be overloaded, which may eventually damage the entire GCT chip and reduce the turn-off current of the GCT chip. Utility Model Content

[0006] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0007] In order to achieve the above object, the present invention provides a power semiconductor device, the power semiconductor device comprises a gate contact ring and at least one gate-commutated thyristor; the gate-commutated thyristor comprises a cathode region and a gate region independently arranged in a first base region, the cathode region and the gate region are electrically connected through the first base region and the gate contact ring;

[0008] The distance between at least one of the gate-commutated thyristors and the gate contact ring is different, and the resistance of the gate region of each gate-commutated thyristor is negatively correlated with the distance between the gate region and the gate contact ring, so as to reduce the voltage difference applied by the gate contact ring to each gate-commutated thyristor.

[0009] Optionally, taking a direction perpendicular to a radial direction of the gate contact ring as a lateral direction, a width of the gate region in the lateral direction increases as a distance between the gate-commutated thyristor and the gate contact ring increases.

[0010] Optionally, the doping concentration of the gate region increases with the increase of the gate-commutated thyristor and the gate contact ring.

[0011] Optionally, the depth of the gate region increases as the gate commutated thyristor and the gate contact ring increase.

[0012] Optionally, the doping concentration of the gate region is 1E17 cm -3 -5E18cm -3 .

[0013] Optionally, the gate-commutated thyristor further includes a cathode electrode arranged on the cathode region, a gate electrode arranged on the gate region, and a drift region, a buffer region, an anode emitter region and an anode electrode arranged in sequence below the first base region.

[0014] Optionally, a first short base region is provided in the first base region, the first short base region is located below the cathode region, the first short base region and the first base region have the same conductivity type, and the doping concentration of the first short base region is greater than the doping concentration of the first base region.

[0015] Optionally, the gate region is located above the first short base region.

[0016] Optionally, the gate region extends into the first short base region.

[0017] Optionally, the cathode region of at least one of the gate-commutated thyristors is arranged in a circular shape to form at least one cathode ring, and at least one of the cathode rings is arranged sequentially in a direction away from the gate contact ring.

[0018] The novel power semiconductor device sets the resistance of the gate region according to the distance between the gate commutation thyristor and the gate contact ring. The resistance of the gate region is negatively correlated with the distance between the gate contact rings, so as to reduce the voltage drop generated by the gate contact ring applying a voltage to the cathode region of each gate commutation thyristor through the gate region, so as to reduce the voltage difference of the voltage applied by the gate contact ring to the cathode region of each gate commutation thyristor, improve the voltage uniformity of the power semiconductor device, and further improve the turn-off uniformity of the power semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A top view of the GCT chip in the related scheme.

[0021] Figure 2 for Figure 1 Longitudinal cross-section of the GCT chip along line AA.

[0022] Figure 3 Schematic diagram of the transmission of electrical signals from the gate contact ring to the gate electrode in the relevant scheme.

[0023] Figure 4 Schematic diagram of the transmission of electrical signals between the gate electrode and the cathode electrode in the related scheme.

[0024] Figure 5 is a top view of a power semiconductor device in an exemplary embodiment.

[0025] Figure 6 is a cross-sectional view of a gate-commutated thyristor in an exemplary embodiment.

[0026] Figure 7 is a cross-sectional view of a gate-commutated thyristor in an exemplary embodiment.

[0027] Figure 8 is a cross-sectional view of a gate-commutated thyristor in an exemplary embodiment.

[0028] Description of reference numerals:

[0029] 10. Gate contact ring; 20. Gate commutated thyristor; 21. First base region; 22. Cathode region; 23. Gate region; 24. Drift region; 25. Buffer region; 26. Anode emitter region; 27. First sub-base region; 30. Cathode electrode; 40. Gate electrode; 50. Anode electrode; 60. Passivation layer. DETAILED DESCRIPTION

[0030] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0032] According to an exemplary embodiment, this embodiment provides a power semiconductor device. The power semiconductor device in this embodiment may be a gate-commutated thyristor (IGCT). For example, the power semiconductor device may be an asymmetric IGCT, a reverse-conducting IGCT or a symmetric IGCT. Alternatively, the power semiconductor device in this embodiment may be other power devices with a radial or annular distribution of the cathode region.

[0033] like Figure 6 , Figure 7 , Figure 8 As shown, the power semiconductor device of this embodiment includes a gate contact ring 10 and at least one gate-commutated thyristor 20; the gate-commutated thyristor 20 includes a cathode region 22 and a gate region 23 independently arranged in a first base region 21, and the cathode region 22 and the gate region 23 are electrically connected to the gate contact ring 10 through the first base region 21; the distance between at least one gate-commutated thyristor 20 and the gate contact ring 10 is different, and the resistance of the gate region 23 of each gate-commutated thyristor 20 is negatively correlated with the distance between it and the gate contact ring 10, so as to reduce the voltage difference applied by the gate contact ring 10 to each gate-commutated thyristor 20.

[0034] The gate region 23 and the first base region 21 have the same conductivity type, and the cathode region 22 and the first base region 21 have opposite conductivity types.

[0035] For example, the first base region 21 has a P-type conductivity type, the gate region 23 has a P-type conductivity type, and the cathode region 22 has an N-type conductivity type.

[0036] A cathode electrode 30 is disposed on the cathode region 22 of the gate-commutated thyristor 20 , and a gate electrode 40 is disposed on the gate region 23 . Both the cathode electrode 30 and the gate electrode 40 are metal electrodes.

[0037] The gate contact ring 10 applies voltage to each gate-commutated thyristor 20 through the first base region 21. The metal boundary of the gate electrode 40 and the resistance generated by the first base region 21 and the cathode region 22 consume additional voltage, increasing the voltage drop. The voltage actually applied to the gate-cathode of each gate-commutated thyristor 20 is the voltage applied by the gate contact ring 10 minus the voltage of the gate electrode 40 and the additional voltage consumed by the resistance generated by the metal boundary of the gate electrode 40 and the first base region 21 and the cathode region 22.

[0038] The power semiconductor device of this embodiment sets the resistance of the gate region 23 according to the distance between the gate commutated thyristor 20 and the gate contact ring 10. The resistance of the gate region 23 is negatively correlated with the distance between the gate contact rings 10. The farther the distance between the gate commutated thyristor 20 and the gate contact ring 10 is, the smaller the resistance of the gate region 23 is. Resistance compensation is performed on the process of the gate contact ring 10 applying voltage to the gate commutated thyristor 20, so that the voltage drop generated by the gate contact ring 10 applying voltage to the gate commutated thyristors 20 at different distances is basically the same, and the voltage difference applied by the gate contact ring 10 to each gate commutated thyristor 20 is reduced, which is beneficial to improving the voltage uniformity of the power semiconductor device and improving the turn-off capability of the power semiconductor device.

[0039] The resistance of the gate region 23 may be adjusted by adjusting one or more parameters of the width, depth or doping concentration of the gate region 23 , so that the resistance of the gate region 23 that is farther from the gate contact ring 10 is smaller.

[0040] In some embodiments, Figure 6 , Figure 7 , Figure 8 As shown, with the direction perpendicular to the radial direction of the gate contact ring 10 as the lateral direction, the width of the gate region 23 in the lateral direction increases as the distance between the gate commutated thyristor 20 and the gate contact ring 10 increases.

[0041] The depth and doping concentration of the gate region 23 of each gate-commutated thyristor 20 are the same. The farther the gate-commutated thyristor 20 is from the gate contact ring 10, the greater the width of the gate region 23 of the gate-commutated thyristor 20. As the distance between the gate-commutated thyristor 20 and the gate contact ring 10 increases, the width of the gate region 23 of the gate-commutated thyristor 20 gradually increases.

[0042] In the power semiconductor device of the present embodiment, the width of the gate region 23 is set according to the distance between the gate commutated thyristor 20 and the gate contact ring 10. The wider the gate region 23 of the gate commutated thyristor 20 that is farther from the gate contact ring 10 is, the smaller the resistance of the gate region 23 is. In this way, when the gate contact ring 10 applies voltage to each gate commutated thyristor 20, the smaller the voltage drop generated by the gate region 23 of the gate commutated thyristor 20 that is farther from the gate contact ring 10 is, the voltage drop generated by the gate contact ring 10 applying voltage to the distant gate commutated thyristor 20 can be compensated, which is beneficial to improving the voltage uniformity of the power semiconductor device and improving the turn-off capability of the power semiconductor device.

[0043] In some embodiments, Figure 6 , Figure 7 , Figure 8 As shown, along the radial direction of the cathode ring 10 , the depth of the gate region 23 is positively correlated with the distance between the gate region 23 and the gate contact ring 10 .

[0044] The gate regions 23 of the gate-commutated thyristors 20 have the same width and doping concentration. The farther the distance between the gate-commutated thyristor 20 and the gate contact ring 10 is, the greater the depth of the gate region 23 of the gate-commutated thyristor 20 is. As the distance between the gate-commutated thyristor 20 and the gate contact ring 10 gradually increases, the depth of the gate region 23 of the gate-commutated thyristor 20 gradually increases, and the resistance of the gate region 23 decreases.

[0045] In the power semiconductor device of the present embodiment, the distance between the gate commutated thyristor 20 and the gate contact ring 10 sets the depth of the gate region 23. The farther the gate commutated thyristor 20 is from the gate contact ring 10, the deeper the gate region 23 is and the smaller the resistance of the gate region 23 is. Thus, when the gate contact ring 10 applies voltage to each gate commutated thyristor 20, the voltage drop generated by the gate region 23 of the gate commutated thyristor 20 that is farther from the gate contact ring 10 is smaller. The resistance of the gate region 23 is adjusted according to the distance so that the consumed resistance when the gate contact ring 10 applies voltage to each gate commutated thyristor 20 is equal, and the voltage drop generated when the gate contact ring 10 applies voltage to the gate commutated thyristor 20 at a long distance is compensated, which is beneficial to improving the voltage uniformity of the power semiconductor device and improving the turn-off capability of the power semiconductor device.

[0046] In some embodiments, Figure 6 , Figure 7 , Figure 8 As shown, the doping concentration of the gate region 23 increases as the gate commutated thyristor 20 and the gate contact ring 10 increase.

[0047] The gate regions 23 of the gate-commutated thyristors 20 have the same width and depth. The gate regions 23 of the gate-commutated thyristors 20 that are farther from the gate contact ring 10 have a greater doping concentration, a smaller resistance, and a better conductivity. When the gate contact ring 10 applies voltage to the gate-commutated thyristors 20, the gate regions 23 of the gate-commutated thyristors 20 that are farther from the gate contact ring 10 have a smaller voltage drop, thereby compensating for the voltage drop caused by the increased distance between the gate regions 10 and the gate contact ring 30, thereby improving the voltage uniformity and turn-off capability of the power semiconductor device.

[0048] In other embodiments, multiple parameters of the width, depth and doping concentration of the gate region 23 can be adjusted simultaneously. By adjusting multiple influencing factors affecting the resistance of the gate region 23 and adjusting the resistance of the gate region 23 in a coordinated manner, the resistance of the gate region 23 of the gate-commutated thyristor 20 at a distance can be further reduced, and the voltage drop of the voltage applied by the gate contact ring 10 to the gate-commutated thyristor 20 at a distance can be reduced, so that the voltage applied by the gate contact ring 10 to the gate-commutated thyristor 20 at different distances is closer, which is beneficial to improving the turn-off uniformity of the power semiconductor device.

[0049] In some embodiments, the gate region 23 of the gate-commutated thyristor 20 that is farther from the gate contact ring 10 has a larger width and a higher doping concentration.

[0050] In some embodiments, the gate region 23 of the gate-commutated thyristor 20 that is farther from the gate contact ring 10 has a deeper depth and a greater doping concentration.

[0051] In some embodiments, the gate region 23 of the gate-commutated thyristor 20 that is farther from the gate contact ring 10 has a greater depth and a deeper depth.

[0052] In some embodiments, the gate region 23 of the gate-commutated thyristor 20 that is farther from the gate contact ring has a larger width and a deeper depth, and also has a greater doping concentration.

[0053] In some embodiments, the doping concentration of the gate region 23 of the gate-commutated thyristor 20 is 1E17 cm -3 -5E18cm -3 .

[0054] In some embodiments, Figure 6 , Figure 7 , Figure 8 As shown, the gate-commutated thyristor 20 further includes a cathode electrode 30 disposed on the cathode region 22 , a gate electrode 40 disposed on the gate region 23 , and a drift region 24 , a buffer region 25 , an anode emitter region 26 and an anode electrode 50 sequentially disposed below the first base region 21 .

[0055] The drift region 24 , the buffer region 25 and the first base region 21 have opposite conductivity types, and the anode emitter region 26 and the first base region 21 have the same conductivity type.

[0056] For example, the first base region 21 has a P-type conductivity type, the drift region 24 and the buffer region 25 have an N-type conductivity type, and the anode emitter region 26 has a P-type conductivity type.

[0057] In some embodiments, Figure 6 , Figure 7 , Figure 8 As shown, a first short base region 27 is provided in the first base region 21 . The first short base region 27 is located below the cathode region 22 . The first short base region 27 and the first base region 21 have the same conductivity type. The doping concentration of the first short base region 27 is greater than the doping concentration of the first base region 21 .

[0058] If the first base region 21 has a P-type conductivity type, the first short base region 27 has a P-type conductivity type; if the first base region 21 has an N-type conductivity type, the first short base region 27 has an N-type conductivity type.

[0059] For example, the doping concentration of the P-type conductive ions in the first base region 21 is in the range of 5E14 -3 -5E16cm -3 The doping concentration of the P-type conductive ions in the first short base region 27 is in the range of 1E17 -3 -5E18cm -3 .

[0060] Along the longitudinal cross-sectional direction of the gate-commutated thyristor 20 , the first short base region 27 divides the first base region 21 into two parts arranged at the upper and lower sides of the first short base region 27 , and the gate region 23 is arranged in the first base region 21 on the side close to the cathode electrode 30 .

[0061] In some embodiments, Figure 6 As shown, the gate region 23 is located above the first short base region 27 , and the bottom surface of the gate region 23 is higher than the first short base region 27 , that is, the doping depth of the gate region 23 is less than the doping depth of the first short base region 27 .

[0062] In some embodiments, Figure 7 , Figure 8 As shown, the gate region 23 extends into the first short base region 27 , and the bottom surface of the gate region 23 is flush with the top surface of the first short base region 27 , or the bottom surface of the gate region 23 is lower than the top surface of the first short base region 27 .

[0063] In some embodiments, the power semiconductor device further includes a passivation layer 60, which covers the top surface of the first base region 21 between the gate electrode 40 and the cathode electrode 30, and the gate electrode 40 and the cathode electrode 30 are separated by the passivation layer 60. The material of the passivation layer 50 may include at least one of polyimide (PI), amorphous hydrogenated carbon (aC:H, also known as diamond-like carbon DLC) or an inorganic-organic composite material, polyparaxylene, and a phenolic resin containing polymer particles.

[0064] In some embodiments, Figure 5 As shown, the cathode region 22 of at least one gate-commutated thyristor 20 is arranged in a circumferential shape to form at least one cathode ring 200 , and the at least one cathode ring 200 is sequentially arranged in a direction away from the gate contact ring 10 .

[0065] like Figure 5 As shown, at least one cathode ring 200 and the gate contact ring 10 are arranged concentrically, the gate contact ring 10 can be arranged at the center of at least one cathode ring 20, and the gate contact ring 10 can be arranged at the outermost periphery of multiple cathode rings 20; at least one cathode ring 20 is arranged in sequence in a direction away from the gate contact ring 10.

[0066] The power semiconductor device of this embodiment adjusts the resistance of the gate region 23 of the gate-commutated thyristor 20 and uses the gate region 23 to perform resistance compensation on the gate-commutated thyristor 20, so that when the power semiconductor device is turned off, the gate contact ring 10 applies a bias to the gate-commutated thyristor 20, so that the resistance through which the gate contact ring 10 applies the bias to the gate electrode 44 of each gate-commutated thyristor 20 is closer, and the voltage drop generated by the gate contact ring 10 applying the bias to each gate-commutated thyristor 20 is equal, thereby improving the uniformity of the voltage actually applied between the gate electrode 40 and the cathode electrode 30 of each gate-commutated thyristor 20 and improving the uniformity of the commutation of the cathode electrode 30 of the gate-commutated thyristor 20, thereby improving the turn-off uniformity of the gate-commutated thyristor 20 in the power semiconductor device, and avoiding the problem that the gate-commutated thyristor 20 far from the gate contact ring 10 is in the on state for a long time and overload occurs, resulting in damage to the power semiconductor device.

[0067] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the attached claims.

Claims

1. A power semiconductor device, characterized in that: The power semiconductor device comprises a gate contact ring (10) and at least one gate commutation thyristor (20); the gate commutation thyristor (20) comprises a cathode region (22) and a gate region (23) independently arranged in a first base region (21); the cathode region (22) and the gate region (23) are electrically connected via the first base region (21) and the gate contact ring (10); The distance between at least one of the gate commutated thyristors (20) and the gate contact ring (10) is different, and the resistance of the gate region (23) of each gate commutated thyristor (20) is negatively correlated with the distance between the gate region (23) and the gate contact ring (10), so as to reduce the voltage difference applied by the gate contact ring (10) to each gate commutated thyristor (20).

2. The power semiconductor device according to claim 1, characterized in that: With the direction perpendicular to the radial direction of the gate contact ring (10) as the lateral direction, the width of the gate region (23) in the lateral direction increases as the distance between the gate commutation thyristor (20) and the gate contact ring (10) increases.

3. The power semiconductor device according to claim 1, characterized in that: The gate region (23) increases as the gate commutation thyristor (20) and the gate contact ring (10) increase.

4. The power semiconductor device according to claim 1, characterized in that: The depth of the gate region (23) increases as the gate commutation thyristor (20) and the gate contact ring (10) increase.

5. The power semiconductor device according to any one of claims 1 to 4, characterized in that: The doping concentration of the gate region (23) is 1E17 cm -3 -5E18cm -3 .

6. The power semiconductor device according to any one of claims 1 to 4, characterized in that: The gate-commutated thyristor (20) further comprises a cathode electrode (30) arranged on the cathode region (22), a gate electrode (40) arranged on the gate region (23), and a drift region (24), a buffer region (25), an anode emitter region (26), and an anode electrode (50) arranged in sequence below the first base region (21).

7. The power semiconductor device according to claim 1, characterized in that: A first short base region (27) is provided in the first base region (21), the first short base region (27) is located below the cathode region (22), the first short base region (27) and the first base region (21) have the same conductivity type, and the doping concentration of the first short base region (27) is greater than the doping concentration of the first base region (21).

8. The power semiconductor device according to claim 7, characterized in that: The gate region (23) is located above the first short base region (27).

9. The power semiconductor device according to claim 7, characterized in that: The gate region (23) extends into the first short base region (27).

10. The power semiconductor device according to any one of claims 1 to 4, characterized in that: The cathode region (22) of at least one of the gate-commutated thyristors (20) is arranged in a circular shape to form at least one cathode ring (200), and at least one of the cathode rings (200) is arranged sequentially in a direction away from the gate contact ring (10).

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