Cantilever nanometer electromechanical decoder circuit

Abstract

The utility model provides a cantilever nanometer electromechanical decoder circuit, comprising a two-dimensional array of memory cells embedded in a memory level dielectric layer and overlying a substrate; a first access line electrically connected to a corresponding row of memory cells within the two-dimensional array; and a first decoder circuit including a first cantilevered nanoelectromechanical device overlying the two-dimensional array of memory cells, embedded in the upper dielectric material layer, and having an output node electrically connected to a respective first access line selected from the first access lines.

Description

Technical Field

[0001] The utility model relates to a cantilever nano-electromechanical decoder circuit. Background Art

[0002] Nanoelectromechanical devices can control signals based on the nanoscale movement of mechanical elements under the influence of electrical bias.

[0003] It should be noted that the contents of the "Prior Art" section are used to help understand the present utility model. Part (or all) of the contents disclosed in the "Prior Art" section may not be the prior art known to those skilled in the art. The contents disclosed in the "Prior Art" section do not mean that the contents have been known to those skilled in the art before the present utility model application. Utility Model Content

[0004] The utility model provides a cantilever nano-electromechanical decoder circuit.

[0005] Some embodiments of the present invention provide a cantilever nanoelectromechanical decoder circuit, comprising a two-dimensional array of memory cells, a plurality of first access lines, and a first decoder circuit. The two-dimensional array of memory cells is embedded in a memory level dielectric layer and overlies a substrate. A plurality of first access lines, wherein each of the plurality of first access lines is electrically connected to a memory cell in a corresponding row of the memory cells in the two-dimensional array. The first decoder circuit comprises a plurality of first cantilever nanoelectromechanical devices overlying the two-dimensional array of the memory cells, wherein the plurality of first cantilever nanoelectromechanical devices are embedded in an upper dielectric material layer and have output nodes electrically connected to corresponding first access lines selected from the plurality of first access lines.

[0006] Some embodiments of the present invention provide a cantilever nanoelectromechanical decoder circuit, comprising a two-dimensional array of memory cells, a plurality of first access lines, and a first decoder circuit. The two-dimensional array of memory cells is embedded in a memory level dielectric layer and overlies a substrate. A plurality of first access lines, wherein each of the plurality of first access lines is electrically connected to a corresponding column of memory cells in the two-dimensional array. The first decoder circuit comprises a plurality of first cantilever nanoelectromechanical devices, the plurality of first cantilever nanoelectromechanical devices overlying the two-dimensional array of memory cells and configured to enable a selected first access line selected from the plurality of first access lines, wherein each of the plurality of first cantilever nanoelectromechanical devices comprises a first gate-controlled nanoelectromechanical switch and a second gate-controlled nanoelectromechanical switch. The first gate-controlled nanoelectromechanical switch is connected to each other in parallel between a first source electrode and a common output node. The second gate-controlled nanoelectromechanical switch is connected to each other in series between a second source electrode and the common output node.

[0007] Based on the above, the embodiments of the utility model are used to solve the problem that when data is stored in a memory, storing each bit of data in a storage unit of the memory will affect the reliability of the data. Because the storage unit has a more preferred state (a more preferred selection state) and a less preferred state (a less preferred selection state). Compared with the less preferred state, the more preferred state is less likely to have a retention error. Each of the binary one and the binary zero in the data is identified as a majority bit value or a minority bit value. The probability of finding a majority bit value in the data is greater than the probability of finding a minority bit value in the data. If the bit of the data has a majority bit value, the bit of the data is stored in the storage unit in a more preferred state; on the contrary, if the bit of the data has a minority bit value, the bit of the data is stored in the storage unit in a less preferred state. The reliability indicator symbol is used to indicate whether the binary one or the binary zero is the majority bit value, or conversely, to indicate whether the binary one or the binary zero is the minority bit value. The integrated circuit writes the data into the memory and reads the stored data from the memory according to the reliability indicator symbol.

[0008] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0010] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0011] Figure 1A is a vertical cross-sectional view of an exemplary structure after forming a semiconductor device, a metal interconnect structure, and a two-dimensional array of memory cells and access lines according to an embodiment of the present invention.

[0012] Figure 1B Yes Figure 1A A magnified view of a region of a two-dimensional array of storage cells in FIG.

[0013] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming an upper level dielectric material layer and a sacrificial material portion according to an embodiment of the present invention.

[0014] Figure 3is a vertical cross-sectional view of an exemplary structure after forming a metal structure of a gate-controlled nanoelectromechanical switch according to an embodiment of the present invention.

[0015] Figure 4 is a vertical cross-sectional view of an exemplary structure after forming a cavity of a gate-controlled nanoelectromechanical switch according to an embodiment of the present invention.

[0016] Figure 5 is a vertical cross-sectional view of an exemplary structure after forming a top cover and a solder material portion according to an embodiment of the present invention.

[0017] Fig. 6A It is a circuit schematic diagram and logic table of two gate-controlled nanoelectromechanical switches connected in parallel according to an embodiment of the utility model.

[0018] Figure 6B It is a circuit schematic diagram and logic table of an alternative configuration of two gate-controlled nanoelectromechanical switches connected in parallel according to an embodiment of the utility model.

[0019] Figure 6C It is a circuit schematic diagram and logic table of two gate-controlled nanoelectromechanical switches connected in series according to an embodiment of the utility model.

[0020] Fig.6D It is a circuit diagram and logic table of a composite nano-electromechanical AND switch according to an embodiment of the utility model.

[0021] Figure 7 According to the embodiment of the utility model Figure 5 Top view of a composite nanoelectromechanical AND-type switch in the illustrated exemplary configuration.

[0022] Figure 8 is a circuit diagram of an exemplary nanoelectromechanical decoder circuit according to an embodiment of the present invention.

[0023] Fig. 9A 4 is a first exemplary circuit diagram of a two-dimensional array of memory cells and a decoder circuit according to an embodiment of the present invention.

[0024] Fig. 9B 4 is a second exemplary circuit diagram of a two-dimensional array of memory cells and a decoder circuit according to an embodiment of the present invention.

[0025] Fig.10 is a flow chart showing general processing steps for manufacturing a device structure according to an embodiment of the present invention.

[0026] Description of Reference Numerals

[0027] 8: Substrate

[0028] 9: Semiconductor material layer

[0029] 12: Shallow trench isolation structure

[0030] 36: Active Zone

[0031] 38:Metal semiconductor alloy part

[0032] 50: Gate dielectric

[0033] 52: Gate electrode

[0034] 56: Dielectric gate spacer

[0035] 58: Dielectric grid cap

[0036] 60: Dielectric material layer

[0037] 80:Metal interconnect structure

[0038] 82: Metal wire structure / metal interconnect structure

[0039] 85: Nanoelectromechanical (NEM) device level metal wire structure

[0040] 85D: Drain electrode

[0041] 85G: Gate electrode / first gate electrode / second gate electrode

[0042] 85S: Source electrode / first source electrode

[0043] 86:Metal through hole structure

[0044] 87: Sacrificial material part

[0045] 88: Metal bonding structure / metal interconnect structure

[0046] 89: Cavity / Nano-Electro-Mechanical (NEM) Cavity

[0047] 90:Gate-controlled nanoelectromechanical switch / nanoelectromechanical switch

[0048] 96: Top cover

[0049] 98: Solder material part

[0050] 99: Upper cavity

[0051] 100: Storage array area

[0052] 101: Storage Cell

[0053] 102: Line level dielectric layer

[0054] 108: Second access line / access line

[0055] 110: Connecting via-level dielectric layer

[0056] 122: Metal barrier liner / connection via structure

[0057] 124: Metal filling material part / connection through-hole structure

[0058] 126: Bottom electrode

[0059] 130: Non-magnetic metal buffer layer

[0060] 140:Synthetic antiferromagnet (SAF) structure / magnetic tunnel junction structure / magnetic tunnel junction

[0061] 146: Non-magnetic tunnel barrier layer / magnetic tunnel junction structure / magnetic tunnel junction

[0062] 148: Free magnetic layer / magnetic tunnel junction structure / magnetic tunnel junction

[0063] 158: Top electrode

[0064] 162, 164: Dielectric spacer

[0065] 166: Dielectric encapsulation structure

[0066] 178: First access line / access line

[0067] 200: Sense amplifier area

[0068] 300: Power supply area

[0069] 400: Address Buffer

[0070] 401: first address buffer transistor / address buffer transistor

[0071] 600: Non-memory device area

[0072] 602: Lower level dielectric material layer

[0073] 604: memory level dielectric material layer / memory level dielectric layer

[0074] 606: upper level dielectric material layer / upper dielectric material layer

[0075] 900: Nanoelectromechanical (NEM) Device Area

[0076] 901: The first gate-controlled nanoelectromechanical switch

[0077] 902: Second gate-controlled nanoelectromechanical switch

[0078] 1010, 1020: Steps

[0079] A1, A0: Main address bits

[0080] Complementary address bits

[0081] CLA1, CLA2, CLB1, CLB2: Cantilever

[0082] D0, D1, D2, D3: Composite nano-electromechanical AND switch

[0083] GA, GB: Gate electrode / node

[0084] MANS: Modified AND-type nanoelectromechanical switch

[0085] MNNS: Modified NAND Nanoelectromechanical Switch

[0086] SA1, SA2, SB1, SB2: Fixed metal structure

[0087] V1: First power supply bias voltage

[0088] V2: Second power supply bias voltage / positive power supply voltage

[0089] V A 、V B : Gate input voltage

[0090] Vo: Output voltage / common output node / output node DETAILED DESCRIPTION

[0091] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0092] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless otherwise expressly stated, elements with the same reference number refer to the same element and are assumed to have the same material composition and the same thickness range.

[0093] Embodiments of the utility model relate to a capacitor circuit that provides self-adjusting capacitance and a method for forming the same. To provide an optimal level of decoupling capacitance, an optimal value is preferably selected for the capacitance of the decoupling capacitor. Too large or too small a value of the decoupling capacitance may adversely affect the performance of the semiconductor circuit. Inherent wafer-to-wafer variation and within-wafer variation in the process parameters of the capacitor circuit may cause large variations in the decoupling capacitance. Such process parameters may include, but are not limited to, the thickness and material composition of various films used to form the decoupling capacitor.

[0094] It may be desirable to randomly access individual memory cells in a two-dimensional array of memory cells in a random access memory device. Word line decoders and bit line decoders occupy a large device area at the level of field effect transistors. Therefore, incorporating the two-dimensional array of memory cells into the interconnect level requires a large area to be allocated for the word line decoders and bit line decoders in the related art.

[0095] According to one aspect of the present invention, to provide a bit line decoder and / or word line decoder for a two-dimensional array of memory cells, a cantilever nanoelectromechanical (NEM) device may be formed at an interconnect level. The cantilever NEM device may use a hybrid logic gate to provide an activation voltage to each of the bit lines and word lines. For example, the cantilever NEM device may be implemented at the topmost interconnect level. A limited number of address buffer transistors may be used at the transistor level on the top surface of the semiconductor layer to provide address signals that are transmitted to a cantilever NEM-based decoder circuit to enable selected bit lines and / or selected word lines, thereby enabling random access to each of the memory cells. In addition, the cantilever NEM device of the present invention enables memory "function" level performance verification of the address decoder circuit with minimal use of complementary metal-oxide-semiconductor (CMOS) devices. In some embodiments, one-time-programmable memory cells (e.g., fuses or antifuses) may be used in the memory array. In some embodiments, arrays and test structures with enhanced functional coverage may be designed with lower area overhead. In general, by forming the decoder circuit at the interconnect level, a large device area for forming transistors may be available on the surface of the semiconductor material layer in the substrate. Various embodiments of the present invention will now be described with reference to the accompanying drawings.

[0096] Reference Figure 1A and Figure 1B , showing an exemplary structure according to an embodiment of the utility model. The exemplary structure includes a substrate 8, which may be a semiconductor substrate (e.g., a commercially available silicon substrate). The substrate 8 may include a semiconductor material layer 9 located at least at an upper portion of the substrate 8. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate, or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single crystal semiconductor material (e.g., single crystal silicon). In one embodiment, the substrate 8 may include a single crystal silicon substrate including a single crystal silicon material.

[0097] A shallow trench isolation structure 12 comprising a dielectric material (e.g., silicon oxide) may be formed in an upper portion of the semiconductor material layer 9. Appropriate doped semiconductor wells (e.g., p-type wells and n-type wells) may be formed in the area laterally enclosed by a corresponding subset of the shallow trench isolation structures 12. Semiconductor devices (including, but not limited to, complementary metal oxide semiconductor (CMOS) field effect transistors) may be formed in the upper portion of the semiconductor material layer 9. Each CMOS field effect transistor may include a corresponding pair of active regions 36 (e.g., a pair of source and drain regions), a gate dielectric 50, a gate electrode 52, an optional dielectric gate cap 58, and an optional dielectric gate spacer 56. Optionally, a metal semiconductor alloy portion 38 (e.g., a metal silicide portion) may be formed on the active region 36 and / or the gate electrode 52. The shallow trench isolation structure 12 may provide electrical isolation between various semiconductor devices located on the semiconductor material layer 9.

[0098] A dielectric material layer 60 and a metal interconnect structure (82, 88) may be formed over the CMOS field effect transistor. A dielectric material layer 60 and a metal interconnect structure 80 may be formed over the CMOS field effect transistor. The metal interconnect structure 80 may include a metal line structure 82 and a metal via structure 86. The metal interconnect structure 80 may be used to provide electrical wiring for the various semiconductor devices located on the semiconductor material layer 9. The dielectric material layer 60 may include a lower level dielectric material layer 602 embedded with a subset of the metal interconnect structures 80 (the metal interconnect structures 80 provide electrical wiring between semiconductor devices located on the top surface of the semiconductor material layer 9) and a memory level dielectric material layer 604 that laterally surrounds the two-dimensional array of memory cells 101, the memory level dielectric material layer 604 overlying the lower level dielectric material layer 602 and laterally surrounding the two-dimensional array of memory cells 101.

[0099] The exemplary structure may include various device regions. For example, the various device regions may include a non-memory device region 600 including a first upper portion of the semiconductor material layer 9 and a subset of metal interconnect structures 80, which may be embedded within a portion of the lower level dielectric material layer 602 overlying the first upper portion of the semiconductor material layer 9. In addition, the various device regions may include a sense amplifier region 200 including a second upper portion of the semiconductor material layer 9 and a subset of metal interconnect structures 80, which may be embedded within a portion of the lower level dielectric material layer 602 overlying the second upper portion of the semiconductor material layer 9. In addition, the various device regions may include an address buffer region 400 including a third upper portion of the semiconductor material layer 9 and a subset of the metal interconnect structures 80, which may be embedded in a portion of the lower-level dielectric material layer 602 overlying the third upper portion of the semiconductor material layer 9. Furthermore, optionally, the various device regions may include a power supply region 300 including a fourth upper portion of the semiconductor material layer 9 and a subset of the metal interconnect structures 80, which may be embedded in a portion of the lower-level dielectric material layer 602 overlying the fourth upper portion of the semiconductor material layer 9. The region including the two-dimensional array of memory cells 101 is referred to herein as a memory array region 100.

[0100] The non-memory device area 600 may include field effect transistors for any non-memory devices and may optionally include other semiconductor devices (e.g., passive devices). In general, the non-memory device area 600 may include any device that is not directly related to the two-dimensional array of memory cells 101. In one embodiment, the non-memory device area 600 may include logic devices for logic circuitry of a system-on-a-chip (SoC) semiconductor die.

[0101] The sense amplifier region 200 includes field effect transistors that form sense amplifiers. The sense amplifiers may be electrically connected to bit lines of the two-dimensional array of memory cells 101 (the bit lines may include the first access line 178). The address buffer region 400 may include an address buffer transistor 401 that may transmit the bit line address and word line address of the selected memory cell to a cantilever nanoelectromechanical (NEM) device to be formed subsequently. The power supply region 300 may include field effect transistors that provide power supply voltages for various other circuits located on the semiconductor material layer 9.

[0102] In one embodiment, the semiconductor material layer 9 may include a single crystal silicon layer, and the field effect transistor may include a corresponding portion of the single crystal silicon layer as a semiconductor channel. As used herein, a "semiconducting" element refers to a device with a conductivity ranging from 1.0×10 -6 Siemens / cm to 1.0×10 5 Siemens / cm. As used herein, "semiconductor material" refers to a material in which the electrical conductivity in the absence of an electrical dopant is between 1.0×10 -6 Siemens / cm to 1.0×10 5 Siemens / cm range, and when appropriately doped with electrical dopants, can produce electrical conductivities ranging from 1.0 Siemens / cm to 1.0×10 5 Siemens / cm range for doped materials.

[0103] Reference Figure 1B In general, a two-dimensional array of memory cells 101 and access lines (178, 108) may be formed on a substrate 8. The access lines (178, 108) may include a first access line 178 and a second access line 108. The first access line 178 may include a bit line or a word line, and the second access line 108 may include a word line or a bit line. In one embodiment, the first access line 178 may include a bit line, and the second access line 108 may include a word line. Alternatively, the first access line 178 may include a word line, and the second access line 108 may include a bit line. In one embodiment, the first access line 178 may be electrically connected to the memory cells 101 of a corresponding row within the two-dimensional array of memory cells 101, and the second access line 108 may be electrically connected to the memory cells 101 of a corresponding row within the two-dimensional array of memory cells 101.

[0104] In general, any type of memory cell known in the art may be used for the memory cells 101 in the two-dimensional array of memory cells 101. In one embodiment, the memory cells 101 of the present invention may be selected from: dynamic random access memory cells; resistive random access memory cells; magnetic tunnel junction random access memory cells; and ferroelectric random access memory cells.

[0105] In an illustrative example, an embodiment is described herein in which the two-dimensional array of memory cells 101 includes magnetic tunnel junction memory cells. In this embodiment, the second access line 108 may be formed in the line-level dielectric layer 102, which may be the topmost dielectric layer selected from the lower-level dielectric material layer 602. A connecting via-level dielectric layer 110 may be formed above the second access line 108. A two-dimensional array of via cavities may be formed through the connecting via-level dielectric layer 110. A row of via cavities may be formed above each second access line 108. A metal barrier layer and a metal filling material may be deposited in the via cavities, and excess portions of the metal filling material and excess portions of the metal barrier layer may be removed from above a horizontal plane including the top surface of the connecting via-level dielectric layer 110. Each remaining portion of the metal filling material and each remaining portion of the metal barrier layer that fills the corresponding via cavity constitutes a connecting via structure (122, 124). A two-dimensional array of connection via structures (122, 124) may be formed through the connection via level dielectric layer 110. Each column of the connection via structures (122, 124) may contact the top surface of the corresponding second access line 108. Each connection via structure (122, 124) may include a combination of a metal barrier liner 122 and a metal filling material portion 124.

[0106] A bottom electrode material layer, a memory material layer stack, and a top electrode material layer may be formed on the two-dimensional array of the connecting via level dielectric layer 110 and the connecting via structure (122, 124). The bottom electrode material layer includes at least one non-magnetic metal material. The memory material layer stack may include an optional non-magnetic metal buffer material layer, a synthetic antiferromagnetic layer, a non-magnetic tunnel barrier material layer, and a free magnetization material layer from bottom to top. The top electrode material layer includes a top electrode material, which may include any non-magnetic material that can be used for the bottom electrode material layer.

[0107] The top electrode material layer can be patterned by applying a photoresist layer on top of the top electrode material layer and patterning the photoresist layer into a two-dimensional array of discrete photoresist material portions, and transferring the pattern in the photoresist layer through the top electrode material layer using an anisotropic etching process. The photoresist layer can then be removed by, for example, ashing. The patterned portions of the top electrode material layer form a two-dimensional array of top electrodes 158.

[0108] The memory material layer stack and the bottom electrode material layer may be patterned by performing an ion beam etch (IBE) process, which transfers the pattern in the top electrode 158 through the memory material layer stack and the bottom electrode material layer. Each patterned portion of the memory material layer stack constitutes a memory cell 101, which is a magnetic tunnel junction (MTJ) memory cell. Each patterned portion of the bottom electrode material layer constitutes a bottom electrode 126. Each MTJ memory cell may include a bottom electrode 126, a magnetic tunnel junction structure (140, 146, 148), and a top electrode 158. Each memory cell 101 may include an optional non-magnetic metal buffer layer 130 and a magnetic tunnel junction structure (140, 146, 148). Each magnetic tunnel junction ( 140 , 146 , 148 ) may include a synthetic antiferromagnet (SAF) structure 140 , a nonmagnetic tunnel barrier layer 146 , and a free magnetization layer 148 .

[0109] At least one dielectric spacer (162, 164) may be formed around each memory cell 101. A dielectric encapsulation structure 166 may be formed around the two-dimensional array of memory cells 101. A memory level dielectric material layer 604 may be deposited and planarized to provide a horizontal top surface. First access lines 178 may be formed in an upper portion of the memory level dielectric material layer 604 such that each first access line 178 contacts a row of top electrodes 158. The first access lines 178 may be formed as bit lines or word lines.

[0110] Reference Figure 2 , an additional dielectric material layer 60 is formed on the two-dimensional array of memory cells 101. The additional dielectric material layer 60 is referred to herein as an upper-level dielectric material layer 606. The upper-level dielectric material layer 606 includes an interlayer dielectric (ILD) material, such as undoped silicate glass, doped silicate glass, or silicon nitride. An additional metal interconnect structure 80 is formed in the upper-level dielectric material layer 606. The additional metal interconnect structure 80 can be configured to provide electrical wiring for a cantilever nanoelectromechanical device to be formed subsequently.

[0111] According to the aspect of the utility model, a cavity can be formed in the topmost dielectric material layer selected from the upper level dielectric material layer 606 by, for example, applying a photoresist layer on the topmost dielectric material layer and patterning the photoresist layer, and transferring the pattern in the photoresist layer to the topmost dielectric material layer by performing an isotropic etching process. The photoresist layer can then be removed by, for example, ashing. The cavity can then be filled with a sacrificial filling material to form a sacrificial material portion 87. The sacrificial material portion 87 includes a material that can then be selectively removed relative to the material of the upper level dielectric material layer 606. In one embodiment, the sacrificial material portion 87 may include a semiconductor material (e.g., silicon or silicon-germanium alloy) or a dielectric material (e.g., porous organic silicate glass, polymer material, amorphous carbon, diamond-like carbon (DLC), etc.). The top surface of the sacrificial material portion 87 can be formed in a horizontal plane including the topmost surface of the upper level dielectric material layer 606. In general, the sacrificial material portion 87 may be formed within the upper portion of the upper level dielectric material layer 606. The shape of the sacrificial material portion 87 may be the same as the shape of the cavity for accommodating the movable portion of the cantilever that is subsequently formed as a component of the cantilever nanoelectromechanical device. The thickness (i.e., height) of the sacrificial material portion 87 may range from 50 nanometers to 1,000 nanometers (e.g., from 100 nanometers to 500 nanometers), although smaller thicknesses or larger thicknesses may also be used.

[0112] Reference Figure 3 , a via cavity and a line cavity may be formed in the topmost dielectric material layer of the upper level dielectric material layer 606 and in the sacrificial material portion 87. For example, a first photoresist layer may be applied over the upper level dielectric material layer 606 and the sacrificial material portion 87, and the first photoresist layer may be photolithographically patterned to form discrete openings (e.g., circular openings) in the first photoresist layer. A first anisotropic etching process may be performed to form a via cavity through the topmost dielectric material layer on the top surface of a corresponding one of the metal line structures 82 embedded in the upper level dielectric material layer 606. The first photoresist layer may then be removed by, for example, ashing. A second photoresist layer may be applied over the upper level dielectric material layer 606 and the sacrificial material portion 87, and the second photoresist layer may be photolithographically patterned to form a line opening in the second photoresist layer. A second anisotropic etching process may be performed to form a line cavity in an upper portion of the topmost dielectric material layer and in an upper portion of the sacrificial material portion of the upper level dielectric material layer 606. The second photoresist layer may then be removed by, for example, ashing.

[0113] At least one metal material may be deposited in the via cavity and in the line cavity, and excess portions of the at least one metal material may be removed from above a horizontal plane including the topmost surface of the upper level dielectric material layer 606 by a planarization process, which may use a chemical mechanical polishing process. The remaining portion of the at least one metal material filling the via cavity constitutes an additional metal via structure 86. The remaining portion of the at least one metal material filling the line cavity comprises a nanoelectromechanical device level (NEM device level) metal line structure 85, which is a component of a gate-controlled nanoelectromechanical switch. The NEM device level metal line structure 85 may include a cantilever metal structure partially formed in a corresponding one of the sacrificial material portions 87 and a NEM device level metal line embedded in the upper level dielectric material layer 606. A subset of the NEM device level metal lines may contact a corresponding one of the sacrificial material portions 87. The additional remaining portion of the at least one metallic material embedded in the upper level dielectric material layer 606 may include a metallic bonding structure 88, which may be, for example, a controlled collapse chip connection (C4) bonding pad.

[0114] Reference Figure 4 , the sacrificial material portion 87 may be selectively removed relative to the material of the upper level dielectric material layer 606, the material of the NEM device level metal line structure 85, and the material of the metal bonding structure 88. In an exemplary embodiment, in which the sacrificial material portion 87 comprises a semiconductor material (e.g., amorphous silicon or polycrystalline silicon), the sacrificial material portion 87 may be selectively removed relative to the material of the upper level dielectric material layer 606, the material of the NEM device level metal line structure 85, and the material of the metal bonding structure 88 using a wet etching process using tetramethylammonium hydroxide (TMAH). A cavity may be formed in the volume from which the sacrificial material portion 87 is removed. The cavity is referred to herein as a nanoelectromechanical (NEM) cavity 89.

[0115] After removing the sacrificial material portion 87, the free end of the cantilever metal structure is exposed to the NEM cavity 89. The combination of the NEM device level metal wire structure 85 and the NEM cavity 89 constitutes a nanoelectromechanical device. The region in which the nanoelectromechanical device is disposed is referred to herein as a nanoelectromechanical (NEM) device region 900. A subset of the NEM device level metal wire structures 85 including a respective major portion located in a respective one of the NEM cavities 89 may include a cantilever metal structure. The cantilever metal structure is a movable metal structure that can be deformed by bending in response to an external electrical bias applied to a respective fixed metal structure (e.g., a gate electrode structure) that is one of the NEM device level metal wire structures 85. The fixed metal structure is embedded in the upper level dielectric material layer 606 in a manner that is not easily bent or deformed. In one embodiment, one, more, and / or each of the nanoelectromechanical (NEM) devices may include a respective cantilever metal structure and at least one fixed metal structure. In embodiments where the NEM device comprises a cantilever metal structure, such NEM device is referred to herein as a cantilever nanoelectromechanical (NEM) device. According to aspects of the present invention, one, more, and / or each of the cantilever NEM devices may comprise a corresponding plurality of cantilever gate-controlled nanoelectromechanical switches, wherein the corresponding plurality of cantilever gate-controlled nanoelectromechanical switches comprises a corresponding cantilever metal structure.

[0116] Reference Figure 5 Optionally, a cap 96 may be attached to the top side of the upper level dielectric material layer 606 in a manner that covers all or most of the NEM devices. An overlying cavity 99 may be formed between the cap and the NEM devices. The height of the overlying cavity 99 may range from 100 nanometers to 5 micrometers (e.g., from 200 nanometers to 2 micrometers), but smaller heights or larger heights may also be used.

[0117] Solder material portion 98 may be attached to metal bonding structure 88. Solder material portion 98 may then be used to attach a semiconductor die including the exemplary structure to another structure, such as an interposer or a package substrate.

[0118] Reference Fig. 6A, according to an embodiment of the present invention, a circuit schematic diagram of two gate-controlled nanoelectromechanical switches 90 connected in parallel and an associated logic table are shown. The two gate-controlled nanoelectromechanical switches 90 are connected to each other in a parallel connection between a source electrode to which a positive power supply voltage +V1 is applied and a common output node that generates an output voltage Vo. Each of the gate-controlled nanoelectromechanical switches 90 includes: a corresponding source electrode 85S, including a cantilever (CLA1 or CLB1) with a free end; a corresponding drain electrode 85D, including a fixed metal structure (SA1 or SB1) near the free end; and a corresponding gate electrode 85G (represented by a node GA or by a node GB), close to the surface of the corresponding source electrode 85S and not in contact with the corresponding source electrode 85S.

[0119] In the circuit shown, the voltage applied to the source electrode 85S may be a positive power supply voltage +V1, and the two gate-controlled nanoelectromechanical switches 90 may be normally closed, that is, when the gate input voltage (V A or V B ) is zero volts, providing electrical connection between the source electrode 85S and the drain electrode 85D through direct physical contact between the source electrode 85S and the drain electrode 85D. A or V B ) becomes a positive gate voltage (e.g., +Vg volts) sufficient to repel the positively charged cantilever (CLA1 or CLB1) from the gate electrode 85G, the cantilever (CLA1 or CLB1) deforms and the physical contact between the cantilever (CLA1 or CLB1) and the corresponding fixed metal structure (SA1 or SB1) is broken.

[0120] In one embodiment, a positive voltage (e.g., +Vg volts) may be applied to the gate electrode (GA or GB) for a logic "1" input of the gate bias voltage, and 0 volts may be applied to the gate electrode (GA or GB) for a logic "0" of the gate bias voltage. The positive gate voltage +Vg volts may be in the range of from 2 volts to 100 volts (e.g., from 5 volts to 30 volts). In the case of the two gate-controlled nanoelectromechanical switches 90 connected in parallel, Fig. 6A In the NEM circuit shown, the first gate electrode G A and the second gate electrode G BBoth need to be charged with a positive gate voltage to repel the two positively charged cantilevers (CLA1 or CLB1) from the two contact locations to electrically float the output node Vo. In other words, the presence of one or more closed switches will cause the output voltage Vo to be the positive power supply voltage +V1 (which is the voltage applied to both cantilevers (CLA1 and CLB1)) due to the zero voltage applied to either of the two gate electrodes (GA and GB). Only the application of a positive gate voltage to both of the two gate electrodes (GA and GB) will cause the output voltage Vo to electrically float. Therefore, Fig. 6A Output table shown. Fig. 6A The nanoelectromechanical device shown produces a modified NAND output, where the output is floating when all gate inputs are logic "1". Fig. 6A The nanoelectromechanical device shown is modified to provide N nanoelectromechanical switches 90 connected in parallel, which produces a modified NAND-type output, where the output is floating when all gate inputs are logic "1", and where N is any positive integer greater than one.

[0121] Reference Figure 6B , according to an embodiment of the present invention, a circuit schematic diagram and an associated logic table of an alternative configuration of two gate-controlled nanoelectromechanical switches 90 connected in parallel are shown. In the alternative configuration, the two gate-controlled nanoelectromechanical switches 90 can be formed in the following configuration: in the configuration, when the gate electrodes (GA and GB) are not electrically biased (i.e., at 0 volts and do not cause cantilever deformation), the two gate-controlled nanoelectromechanical switches 90 are turned on. The two gate-controlled nanoelectromechanical switches 90 are connected to each other in a parallel connection between a source electrode to which a positive power supply voltage +V1 is applied and a common output node that generates an output voltage Vo. Each of the gate-controlled nanoelectromechanical switches 90 includes: a corresponding source electrode 85S, including a cantilever (CLA1 or CLB1) having a free end; a corresponding drain electrode 85D, including a fixed metal structure (SA1 or SB1) near the free end; and a corresponding gate electrode 85G (represented by node GA or by node GB), close to the surface of the corresponding source electrode 85S and not in contact with the corresponding source electrode 85S.

[0122] In the circuit shown, the voltage applied to the source electrode 85S may be a positive power supply voltage +V1, and the two gate-controlled nanoelectromechanical switches 90 may be normally open, that is, when the gate input voltage (V A or V B ) is zero volts to provide electrical disconnection between the source electrode 85S and the drain electrode 85D by the absence of direct physical contact between the source electrode 85S and the drain electrode 85D. In this embodiment, a negative gate voltage offset scheme can be used to generate a suitable gate bias voltage.

[0123] In one embodiment, a negative voltage (e.g., -Vg' volts) may be applied to the gate electrode (GA or GB) for a logic "0" input of the gate bias voltage, and 0 volts may be applied to the gate electrode (GA or GB) for a logic "1" of the gate bias voltage. A and V B ) becomes a negative gate voltage (e.g., -Vg' volts) sufficient to pull the positively charged cantilever (CLA1 or CLB1) toward the gate electrode 85G, the cantilever (CLA1 or CLB1) deforms and the cantilever (CLA1 or CLB1) contacts the corresponding fixed metal structure (SA1 or SB1). The negative gate voltage -Vg' volts may be in the range of from -100 volts to -2 volts (e.g., from -30 volts to -5 volts). In the case of the two gate-controlled nanoelectromechanical switches 90 connected in parallel, Figure 6B In the NEM circuit shown, the first gate electrode G A and the second gate electrode G B Both need to be at logic "1" (e.g., zero voltage) to electrically disconnect both of the two positively charged cantilevers (CLA1 or CLB1) from the output node and electrically float the output node Vo. In other words, the presence of one or more closed switches causes the output voltage Vo to be the positive power supply voltage +V1 (which is the voltage applied to both of the cantilevers (CLA1 and CLB1)) due to the negative bias voltage applied to either of the two gate electrodes (GA and GB). Only by applying a voltage representing logic "1" (e.g., 0 volts) to both of the two gate electrodes (GA and GB) will the output voltage Vo electrically float. Therefore, Figure 6B Output table shown. Figure 6B The nanoelectromechanical device shown produces a modified NAND-type output, where the output is floating when all gate inputs are logic "1". Figure 6B The nanoelectromechanical device shown is modified to provide N nanoelectromechanical switches 90 connected in parallel, which produces a modified NAND-type output, where the output is floating when all gate inputs are logic "1", and where N is any positive integer greater than one.

[0124] Reference Figure 6C, according to an embodiment of the utility model, a circuit schematic diagram and a logic table of two gate-controlled nanoelectromechanical switches 90 connected in series are shown. The two gate-controlled nanoelectromechanical switches 90 are connected to each other in a series connection between a source electrode to which a positive power supply voltage +V2 is applied and an output node that generates an output voltage Vo. Each of the gate-controlled nanoelectromechanical switches 90 includes: a corresponding source electrode 85S, including a cantilever (CLA2 or CLB2) with a free end; a corresponding drain electrode 85D, including a fixed metal structure (SA2 or SB2) near the free end; and a corresponding gate electrode 85G (represented by a node GA or by a node GB), close to the surface of the corresponding source electrode 85S and not in contact with the corresponding source electrode 85S.

[0125] In the circuit shown, the voltage applied to the source electrode 85S may be a positive power supply voltage +V2, and the two gate-controlled nanoelectromechanical switches 90 may be normally open, that is, when the gate input voltage (V A or V B ) is zero volts, the source electrode 85S is electrically disconnected from the drain electrode 85D. A and V B ) becomes a positive gate voltage (e.g., +Vg volts) sufficient to pull the positively charged cantilever (CLA1 or CLB1) toward the gate electrode 85G, the cantilever (CLA1 or CLB1) deforms and contacts the corresponding fixed metal structure (SA1 or SB1).

[0126] In one embodiment, a positive voltage (e.g., +Vg volts) may be applied to the gate electrode (GA or GB) for a logic "1" input of the gate bias voltage, and 0 volts may be applied to the gate electrode (GA or GB) for a logic "0" of the gate bias voltage. The positive gate voltage +Vg volts may be in the range of from 2 volts to 100 volts (e.g., from 5 volts to 30 volts). In the embodiment comprising the two gate-controlled nanoelectromechanical switches 90 connected in series, Figure 6C In the NEM circuit shown, the first gate electrode G A and the second gate electrode G B Both need to be charged with a positive gate voltage to pull the two positively charged cantilevers (CLA1 or CLB1) to the corresponding contact position so that the output node Vo is equal to the positive supply voltage V2. In other words, the presence of one or more open switches will cause the output voltage Vo to float electrically due to the zero voltage applied to either of the two gate electrodes (GA and GB). Only the application of a positive gate voltage to both of the two gate electrodes (GA and GB) will make the output voltage Vo the same as the positive supply voltage V2. Therefore, Figure 6C Output table shown. Figure 6CThe nanoelectromechanical device shown produces a modified AND-type output, where the output is floating when any of the gate inputs includes a logical "0". Figure 6C The nanoelectromechanical device shown is modified to provide N nanoelectromechanical switches 90 connected in series, which produces a modified AND-type output, wherein the output is floating when any of the gate inputs includes a logical "0", and wherein N is any positive integer greater than one.

[0127] Reference Fig.6D According to the embodiment of the utility model, a composite nano-electromechanical AND switch and its logic table are shown. Fig. 6A or Figure 6B The N gate-controlled nanoelectromechanical switches 90 connected in parallel as shown in FIG. Figure 6C The N gate-controlled nanoelectromechanical switches 90 connected in series as shown in are combined to form a composite nanoelectromechanical AND-type switch, so that the output node for generating the output voltage Vo is shared. In this embodiment, for all gate input conditions where at least one gate input voltage includes a logic "0", the output voltage may be a first power supply bias voltage V1; and for gate input conditions where all gate input voltages include a logic "1", the output voltage may be a second power supply bias voltage V2. Generally speaking, the second power supply bias voltage V2 is different from the first power supply bias voltage V1.

[0128] exist Fig. 6A or Figure 6B shown in and incorporated into Fig.6D The N gate-controlled nanoelectromechanical switches 90 in the composite nanoelectromechanical AND type switch are referred to herein as N first gate-controlled nanoelectromechanical switches 901. Figure 6C shown in and incorporated into Fig.6D The N gate-controlled nanoelectromechanical switches 90 in the composite nanoelectromechanical AND switch are referred to herein as N second gate-controlled nanoelectromechanical switches 902 .

[0129] In it Fig.6D The composite nanoelectromechanical AND type switch includes reference Fig. 6A In the embodiment of the modified NAND nanoelectromechanical switch described, the gate inputs of the N second gate-controlled nanoelectromechanical switches 902 connected in series (forming the modified AND nanoelectromechanical switch) can be directly connected to the corresponding gate inputs in the modified NAND nanoelectromechanical switch. Fig.6D The composite nanoelectromechanical AND type switch includes reference Figure 6BIn the illustrated embodiment of the modified NAND nanoelectromechanical switch, the gate input of the modified NAND nanoelectromechanical switch can be level-shifted relative to the gate inputs of the N second gate-controlled nanoelectromechanical switches 902 connected in series (forming the modified AND nanoelectromechanical switch).

[0130] Although the present invention is illustrated using an example in which N is 2, N may be any positive integer greater than 1. For example, N may be in the range of 2 to 30.

[0131] Figure 7 According to the embodiment of the utility model Figure 5 A top view of a composite nanoelectromechanical AND switch in an exemplary structure is shown. Fig.6D The composite nanoelectromechanical AND-type switch shown in .

[0132] The composite nanoelectromechanical AND switch may include a modified NAND nanoelectromechanical switch MNNS and a modified AND nanoelectromechanical switch MANS, wherein the modified NAND nanoelectromechanical switch MNNS and the modified AND nanoelectromechanical switch MANS are configured to share a fixed metal structure connected to an output node generating an output voltage Vo. The modified NAND nanoelectromechanical switch MNNS includes N first gate-controlled nanoelectromechanical switches 901 connected in parallel, each of the N first gate-controlled nanoelectromechanical switches 901 including a cantilever (CLA1 or CLB1) implementing a corresponding source electrode 85S and including a fixed metal structure (SA1 or SB1) implementing a corresponding drain electrode 85D. The modified AND nanoelectromechanical switch MANS includes N second gate-controlled nanoelectromechanical switches 902 connected in series, each of the N second gate-controlled nanoelectromechanical switches 902 including a cantilever (CLA2 or CLB2) implementing a corresponding source electrode 85S and including a fixed metal structure (SA2 or SB2) implementing a corresponding drain electrode 85D. The source electrodes 85S of the N first gate-controlled nanoelectromechanical switches 901 are connected to an electrical node providing a first power bias voltage V1. The source electrode 85S of one of the N second gate-controlled nanoelectromechanical switches 902 is connected to an electrical node providing a second power bias voltage V2.

[0133] Generally, multiple composite nanoelectromechanical AND switches can be formed to control access lines (e.g. Figure 1A and Figures 2 to 5178 and / or the second access line 108 shown in . The total number of composite nanoelectromechanical AND switches may be the same as the total number of access lines. For example, in an embodiment in which a P×Q array of memory cells 101 is arranged to be randomly accessed via P rows of word lines and Q columns of bit lines, a first decoder circuit including Q composite nanoelectromechanical AND switches may be provided to serve as a bit line decoder circuit, and a second decoder circuit including P composite nanoelectromechanical AND switches may be provided to serve as a word line decoder circuit. In which the integer Q is greater than 2 for the positive integer N (N-1) and not more than 2 N In the embodiment of the invention, N bit addresses can be used to address each of the Q composite nanoelectromechanical AND switches. If for a positive integer M, the integer P is greater than 2 (M-1) and not more than 2 M , then each of the Q composite nanoelectromechanical AND switches can be addressed using an M-bit address. In an exemplary embodiment, M may be an integer in the range of 2 to 20, N may be an integer in the range of 2 to 20, and P may be an integer in the range of 2 2 to 2 20 An integer in the range of, and Q can be between 2 2 to 2 20 An integer in the range of .

[0134] Reference Figure 8 , a circuit schematic diagram of an exemplary nanoelectromechanical decoder circuit including a system of N bit addresses and including Q composite nanoelectromechanical AND type switches is shown. In the example shown, N is 2 and Q is 4. The Q composite nanoelectromechanical AND type switches are labeled D0, D1, D2, and D3. The two primary address bits are labeled A0 and A1. The two complementary address bits are labeled and The signals for the address bits and the complementary address bits may be provided by Figure 1A and Figures 2 to 5 The address buffer transistor 401 in the address buffer 400 shown in FIG. 1 is generated and can be transmitted to the various nanoelectromechanical switches 90 (in FIG. 1 ) in the implementation of the nanoelectromechanical decoder circuit. Fig.6D and Figure 7 The metal structure of the gate electrode 85G (eg Figure 1A and Figures 2 to 5 The NEM device level metal line structure 85 is shown in FIG.

[0135] The nanoelectromechanical decoder circuit of the present invention can be used as a bit line decoder circuit and / or a word line decoder circuit. Although the present invention is described using an embodiment in which N is 2 and Q is 4, as discussed above, N and Q (and M and P) can generally be larger numbers. In an illustrative example, a bit line decoder circuit configured to address Q bit lines using a system of N bit addresses can be provided, and a word line decoder circuit configured to address P word lines using a system of M bit addresses can be provided.

[0136] Fig. 9A 1 is a first exemplary circuit diagram of a two-dimensional array of memory cells 101 and a decoder circuit according to an embodiment of the present invention. Optionally, each memory cell 101 may include a cell access transistor, which may be a thin film transistor using a semiconductor metal oxide channel and formed in a memory level dielectric material layer 604 (e.g., Figure 1A and Figures 2 to 5 shown in ).

[0137] In general, multiple decoder circuits may be used, each of which may include a corresponding nanoelectromechanical decoder circuit. A first decoder circuit may be configured to randomly access a selected first access line 178 (e.g., a selected bit line) selected from the N first access lines. A second decoder circuit may be configured to randomly access a selected second access line 108 (e.g., a selected word line) selected from the M first access lines.

[0138] The address output signal may be generated from an address buffer transistor 401 disposed in the address buffer 400. The address buffer transistor 401 may generate a bit line select signal for a bit line decoder, which enables a selected bit line. The bit line select signal may be in the form of a suitable voltage applied to a metal line that is configured to transmit a primary address bit and a complementary address bit. In one embodiment, N primary address bits and N complementary address bits may be generated for the bit line select signal.

[0139] The address buffer transistor 401 may generate a word line select signal for a word line decoder, which enables the selected word line. The word line select signal may be in the form of a suitable voltage applied to a metal line that is configured to transmit the primary address bits and the complementary address bits to the word line decoder. In one embodiment, M primary address bits and M complementary address bits may be generated for the bit line select signal.

[0140] Fig. 9B1 is a second exemplary circuit diagram of a two-dimensional array of memory cells 101 and a decoder circuit according to an embodiment of the present invention. The nanoelectromechanical decoder circuit of the present invention can also be used as a sensor decoder circuit. In some embodiments, since the bit line decoder and the sensor decoder are connected to the same set of bit lines (i.e., the first access line 178), the bit line decoder circuit and the sensor decoder circuit can use the same addressing system. In this embodiment, the same set of address buffer transistors 401 can be used to control the bit line decoder circuit and the sensor decoder circuit.

[0141] Common Reference Figures 1A to 9B , a nanoelectromechanical decoder circuit including a composite nanoelectromechanical AND type switch and providing a composite logic AND gate can be used to address any array of memory cells 101 using at least one set of access lines (178, 108). Such a memory cell 101 may be, but is not necessarily, a dynamic random access memory cell, a resistive random access memory cell, a magnetic tunnel junction random access memory cell, or a ferroelectric random access memory cell. The total number of output signals generated by the address buffer transistor 401 can be twice the number of bits in the address system (i.e., 2N for a system with N bit addresses). Therefore, the area occupied by the address buffer transistor 401 can be small, and the excess area generated by reducing the area occupied by the address buffer transistor 401 can be advantageously used to provide additional semiconductor devices. In other words, the address buffer area 400 can be increased by reducing the area. Figure 1A and Figures 2 to 5 The area of ​​the non-memory device region 600 is shown in FIG.

[0142] Common Reference Figures 1A to 9B According to various embodiments of the present invention, a device structure is provided, which includes: a two-dimensional array of memory cells 101, embedded in a memory level dielectric layer 604 and overlying a substrate 8; a first access line 178, electrically connected to a corresponding row of memory cells 101 within the two-dimensional array; and a first decoder circuit, including a first cantilever nanoelectromechanical device, which is overlying the two-dimensional array of memory cells 101, embedded in an upper dielectric material layer 606 and having an output node electrically connected to a corresponding first access line selected from the first access line 178.

[0143] In one embodiment, each of the first cantilever electromechanical devices is configured to generate a corresponding output for enabling or disabling a corresponding first access line 178; and the first decoder circuit is configured to enable a selected first access line 178 selected from the first access lines 178 without enabling any other first access lines 178 other than the selected first access line 178.

[0144] In one embodiment, each of the first cantilever nanoelectromechanical devices includes: first gate-controlled nanoelectromechanical switches 901, which are connected to each other in parallel between the first source electrode 85S and the common output node Vo; and second gate-controlled nanoelectromechanical switches 902, which are connected to each other in series between the second source electrode 85S and the common output node Vo.

[0145] In one embodiment, each of the first gate-controlled nanoelectromechanical switch 901 and the second gate-controlled nanoelectromechanical switch 902 includes: a corresponding source electrode 85S, including a cantilever having a free end; a corresponding drain electrode 85D, including a fixed metal structure near the free end; and a corresponding gate electrode 85G, close to the surface of the corresponding source electrode 85S and not in contact with the corresponding source electrode 85S.

[0146] In one embodiment, each of the first gate-controlled nanoelectromechanical switch 901 and the second gate-controlled nanoelectromechanical switch 902 includes a cavity 89 in which a free end of the corresponding source electrode 85S is suspended and a surface portion of the fixed metal structure is physically exposed.

[0147] In one embodiment, the first gate-controlled nanoelectromechanical switch 901 includes a first gate electrode 85G; the second gate-controlled nanoelectromechanical switch 902 includes a second gate electrode 85G; and each of the first gate electrodes 85G is electrically shorted (ie, electrically connected) to a corresponding one of the second gate electrodes 85G.

[0148] In one embodiment, the first gate-controlled nanoelectromechanical switch 901 includes a first gate electrode 85G; the second gate-controlled nanoelectromechanical switch 902 includes a second gate electrode 85G; and the voltage applied to the first gate electrode 85G is level-shifted relative to the voltage applied to the second gate electrode 85G.

[0149] In one embodiment, the device structure includes a first address buffer transistor 401 located on the substrate 8 and configured to generate a set of output signals applied to each of the first gate electrode 85G and the second gate electrode 85G.

[0150] In one embodiment, the first address buffer transistor 401 is configured to generate N digital address outputs; and each of the first cantilever nanoelectromechanical devices includes N first gate-controlled nanoelectromechanical switches 901 and N second gate-controlled nanoelectromechanical switches 902. In one embodiment, the total number of first cantilever nanoelectromechanical devices in the first decoder circuit is between 2 (N-1) +1 to 2 N within the range.

[0151] In one embodiment, the first access line 178 is a bit line and the first decoder circuit includes a bit line address decoder circuit.

[0152] In one embodiment, the device structure includes: a second access line 108 electrically connected to a corresponding column of memory cells 101 in the two-dimensional array; and a second decoder circuit including a second cantilever nanoelectromechanical device overlying the two-dimensional array of memory cells 101, embedded in the upper dielectric material layer 606, and having an output node electrically connected to a corresponding second access line selected from the second access lines 108. In one embodiment, the second access line 108 is a word line, and the second decoder circuit includes a word line address decoder circuit.

[0153] According to another aspect of the present invention, a device structure is provided, which includes: a two-dimensional array of memory cells 101, embedded in a memory level dielectric layer 604 and overlying a substrate 8; a first access line 178, electrically connected to the memory cells 101 of the corresponding row within the two-dimensional array; and a first decoder circuit, including a first cantilever nanoelectromechanical device, which is overlying the two-dimensional array of memory cells 101 and is configured to enable a selected first access line selected from the first access line 178, wherein each of the first cantilever nanoelectromechanical devices includes: a first gate-controlled nanoelectromechanical switch 901, which is connected to each other in parallel between a first source electrode 85S and a common output node Vo; and a second gate-controlled nanoelectromechanical switch 902, which is connected to each other in series between a second source electrode 85S and the common output node Vo.

[0154] In one embodiment, each of the first gate-controlled nanoelectromechanical switch 901 and the second gate-controlled nanoelectromechanical switch 902 includes: a corresponding source electrode 85S, including a cantilever having a free end; a corresponding drain electrode 85D, including a fixed metal structure near the free end; and a corresponding gate electrode 85G, close to the surface of the corresponding source electrode 85S and not in contact with the corresponding source electrode 85S.

[0155] In one embodiment, each of the first gate-controlled nanoelectromechanical switch 901 and the second gate-controlled nanoelectromechanical switch 902 includes a cavity 89, a free end of the corresponding source electrode 85S is suspended in the cavity 89 and a surface portion of the fixed metal structure is physically exposed to the cavity 89; and the device structure includes a top cover 96, which covers each of the cavity 89 of the first gate-controlled nanoelectromechanical switch 901 and the cavity 89 of the second gate-controlled nanoelectromechanical switch 902.

[0156] Reference Fig.10 , a flow chart illustrating general processing steps for manufacturing a device structure according to an embodiment of the present invention.

[0157] Refer to step 1010 and Figure 1A and Figure 1B A two-dimensional array of memory cells 101 and first access lines 178 may be formed on the substrate 8. The first access lines 178 are electrically connected to the memory cells 101 of the corresponding row in the two-dimensional array.

[0158] Refer to step 1020 and Figures 2 to 9B A first decoder circuit including a first cantilever nanoelectromechanical device may be formed on the two-dimensional array of memory cells 101. The first cantilever nanoelectromechanical device has an output node electrically connected to a corresponding first access line selected from the first access lines 178.

[0159] According to aspects of the present invention, a composite AND gate may be provided using a combination of cantilever NEM switches connected in parallel and cantilever NEM switches connected in series. The composite AND gate may be used to provide a decoder circuit for selecting access lines for a two-dimensional array of memory cells 101. The decoder circuit may be constructed within the level of dielectric material layer 60 (e.g., the level of the topmost dielectric material layer). In this way, device area may be freed up at the level of field effect transistors, and additional area may be allocated to form other semiconductor devices (e.g., devices formed in non-memory device area 600).

[0160] In some embodiments, a device structure includes a two-dimensional array of memory cells embedded in a memory level dielectric layer and overlying a substrate; a plurality of first access lines, wherein each of the plurality of first access lines is electrically connected to a corresponding row of memory cells in the two-dimensional array; and a first decoder circuit, including a plurality of first cantilever nanoelectromechanical devices overlying the two-dimensional array of memory cells, wherein the plurality of first cantilever nanoelectromechanical devices are embedded in an upper dielectric material layer and have output nodes electrically connected to corresponding first access lines selected from the plurality of first access lines.

[0161] In some embodiments, each of the plurality of first cantilever nanoelectromechanical devices is configured to generate a corresponding output for enabling or disabling the corresponding first access line; and the first decoder circuit is configured to enable a selected first access line selected from the plurality of first access lines without enabling any other first access lines among the plurality of first access lines except the selected first access line.

[0162] In some embodiments, each of the plurality of first cantilever nanoelectromechanical devices comprises: a first gate-controlled nanoelectromechanical switch connected to each other in parallel between a first source electrode and a common output node; and a second gate-controlled nanoelectromechanical switch connected to each other in series between a second source electrode and the common output node.

[0163] In some embodiments, each of the first gate-controlled nanoelectromechanical switch and the second gate-controlled nanoelectromechanical switch includes: a corresponding source electrode, including a cantilever having a free end; a corresponding drain electrode, including a fixed metal structure near the free end; and a corresponding gate electrode, close to the surface of the corresponding source electrode and not in contact with the corresponding source electrode.

[0164] In some embodiments, each of the first gate-controlled nanoelectromechanical switch and the second gate-controlled nanoelectromechanical switch includes a cavity, the free end of the corresponding source electrode is suspended in the cavity and a surface portion of the fixed metal structure is physically exposed to the cavity.

[0165] In some embodiments, the first gate-controlled nanoelectromechanical switch includes a first gate electrode; the second gate-controlled nanoelectromechanical switch includes a second gate electrode; and each of the first gate electrodes is electrically connected to a corresponding one of the second gate electrodes.

[0166] In some embodiments, the device structure further includes a first address buffer transistor located on the substrate and configured to generate a set of output signals applied to each of the first gate electrode and the second gate electrode.

[0167] In some embodiments, the first address buffer transistor is configured to generate N digital address outputs; and each of the plurality of first cantilever nanoelectromechanical devices includes N first gate-controlled nanoelectromechanical switches and N second gate-controlled nanoelectromechanical switches.

[0168] In some embodiments, the total number of the plurality of first cantilever nanoelectromechanical devices in the first decoder circuit is between 2 (N-1) +1 to 2 N within the range.

[0169] In some embodiments, the plurality of first access lines are bit lines and the first decoder circuit comprises a bit line address decoder circuit.

[0170] In some embodiments, the device structure further includes: a second access line electrically connected to the memory cells of the corresponding column in the memory cells within the two-dimensional array; and a second decoder circuit including a plurality of second cantilever nanoelectromechanical devices, the plurality of second cantilever nanoelectromechanical devices overlying the two-dimensional array of the memory cells, embedded in the upper dielectric material layer and having output nodes electrically connected to corresponding second access lines selected from the second access lines.

[0171] In some embodiments, the second access line is a word line, and the second decoder circuit comprises a word line address decoder circuit.

[0172] In some embodiments, the device structure includes: a two-dimensional array of memory cells embedded in a memory level dielectric layer and overlying a substrate; a plurality of first access lines, wherein each of the plurality of first access lines is electrically connected to a corresponding row of memory cells in the two-dimensional array; and a first decoder circuit, including a plurality of first cantilever nanoelectromechanical devices, wherein the plurality of first cantilever nanoelectromechanical devices overly the two-dimensional array of memory cells and are configured to enable a selected first access line selected from the plurality of first access lines, wherein each of the plurality of first cantilever nanoelectromechanical devices includes: a first gate-controlled nanoelectromechanical switch connected to each other in parallel between a first source electrode and a common output node; and a second gate-controlled nanoelectromechanical switch connected to each other in series between a second source electrode and the common output node.

[0173] In some embodiments, each of the first gate-controlled nanoelectromechanical switch and the second gate-controlled nanoelectromechanical switch includes: a corresponding source electrode, including a cantilever having a free end; a corresponding drain electrode, including a fixed metal structure near the free end; and a corresponding gate electrode, close to the surface of the corresponding source electrode and not in contact with the corresponding source electrode.

[0174] In some embodiments, each of the first gate-controlled nanoelectromechanical switch and the second gate-controlled nanoelectromechanical switch includes a cavity, the free end of the corresponding source electrode is suspended in the cavity and the surface portion of the fixed metal structure is physically exposed to the cavity; and the device structure includes a top cover, the top cover covering each of the cavity of the first gate-controlled nanoelectromechanical switch and the cavity of the second gate-controlled nanoelectromechanical switch.

[0175] In some embodiments, the memory cell is selected from: a dynamic random access memory cell; a resistive random access memory cell; a magnetic tunnel junction random access memory cell; and a ferroelectric random access memory cell.

[0176] In some embodiments, a method of forming a device structure comprises: forming a two-dimensional array of memory cells and a first access line over a substrate, wherein the first access line is electrically connected to memory cells of corresponding rows of the memory cells within the two-dimensional array; and forming a first decoder circuit comprising a first cantilever nanoelectromechanical device over the two-dimensional array of memory cells, wherein the first cantilever nanoelectromechanical device has an output node electrically connected to a corresponding first access line selected from the first access line.

[0177] In some embodiments, each of the first cantilever nanoelectromechanical devices includes: a first gate-controlled nanoelectromechanical switch connected to each other in parallel between a first source electrode and a common output node; and a second gate-controlled nanoelectromechanical switch connected to each other in series between a second source electrode and the common output node.

[0178] In some embodiments, each of the first gate-controlled nanoelectromechanical switch and the second gate-controlled nanoelectromechanical switch includes: a corresponding source electrode, including a cantilever having a free end; a corresponding drain electrode, including a fixed metal structure near the free end; and a corresponding gate electrode, close to the surface of the corresponding source electrode and not in contact with the corresponding source electrode.

[0179] In some embodiments, the method further includes: forming an upper-level dielectric material layer above the two-dimensional array of the storage cells; forming a sacrificial material portion within an upper portion of the upper-level dielectric material layer; forming a cantilever metal structure and a metal line in the upper-level dielectric material layer and the sacrificial material portion; and removing the sacrificial material portion, wherein a free end of the cantilever metal structure is exposed to a cavity formed by removing the sacrificial material portion, and wherein each of the first cantilever nanoelectromechanical devices includes a corresponding plurality of cantilever gate-controlled nanoelectromechanical switches, and the corresponding plurality of cantilever gate-controlled nanoelectromechanical switches include a corresponding one of the cantilever metal structures.

[0180] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions and modifications to it without departing from the spirit and scope of the present invention.

Claims

1. A cantilever nanoelectromechanical decoder circuit, characterized in that: include: a two-dimensional array of memory cells embedded in a memory level dielectric layer and overlying a substrate; a plurality of first access lines, wherein each of the plurality of first access lines is electrically connected to a corresponding row of memory cells in the two-dimensional array; as well as A first decoder circuit includes a plurality of first cantilever nanoelectromechanical devices overlying the two-dimensional array of memory cells, wherein the plurality of first cantilever nanoelectromechanical devices are embedded in an upper dielectric material layer and have output nodes electrically connected to corresponding first access lines selected from the plurality of first access lines.

2. The cantilever nanoelectromechanical decoder circuit according to claim 1, wherein: Each of the plurality of first cantilever nanoelectromechanical devices is configured to generate a respective output for enabling or disabling the respective first access line; and The first decoder circuit is configured to enable a selected first access line from the plurality of first access lines without enabling any other first access lines from the plurality of first access lines except the selected first access line.

3. The cantilever nanoelectromechanical decoder circuit of claim 1 , wherein each of the plurality of first cantilever nanoelectromechanical devices comprises: first gate-controlled nanoelectromechanical switches connected to each other in parallel connection between the first source electrode and the common output node; as well as The second gate-controlled nanoelectromechanical switches are connected to each other in series between the second source electrode and the common output node.

4. The cantilever nanoelectromechanical decoder circuit of claim 3, wherein each of the first gate-controlled nanoelectromechanical switch and the second gate-controlled nanoelectromechanical switch comprises: a corresponding source electrode including a cantilever having a free end; a corresponding drain electrode including a fixed metal structure proximate said free end; as well as The corresponding gate electrode is close to the surface of the corresponding source electrode and is not in contact with the corresponding source electrode.

5. The cantilever nanoelectromechanical decoder circuit of claim 4, wherein each of the first gate-controlled nanoelectromechanical switch and the second gate-controlled nanoelectromechanical switch comprises a cavity, the free end of the corresponding source electrode is suspended in the cavity and a surface portion of the fixed metal structure is physically exposed to the cavity.

6. The cantilever nanoelectromechanical decoder circuit according to claim 4, wherein: Also included is a first address buffer transistor located on the substrate and configured to generate a set of output signals applied to each of the first gate electrode and the second gate electrode.

7. The cantilever nanoelectromechanical decoder circuit according to claim 6, wherein: The first address buffer transistor is configured to generate N digital address outputs; and Each of the plurality of first cantilever nanoelectromechanical devices includes N first gate-controlled nanoelectromechanical switches and N second gate-controlled nanoelectromechanical switches.

8. A cantilever nanoelectromechanical decoder circuit, characterized in that: include: a two-dimensional array of memory cells embedded in a memory level dielectric layer and overlying a substrate; a plurality of first access lines, wherein each of the plurality of first access lines is electrically connected to a corresponding row of memory cells in the two-dimensional array; as well as a first decoder circuit comprising a plurality of first cantilever nanoelectromechanical devices overlying the two-dimensional array of memory cells and configured to enable a selected first access line selected from the plurality of first access lines, wherein each of the plurality of first cantilever nanoelectromechanical devices comprises: first gate-controlled nanoelectromechanical switches connected to each other in parallel connection between the first source electrode and the common output node; as well as The second gate-controlled nanoelectromechanical switches are connected to each other in series between the second source electrode and the common output node.

9. The cantilever nanoelectromechanical decoder circuit of claim 8, wherein the memory cell is selected from: Dynamic random access memory cells; Resistive random access memory cells; Magnetic tunnel junction random access memory cell; and Ferroelectric random access memory cell.

10. A cantilever nanoelectromechanical decoder circuit, characterized in that: include: a two-dimensional array of memory cells embedded in a memory level dielectric layer and overlying a substrate; a first access line electrically connected to memory cells in a corresponding column of the memory cells in the two-dimensional array; as well as The first decoder circuit includes a plurality of first cantilever nanoelectromechanical devices overlying the two-dimensional array of the memory cells, embedded in an upper dielectric material layer and having output nodes electrically connected to corresponding first access lines selected from the first access lines.

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