Digital-to-analog converter circuit for suppressing even nonlinearity, transmitter and transceiver

Abstract

The utility model provides a digital-to-analog converter (DAC) circuit for suppressing even nonlinearity, which is applied to a transmitter and a transceiver and can effectively reduce local oscillator leakage (LOL) and improve the quality of transmitted signals. The digital-to-analog converter is a current type digital-to-analog converter and comprises a plurality of groups of corresponding current source circuits and switching circuits, for each group of current source circuit and switch circuit, a lateral shielding circuit is arranged between a current output wire of the current source circuit and a data input wire of the switch circuit, so that even nonlinearity of the digital-to-analog converter is remarkably inhibited.

Description

Technical Field

[0001] The present application belongs to the field of digital-to-analog signal conversion and radio frequency transceiver, and specifically relates to a digital-to-analog converter circuit, a transmitter and a transceiver for suppressing even-order nonlinearity. Background Art

[0002] This section is intended to provide a background or context to the embodiments of the application that are recited in the claims. No description herein is admitted to be prior art by inclusion in this section.

[0003] Due to the existence of even-order nonlinearity of the digital-to-analog converter (DAC), an additional DC offset will be generated when the DAC outputs an AC signal. After the DC offset is up-converted by the transmitter, it will generate additional local oscillator components, which will further deteriorate the local oscillator leakage index (LO Leakage) at the RF output end. In addition, the DC component caused by the even-order nonlinearity of the DAC will change with the frequency and amplitude of the output signal. Therefore, this part of the DC component cannot be eliminated by fixed DC compensation during the calibration process.

[0004] Therefore, how to fundamentally reduce the even-order nonlinearity of DAC is an urgent problem to be solved.

[0005] Application Contents

[0006] In view of the problems existing in the above-mentioned prior art, a digital-to-analog converter circuit, a transmitter and a transceiver for suppressing even-order nonlinearity are proposed.

[0007] In a first aspect, a digital-to-analog converter circuit for suppressing even-order nonlinearity is provided, comprising: a current-type digital-to-analog converter, comprising a plurality of groups of corresponding current source circuits and switch circuits; for each group of current source circuits and switch circuits, a lateral shielding circuit is provided between the current output line of the current source circuit and the data input line of the switch circuit.

[0008] Preferably, a ground line is provided between the current output line and the data input line as the lateral shielding circuit.

[0009] Preferably, the current-mode digital-to-analog converter (DAC) is configured to suppress frequency-dependent DAC even-order nonlinearities.

[0010] Preferably, the digital-to-analog converter circuit further comprises: an automatic calibration device configured to eliminate the influence of the frequency-independent DAC even-order nonlinearity on the transmitter local oscillator leakage (LOL) by DC component compensation using automatic calibration.

[0011] In a second aspect, a transmitter is provided, comprising the digital-to-analog converter circuit described in the first aspect.

[0012] According to a third aspect, a transceiver is provided, comprising the digital-to-analog converter circuit according to the first aspect.

[0013] One of the advantages of the above embodiment is that it can significantly suppress DAC even-order nonlinearity, thereby significantly improving the signal quality of the transmitter and the transceiver.

[0014] Other advantages of the present application will be explained in more detail with reference to the following description and drawings.

[0015] It should be understood that the above description is only an overview of the technical solution of the present application, so that the technical means of the present application can be more clearly understood and implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are specifically described below by way of example. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The advantages and benefits described herein and other advantages and benefits will be apparent to those of ordinary skill in the art by reading the detailed description of the exemplary embodiments below. The accompanying drawings are only used for the purpose of illustrating exemplary embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0017] Figure 1 A power supply DAC architecture in the prior art;

[0018] Figure 2 A digital-to-analog converter circuit provided in an embodiment of the present application;

[0019] Figure 3 A comparative diagram of the digital-to-analog converter circuit provided in an embodiment of the present application for suppressing even-order nonlinearity.

[0020] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts. DETAILED DESCRIPTION

[0021] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0022] In the description of the embodiments of the present application, it should be understood that terms such as "including" or "having" are intended to indicate the presence of disclosed features, numbers, steps, behaviors, components, parts, or a combination thereof in the present specification, and do not exclude the possibility of the presence of one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof.

[0023] Unless otherwise specified, “ / ” means or. For example, A / B can mean A or B. The “and / or” in this article is merely a way to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0024] The terms "first", "second", etc. are used only to distinguish the same or similar technical features for the convenience of description, and should not be understood as indicating or implying the relative importance or quantity of these technical features. Thus, the features defined by "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise specified, the term "plurality" means two or more than two.

[0025] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] like Figure 1 As shown, Figure 1 FIG. 4 is a schematic diagram showing the architecture of a current-mode DAC.

[0027] See also Figure 1 The current-type DAC includes a current source circuit group and a switch circuit group, which respectively include multiple groups of current source circuits and switch circuits arranged in parallel. The bias voltage is applied to the current source circuit group as a power-on voltage, and the output side of the current source circuit group is a current output wiring; the level pulse signal (0 or 1) is input into the switch circuit group through the data input wiring to control the opening and closing of each switch.

[0028] This application is for Figure 1 The current-mode DAC architecture shown in the figure is studied. Through control tests after layout parasitic extraction and actual chip measurement verification, it is accurately located that the even-order nonlinearity of the DAC mainly comes from the capacitive coupling between the current output line (CURRENT_OUT) of the current source circuit group and the data input line (DATA_IN) of the switch circuit group.

[0029] Figure 2 A digital-to-analog converter circuit for suppressing even-order nonlinearity provided by an embodiment of the present application is shown.

[0030] In order to reduce the capacitive coupling between the lines, the present application adds a lateral shielding circuit between the data input line (DATA_IN) of each current output line (CURRENT_OUT) of the current source circuit group and the switch circuit group, so as to significantly reduce the capacitive coupling between the current output line (CURRENT_OUT) and the data input line (DATA_IN), thereby reducing the even-order nonlinearity of the DAC output. Specifically, in the actual circuit layout design, the various input / output routing methods are intricate, and the embodiment of the present application adds a lateral shielding circuit between the power output line of the current source circuit and the data input line that controls the switch for each group of series-connected current sources and switches.

[0031] For example, suppose Figure 1 The leftmost current source is the first current source, and the leftmost switch is the first switch, then see Figure 2 The lateral shielding circuit is arranged between the first data input wiring connected to the first switch and the first power output wiring at the output side of the first current source to reduce the capacitive coupling between the two.

[0032] Preferably, the present application adopts adding a ground line (GND) between each group of CURRENT_OUT and DATA_IN wiring. It can be understood that by setting the ground line, the capacitive coupling can be reduced at a low cost.

[0033] Figure 3 The effect diagram of the digital-to-analog converter circuit of the embodiment of the present application on suppressing even-order nonlinearity is shown, and the comparison shows the change of the output second harmonic distortion (dBC) with the output frequency (MHz) before and after the addition of lateral shielding to the current-type DAC. Through the simulation comparison after parasitic extraction, it can be seen that after adopting the layout layout technology for suppressing DAC even-order nonlinearity in the embodiment of the present application, the harmonic distortion caused by the DAC second-order nonlinearity is reduced by more than 20dB.

[0034] Preferably, since the DC component caused by the DAC even-order nonlinearity will change with the frequency and amplitude of the output signal, this DC component cannot be eliminated by fixed DC compensation during the calibration process. Therefore, the current-type digital-to-analog converter (DAC) of the present application is specifically configured to suppress the frequency-related DAC even-order nonlinearity.

[0035] Preferably, the digital-to-analog converter circuit of the present application further comprises: an automatic calibration device configured to utilize automatic calibration to eliminate the influence of the frequency-independent DAC even-order nonlinearity by DC component compensation to the transmitter local oscillator leakage (LOL).

[0036] The present application also provides a transmitter, which includes the digital-to-analog converter circuit for suppressing even-order nonlinearity described in the above embodiment.

[0037] The present application also provides a transceiver, which includes the digital-to-analog converter circuit for suppressing even-order nonlinearity described in the above embodiment.

[0038] It can be understood that the digital-to-analog converter circuit of the above embodiment of the present application can significantly suppress the DAC even-order nonlinearity. Furthermore, suppressing the DAC even-order nonlinearity can effectively reduce the DC offset at the DAC output, thereby reducing the local oscillator leakage caused by the DC component at the antenna end after the transmitter up-conversion. Those skilled in the art are aware that the leaked local oscillator signal will cause a decrease in the quality of the transmitter signal and cause the vector magnitude error (EVM) to deteriorate. Therefore, suppressing the DAC even-order nonlinearity is of great significance to improving the signal quality of the transmitter or transceiver.

[0039] Although the spirit and principle of the present application have been described above with reference to several specific embodiments, it should be understood that the present application is not limited to the disclosed specific embodiments, and the division of various aspects does not mean that the features in these aspects cannot be combined. The present application is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the attached claims.

Claims

1. A digital-to-analog converter circuit for suppressing even-order nonlinearity, characterized in that: include: A current-type digital-to-analog converter (DAC), including a plurality of corresponding current source circuits and switch circuits; For each set of current source circuits and switch circuits, a lateral shielding circuit is provided between a current output wiring of the current source circuit and a data input wiring of the switch circuit to suppress even-order nonlinearity.

2. The digital-to-analog converter circuit according to claim 1, characterized in that: Also includes: A ground line is provided between the current output line and the data input line as the lateral shielding circuit.

3. The digital-to-analog converter circuit according to any one of claims 1 to 2, characterized in that: The current-mode digital-to-analog converter (DAC) is configured to suppress frequency-dependent DAC even-order nonlinearities.

4. The digital-to-analog converter circuit according to claim 1, characterized in that: Also includes: The automatic calibration device is configured to eliminate the influence of the frequency-independent DAC even-order nonlinearity on the transmitter local oscillator leakage (LOL) by direct current component compensation using automatic calibration.

5. A transmitter, characterized in that: The method comprises a digital-to-analog converter circuit as claimed in any one of claims 1 to 4.

6. A transceiver, characterized in that: The method comprises a digital-to-analog converter circuit as claimed in any one of claims 1 to 4.

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