LED parallel control chip with built-in self-checking address code burning circuit

Abstract

The utility model relates to an LED parallel control chip with a built-in self-checking address code burning circuit, which comprises a voltage stabilizing module, an oscillating circuit, a logic control module, an output control module, a single-wire parallel control input end and the self-checking address code burning circuit, the self-checking address code burning circuit comprises a self-checking address burning input end, an address code output module and a chip address burning circuit module. The voltage stabilizing module, the oscillating circuit, the logic control module, the output control module and the address code output module are connected to the positive electrode of the power supply in a single-wire parallel mode; the single-line parallel control input end is connected with one input end of the logic control module; the self-checking address burning input end and the single-wire parallel control input end are arranged in a mutually independent input manner, and the self-checking address burning input end is respectively connected with the other input end of the logic control module and the input end of the chip address burning circuit module; and the logic control module is respectively connected with the chip address burning circuit module and the address code output module.

Description

Technical Field

[0001] The utility model belongs to the technical field of LED control chips, in particular to an LED parallel control chip with a built-in self-checking address code burning circuit. Background Art

[0002] At present, most LED full-color display chips on the market use single-line or double-line series transmission signals, and in order to solve the problem of a certain IC being damaged without affecting the overall display effect, breakpoint continuous transmission or two-way channel transmission are generally used. However, traditional LED control chips have the following problems:

[0003] 1. If two consecutive lamp beads are damaged, the lamp beads behind will still be out of control, making it impossible to continue to transmit data signals and the latter part cannot be displayed normally.

[0004] 2. When the traditional single-line series or double-line series LED control chip is used in multi-stage drive applications, the transmission signal will change due to the series transmission. If it is transmitted through IC reforming, the signal rate may change, resulting in erroneous data or unrecognizable. If it is transmitted without IC reforming, the signal duty cycle will change, resulting in erroneous data.

[0005] 3. In terms of address fuse burning, the traditional method of burning metal fuses also has considerable problems. One of the burning methods is to burn metal fuses with lasers, which requires the use of special laser trimming equipment and can only be performed before chip packaging, which has a limited scope of application. Another burning method is to burn metal fuses with external high current. Because it requires opening windows or reserving pins, it also requires external high current, which will be limited by the design of the burning power supply equipment and pins. Since LED control chips need to burn address codes when used in multi-level drive fields, and the address codes of each chip will be different, that is, each chip needs to be burned separately. When using traditional methods to burn address codes, it will cause problems such as many steps required for the front-end production of LED control chips, long time, high labor costs, and low production efficiency. Utility Model Content

[0006] The purpose of the utility model is to provide an LED parallel control chip with a built-in self-checking address code burning circuit to address the deficiencies in the prior art, so as to solve the problems existing in transmitting data by traditional single-line series connection or double-line series connection and burning address codes by traditional burning methods.

[0007] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0008] An LED parallel control chip with a built-in self-checking address code burning circuit, comprising a voltage stabilizing module, an oscillating circuit, a logic control module and an output control module, wherein the output end of the logic control module is connected to the LED signal output end through the output control module, and characterized in that: it also comprises a single-line parallel control input end and a self-checking address code burning circuit, wherein the self-checking address code burning circuit comprises a self-checking address burning input end, an address code output module and a chip address burning circuit module;

[0009] The voltage stabilizing module, oscillation circuit, logic control module, output control module and address code output module are connected to the positive pole of the power supply in a single-line parallel manner; the single-line parallel control input end is used to input the address code and control data signal and is connected to an input end of the logic control module; the self-checking address burning input end and the single-line parallel control input end are independently inputted and set, the self-checking address burning input end is used to input the start burning coding signal and is respectively connected to the other input end of the logic control module and the input end of the chip address burning circuit module; the chip address burning circuit module is bidirectionally connected to the logic control module, and the output end of the logic control module is connected to the input end of the address code output module.

[0010] Preferably, the logic control module includes an address logic judgment circuit, a decoder circuit, a data decoding function circuit, an address code function circuit and an address code burning control function circuit;

[0011] An input end of the address logic judgment circuit is connected to the single-line parallel control input end, an output end of the address logic judgment circuit is respectively connected to an input end of a decoder circuit and an input end of an address code burning control function circuit through a data decoding function circuit, an input end of the decoder circuit is connected to an output end of an oscillating circuit, and an output end of the decoder circuit is connected to an input end of an output control module;

[0012] The other input end of the address logic judgment circuit is connected to the self-checking address burning input end, the address logic judgment circuit is bidirectionally connected to the chip address burning circuit module through the address code function circuit, and the output end of the address logic judgment circuit is connected to the input end of the address code output module.

[0013] Preferably, the address code functional circuit includes an address data decoding module and a burning time control module.

[0014] Preferably, the address data decoding module has the same structure as the data decoding functional circuit.

[0015] Preferably, the output control module includes a grayscale control circuit and an output drive circuit connected to the positive pole of the power supply in a single-line parallel manner, and the output end of the decoder circuit is connected to the LED signal output end through the grayscale control circuit and the output drive circuit in turn.

[0016] Preferably, the LED signal output end includes a red light signal output end, a green light signal output end and a blue light signal output end.

[0017] Preferably, the chip address burning circuit module includes a fuse, a first MOS tube and a weak pull-down circuit, the gate of the first MOS tube is connected to the self-test address burning input terminal, the drain of the first MOS tube is connected to the positive pole of the power supply through the fuse, the drain of the first MOS tube is connected to the logic control module through the weak pull-down circuit, and the source of the first MOS tube is grounded.

[0018] Preferably, the weak pull-down circuit comprises a first resistor, a second resistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor;

[0019] One end of the first resistor is connected to the drain of the first MOS tube, the other end of the first resistor is respectively connected to the drain of the second MOS tube, the gate of the third MOS tube and the gate of the fourth MOS tube, the gate of the second MOS tube is connected to the positive electrode of the power supply through the second resistor, the source of the second MOS tube and the source of the third MOS tube are respectively grounded, the drain of the third MOS tube and the drain of the fourth MOS tube are respectively connected to the logic control module, and the source of the fourth MOS tube is connected to the positive electrode of the power supply.

[0020] Preferably, the fuse is a polycrystalline silicon fuse.

[0021] Preferably, the voltage stabilizing module comprises an external resistor and a Zener circuit for power supply voltage division.

[0022] Compared with the prior art, the above technical solution adopted by the present invention has the following beneficial effects:

[0023] The utility model adopts a self-checking address code burning circuit different from the ones on the market to burn the address code so as to build an address into the LED control chip; the self-checking address code burning circuit of the utility model can automatically check and adjust the internal address burning time under the influence of different processes or other factors, so that the required internal address can be burned normally without being affected.

[0024] The utility model adopts a single-line parallel method to transmit data based on the traditional architecture, so that when multiple LED lamp beads are damaged, the data transmission and use of other lamp beads will not be affected, thereby not affecting the overall display effect. The utility model improves the transmission method from a single-line series protocol to a single-line parallel protocol, which can solve the problems of reorganization signal, slow transmission efficiency, low fault tolerance, and small transmission quantity caused by the traditional single-line series or double-line series LED control chip series transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions, and the following description is made with respect to the drawings:

[0026] Figure 1 A schematic diagram of logic signals for a single signal cycle for data transmission;

[0027] Figure 2 This is a schematic diagram of the pin positions of the LED parallel control chip of the utility model;

[0028] Figure 3 This is a system connection diagram of Example 1 of the LED parallel control chip of the utility model;

[0029] Figure 4 This is a system connection diagram of Example 2 of the LED parallel control chip of the utility model;

[0030] Figure 5 This is a single address code burning circuit diagram of the utility model;

[0031] Figure 6 It is a schematic diagram of eight address code burning circuits of the utility model;

[0032] Figure 7 This is a schematic diagram of the data decoding function circuit of the logic control module of the utility model;

[0033] Figure 8 This is a schematic diagram of the address code function circuit of the logic control module of the utility model;

[0034] Fig. 9 This is a schematic diagram of the address code burning and timing control function circuit of the logic control module of the utility model;

[0035] Fig.10 This is a schematic diagram of the connection of the self-checking function system of the self-checking address code burning circuit of the utility model;

[0036] Fig.11 This is a multi-level system diagram of the LED parallel control chip driver of the utility model;

[0037] Fig.12 This is a schematic diagram of the programming process of the LED parallel control chip of the utility model on the production line. DETAILED DESCRIPTION

[0038] The embodiments described below are only some of the embodiments of the present invention and do not represent all the embodiments consistent with the present invention. Now, in conjunction with the accompanying drawings, the exemplary embodiments are described as follows:

[0039] See also Figure 1-12As shown in FIG. 1 , the utility model provides an LED parallel control chip with a built-in self-checking address code burning circuit, which includes a voltage stabilizing module 10, an oscillating circuit 20, a logic control module 30, a chip address burning circuit module 40, an output control module 50 and an LED signal output terminal;

[0040] In order to solve the problems of reorganization signal, slow transmission efficiency, low fault tolerance, small transmission quantity and so on brought by the traditional single-line series or double-line series transmission of LED control chips, the utility model connects the voltage stabilizing module 10, the oscillation circuit 20, the logic control module 30, the output control module 50 and the address code output module 60 to the positive power supply VDD in a single-line parallel manner, and the grayscale control circuit 51 and the output drive circuit 52 of the output control module 50 are connected to the positive power supply VDD in a single-line parallel manner.

[0041] In this embodiment, the utility model adopts a single-line parallel method to transmit data based on the traditional architecture, so that when multiple LED lamp beads are damaged, the data transmission and use of other lamp beads will not be affected, and the overall display effect will not be affected. It should be noted that the above-mentioned circuits or modules can all be existing conventional technologies.

[0042] See also Figure 3 As shown, as a preferred embodiment, based on the above structure, preferably, the voltage stabilizing module 10 includes an external resistor and a Zener circuit for power supply voltage division; the oscillation circuit 20 is connected to the input end of the logic control module 30; the output end of the logic control module 30 is connected to the LED signal output end through the output control module 50, and the LED signal output end includes a red light signal output end LEDR, a green light signal output end LEDG and a blue light signal output end LEDB; the output control module 50 includes a grayscale control circuit 51 and an output drive circuit 52; the logic control module 30 is connected to the chip address burning circuit module 40 for bidirectional communication.

[0043] Example 1

[0044] See also Figure 3As shown, in order to solve the problems that the traditional burning method for address code burning will cause the front-end production of LED control chips to require many steps, a long time, high labor costs, and low production efficiency, on the basis of the above structure, further, the utility model also includes a single-line parallel control input terminal DIN1 and a self-checking address code burning circuit, the self-checking address code burning circuit includes a self-checking address burning input terminal DIN2, an address code output module 60 and a chip address burning circuit module 40; the single-line parallel control input terminal DIN1 is used to input the address code and the control data signal and is connected to an input terminal of the logic control module 30; the self-checking address burning input terminal DIN2 and the single-line parallel control input terminal DIN1 are independently input and set, the self-checking address burning input terminal DIN2 is used to input the start burning code signal and is respectively connected to the other input terminal of the logic control module 30 and the input terminal of the chip address burning circuit module 40; the chip address burning circuit module 40 is bidirectionally connected to the logic control module 30, and the output terminal of the logic control module 30 is connected to the input terminal of the address code output module 60.

[0045] In this embodiment, the utility model burns the address code by adopting a self-checking address code burning circuit different from those on the market, so as to build an address into the LED control chip, so that it can automatically check and adjust the internal address burning time under the influence of different processes or other factors, so that it can burn the required internal address normally without being affected.

[0046] Example 2

[0047] See also Figure 4 As shown, as a preferred implementation, based on the structure of the above embodiment 1, preferably, the logic control module 30 includes an address logic judgment circuit 31, a decoder circuit 32, a data decoding function circuit 33, an address code function circuit 34 and an address code burning control time function circuit 35;

[0048] One input end of the address logic judgment circuit 31 is connected to the single-line parallel control input end DIN1, and the output end of the address logic judgment circuit 31 is respectively connected to the input end of the decoder circuit 32 and the input end of the address code burning control function circuit 35 through the data decoding function circuit 33. The input end of the decoder circuit 32 is connected to the output end of the oscillation circuit 20, and the output end of the decoder circuit 32 is connected to the LED signal output end through the grayscale control circuit 51 and the output drive circuit 52 in sequence; the other input end of the address logic judgment circuit 31 is connected to the self-detection address burning input end DIN2, the address logic judgment circuit 31 is bidirectionally connected to the chip address burning circuit module 40 through the address code function circuit 34, and the output end of the address logic judgment circuit 31 is connected to the input end of the address code output module 60.

[0049] In the multi-stage drive, the address code output module 60 outputs the pad position DOUT after the chip address code is incremented by one. The output end of the address code output module 60 is connected to the self-detection address burning input end DIN2 of the next stage self-detection address code burning circuit.

[0050] Based on the above structure, preferably, the address code function circuit 34 includes an address data decoding module 341 and a programming time control module 342 ; the address data decoding module 341 has the same structure as the data decoding function circuit 33 .

[0051] See also Figure 5 or Figure 6 As shown, based on the structure of the above-mentioned embodiment 2, preferably, the chip address burning circuit module 40 includes a fuse, a first MOS tube M1 and a weak pull-down circuit, the gate of the first MOS tube M1 is connected to the self-checking address burning input terminal DIN2, the drain of the first MOS tube M1 is connected to the positive power supply VDD through the fuse, the drain of the first MOS tube M1 is connected to the logic control module 30 through the weak pull-down circuit, and the source of the first MOS tube M1 is grounded GND.

[0052] On the basis of the above structure, preferably, the weak pull-down circuit includes a first resistor R1, a second resistor R2, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4; one end of the first resistor R1 is connected to the drain of the first MOS tube M1, and the other end of the first resistor R1 is respectively connected to the drain of the second MOS tube M2, the gate of the third MOS tube M3 and the gate of the fourth MOS tube M4, the gate of the second MOS tube M2 is connected to the positive power supply VDD through the second resistor R2, the source of the second MOS tube M2 and the source of the third MOS tube M3 are respectively grounded GND, the drain of the third MOS tube M3 and the drain of the fourth MOS tube M4 are respectively connected to the logic control module 30, and the source of the fourth MOS tube M4 is connected to the positive power supply VDD.

[0053] Based on the above structure, preferably, the fuse is a polycrystalline silicon fuse, which can be successfully melted with a larger current after packaging.

[0054] The working principle of the utility model is as follows:

[0055] See also Figure 1 As shown, Figure 1The schematic diagram of the logic signal of a single signal cycle for data transmission; the data signal of the LED control chip is a square wave signal with a period of 1200ns. When the high level time is about 66.6% of the entire cycle, i.e. 800ns, and the low level time is about 33.3% of the entire cycle, i.e. 400ns, the carrier signal is considered as logic 1. When the high level time is about 33.3% of the entire cycle, i.e. 400ns, and the low level time is about 66.6% of the entire cycle, i.e. 800ns, the carrier signal is considered as logic 0.

[0056] See also Figure 2 As shown, Figure 2 The figure is a schematic diagram of the pin positions of the LED parallel control chip of the utility model; VDD in the figure is the pad position of the positive electrode of the chip external power supply, GND in the figure is the pad position of the chip grounding, DIN1 in the figure is the pad position of the chip data input, DIN2 in the figure is the pad position of the chip address code input, DOUT in the figure is the pad position of the chip address code output after adding one, LEDR is the pad position of the red light signal output, LEDG is the pad position of the green light signal output, and LEDB is the pad position of the blue light signal output.

[0057] See also Figure 3 As shown, Figure 3 This is a system connection diagram of Example 1 of the LED parallel control chip of the utility model; the voltage stabilizing module 10, the oscillation circuit 20, the logic control module 30, the chip address burning circuit module 40, the output control module 50 and the LED signal output terminal in Example 1 can all adopt existing conventional circuits or modules, and the functions of each circuit or module are as follows:

[0058] The voltage stabilizing module 10 mainly includes an external resistor and a Zener circuit for dividing the power supply voltage, which is used to reduce the power supply voltage and provide a stable working voltage for the circuit;

[0059] The oscillation circuit 20 outputs a clock signal with stable frequency under different power supply voltages and different temperatures according to the enable signal;

[0060] The logic control module 30 mainly includes an address logic judgment circuit 31 and a decoder circuit 32. The decoder circuit 32 is an RGB LED pwm output processing circuit;

[0061] The address logic judgment circuit 31 is used to compare the input address code with the address in the chip address burning circuit module 40. When the chip is selected, the internal circuit will receive the data information in the carrier data after the address code.

[0062] The decoder circuit 32 decodes the data signal according to the fixed frequency clock signal output by the oscillation circuit 20 to obtain the PWM signal of the LED light control. When the address in the LED light control data is the same as the burned address, the PWM signal of the LED light with different duty ratios is output to the output control module 50.

[0063] The output control module 50 includes a grayscale control circuit 51 and an output drive circuit 52; the grayscale control circuit 51 converts the data information in the carrier data circuit into grayscale signals with different duty cycles;

[0064] The output driving circuit 52 is connected to the external LED driving terminal and is used to drive the LED module to work according to the grayscale signal;

[0065] The chip address burning circuit module 40 mainly burns the input address code into the module by blowing the fuse (polysilicon fuse) after receiving the start burning signal.

[0066] The working principle of the embodiment 1 of the utility model is as follows: the LED control chip after burning sends a data signal to the DIN1 pin by the external control module, and the data signal format to the single-line parallel control input terminal DIN1 is a header code (8 bits) + address code (8 bits) + first group of control data (8 bits) + second group of control data (8 bits) + third group of control data (8 bits). Each chip has a fixed address burned inside, and the input address code will be compared with the internal address. Only when the two are completely consistent, the following three groups of data (24 bits in total) are valid for the chip. The three groups of data each control the corresponding three LED lights, for example, the first group of data controls the gray value of the corresponding RLED (red light), the second group of data controls the gray value of the corresponding GLED (green light), and the third group of data controls the gray value of the corresponding BLED (blue light).

[0067] Exemplary description: when the display of the LED high-brightness mode is enabled, the corresponding output duty cycle is a PWM signal of 100%; when the display of the LED medium-brightness mode is enabled, the corresponding output duty cycle is a PWM signal of 50%; when the display of the LED low-brightness mode is enabled, the corresponding output duty cycle is a PWM signal of 10%.

[0068] See also Figure 4 As shown, Figure 4This is a schematic diagram of system connection of Example 2 of the LED parallel control chip of the utility model; the input end of the chip of the utility model is divided into DIN1 pin and DIN2 pin, and the two input ends are independent inputs, do not interfere with each other, and are recognized separately, wherein DIN1 is a single-line parallel control input end, and DIN2 is a self-checking address burning input end; the utility model sets a set of 8-bit header code and 8-bit address code, and the 8-bit header code is to prevent the influence of clutter, resulting in erroneous opening of functions, and to reserve user function design; the 8-bit address code is used as the address code to be burned by the first LED control chip. After detecting the input address code, the system starts the self-checking address code burning circuit to enter the address code burning mode, and the burning time can be adjusted and self-checked. In addition, the chip address burning circuit module 40 is provided with a protection resistor to avoid large current damage to the circuit during burning. After the burning is successful, the chip address burning circuit module 40 will be locked to prevent the address code from being burned for the second time after power is turned on again. If the burning fails, the second burning can be performed.

[0069] The utility model can also be provided with a startup burning code setting module so as to send a startup burning code signal to the self-checking address code burning circuit for use in the startup burning address code mode; the startup burning code signal is only used during burning, and the chip does not need to be burned when it works normally in the application, and the DIN2 pin can be floated or grounded.

[0070] See also Figure 5 As shown, Figure 5 The figure is a single address code burning circuit diagram of the utility model; as a specific implementation, the self-checking address code burning circuit of the LED control chip of the utility model has a chip address burning circuit module 40 for single address code burning, that is, it has a fuse, a first MOS tube M1 and a weak pull-down circuit; the weak pull-down circuit includes a first resistor R1, a second resistor R2, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4;

[0071] The gate of the first MOS tube M1 is connected to the self-checking address burning input terminal DIN2, the drain of the first MOS tube M1 is connected to the positive power supply VDD through a fuse, one end of the first resistor R1 is connected to the drain of the first MOS tube M1, the other end of the first resistor R1 is respectively connected to the drain of the second MOS tube M2, the gate of the third MOS tube M3 and the gate of the fourth MOS tube M4, the gate of the second MOS tube M2 is connected to the positive power supply VDD through the second resistor R2, the source of the first MOS tube M1, the source of the second MOS tube M2 and the source of the third MOS tube M3 are respectively grounded GND, the drain of the third MOS tube M3 and the drain of the fourth MOS tube M4 are respectively connected to the logic control module 30, and the source of the fourth MOS tube M4 is connected to the positive power supply VDD.

[0072] In this embodiment, before burning, since the poly fuse is a low-impedance component, the M1 tube is closed, the M2 tube has a strong impedance, and the VDD has a strong pull-up effect on the other end of the poly fuse, the circuit transmits a low level of logic "0" to the logic control module. When the coding signal to start burning is logic "1", the M1 tube will be opened. At this time, there will be a large current from VDD through the M1 tube to the ground to melt the poly fuse. After melting, the M1 tube is closed again, and the impedance of the poly fuse will become very large. At this time, the impedance of the M2 tube will be much smaller than the impedance of the poly fuse. Therefore, under the action of the pull-down current of the M2 tube, the signal output to the logic control module is logic "1", so that the circuit successfully completes the burning of the 1-bit address code.

[0073] See also Figure 6 As shown, Figure 6 Schematic diagram of eight address code burning circuits of the utility model; as another specific implementation, the self-checking address code burning circuit of the LED control chip of the utility model has eight chip address burning circuit modules 40 for eight address code burning, that is, eight fuses, eight first MOS tubes M1 and eight weak pull-down circuits;

[0074] The 8 fuses are Fuse1, Fuse2, Fuse3, Fuse4, Fuse5, Fuse6, Fuse7 and Fuse8 in order, one end of each fuse is connected to VDD, and the other end is connected to the first MOS tube M1 to ground; the self-checking address burning input terminal DIN2 is used to input 8 start-up burning code signals, and the 8 start-up burning code signals are A0, A1, A2, A3, A4, A5, A6 and A7 in order.

[0075] The burning principle of this embodiment is: first, the external input address code is placed in the register. When the start burning coding signal comes in, the address code is input in parallel to the 8 chip address burning circuit modules 40 responsible for burning. If the address code is "1", the first MOS tube M1 is driven to open, and the fuse is blown by outputting a large current. If the address code is "0", the first MOS tube M1 is closed and the fuse will not be blown, so as to make the correct position address burning; before the LED control chip is burned, the internal logic state defaults to the address code of 0000 0000. The utility model can obtain different address codes by blowing 8 fuses, for example: blowing Fuse1 can obtain the address code 1000 0000; blowing Fuse1 and Fuse2 can obtain the address code 1100 0000; blowing Fuse1, Fuse2, and Fuse3 can obtain the address code 1110 0000. By analogy, we can get a total of 256 different address codes: 0000 0000, 0000 0001, 0000 0010, ... 1111 1110, 1111 1111.

[0076] It should be noted that the address code of this embodiment is discussed using an 8-bit address code as an example. The address code is a preset bit and can be adjusted according to actual product application conditions. If it is a 16-bit address code, the number of address combinations is 65536.

[0077] See also Figure 7 As shown, Figure 7 This is a schematic diagram of the data decoding function circuit 33 of the logic control module of the utility model; the data signal format of the single-line parallel control input terminal DIN1 is header code (8 bits) + address code (8 bits) + first group of control data (8 bits) + second group of control data (8 bits) + third group of control data (8 bits). Figure 7The circuit shown in the figure is used to illustrate the decoding process. The utility model mainly uses the clk_data input by the oscillation circuit as a trigger judgment, and the flash signal is used as a reset signal for the internal function, which is used for the cyclic decoding of the entire module. When the D flip-flop of the dump has not been triggered, that is, the Q output is 0, the decoding function will continue to decode. The mode, h_flag, and h2 triggers are all different moments of decoding. The Q output end of the D flip-flop will connect the upper and lower parts. The circuit in the upper half of the figure is the judgment of each trigger signal on the dump signal. It must be ensured that the dump signal has not been triggered, which means that the data decoding has not been completed. Among them, the load_rom trigger is to enable the two-choice selector to determine which function is enabled, whether to judge the data 24bit or the control time 9bit. Finally, it is summarized to the D flip-flop of the dump for the final dump output. The control switch of the module decoding function is triggered and controlled by modeoff and dump together. The Q output of modeoff must be kept to be 0 and the Q output of dump must be kept to be 0 before normal decoding can be performed.

[0078] Figure 7 The lower part of the circuit shown is the main decoding process. After four levels of judgment, the judgment is triggered by the Mode, h_flag, h2 and data_data signals respectively, which are all in the decoding process. ROM[0] is the transfer station of the entire decoding process and is the place where the current decoding signal is stored. The first level of judgment is triggered by the h2 signal. When h2 is 0, it is at the beginning or end of the decoding process. Here, it will be judged in conjunction with the trigger of h_flag. When h2 is 1 and h_flag is 0, it is the beginning of decoding. At this time, the data storage will be shifted by judging the trigger of the data_data signal, which also represents the start of the decoding count. On the contrary, when h2 is 0 and h_flag is 0, it is the end of decoding. When h_flag is 1 and h2 is 1, the current input data is captured by judging the trigger of the data_data signal to obtain the decoding signal. The trigger of the Mode signal is used to determine whether it is in a certain mode. When Mode is 1, the data is not decoded directly, but the two-choice selector of the panduan in the upper circuit part is judged to determine whether the data is 24 bits or the timing control is 9 bits.

[0079] See also Figure 8 As shown, Figure 8Schematic diagram of the address code function circuit 34 of the logic control module of the utility model; here is the circuit module of the self-checking address burning input terminal DIN2, the address code function circuit 34 includes an address data decoding module 341 and a burning time control module 342, which are mainly divided into two major functions, one is the decoding of address data, and the other is the control of burning time; among them, the address data decoding module 341 for decoding address data can refer to Figure 7 The data decoding function circuit 33 shown in the figure uses the same method, and both use the clk_data input by the oscillation circuit as a trigger judgment.

[0080] See also Fig. 9 As shown, Fig. 9 The schematic diagram of the address code burning control time function circuit 35 of the logic control module of the utility model; the address code burning control time function circuit 35 mainly uses the ms250 input signal as a trigger, so that the load_off trigger increases at a fixed time under the trigger of the timing signal ms250 until it is consistent with the input rom_load, and then the load burning signal is turned on. The value of rom_load is determined by the rom_ok and load_rom signals. If load_rom is not enabled, the internally set default value will be used to control the burning time. Otherwise, the value of rom_load is received.

[0081] When the address code of the chip is burned, the chip will no longer need to be burned when it is used. During normal operation, the single-line parallel control input terminal DIN1 first inputs the address code followed by the data. In the logic control module 30, the address code in the chip address burning circuit module 40 will be compared with the input address code. Only when it is completely consistent with the input address code, the data after the address code is valid for this chip.

[0082] See also Fig.10 As shown, Fig.10 This is a schematic diagram of the self-checking function system connection of the self-checking address code burning circuit of the utility model, and a schematic diagram of the circuit module used to determine whether the burning is completed. Fig.10As shown, when the burning is started, A0-A7 of the start burning coding signal will output an 8-bit address code of logic "0" or "1", and the 8-bit address code will be simultaneously given to the chip address burning circuit module 40 and the address logic judgment circuit 31 of the next level. When the chip address burning circuit module input A0-A7 is logic "1", the corresponding F0-F7 output will also be logic "1" after burning. For example, the 8-bit address code of A0-A7 is 1111 0000, and the 8-bit address code of F0-F7 is also 1111 0000 after the burning is completed. During the burning process, it may be affected by force majeure factors, resulting in an uncertain burning time. At this time, it will be determined whether the burning is completed when the timing self-test signal sent by the address logic judgment circuit comes. Therefore, the burning time is not fixed, it is self-checkable and controllable. Only when the 8-bit address code of the address logic judgment circuit A0-A7 is completely consistent with the 8-bit address code of F0-F7, the system determines that the burning has been completed. At this time, the output OK will change from logic "0" to logic "1". The logic "1" of OK will be used as a feedback signal to terminate the burning, and no large current will flow through the poly fuse.

[0083] See also Fig.11 As shown, Fig.11 This is a multi-level system diagram of the LED parallel control chip drive of the utility model; the utility model includes multiple LED drive modules, all of which are of the same model and have the same functions. All of the drive modules are sequentially arranged as LED drive module 1, LED drive module 2, LED drive module 3, ..., LED drive module N.

[0084] The address code output module 60 of the utility model is the pad position DOUT output after the chip address code is incremented by one. The output end of the address code output module 60 is connected to the self-checking address burning input end DIN2 of the next-level LED driver module; all LED driver modules adopt a parallel connection method to share the single-line parallel control input end DIN1, and DIN2 and DOUT are only used when the address code is burned.

[0085] See also Fig.12 As shown, Fig.12 This is a schematic diagram of the burning process of the LED parallel control chip of the utility model on the production line; in the figure, the upper light bar is connected to the LED control chip, and each LED control chip drives the red, green and blue LED lights.

[0086] The specific burning process of the utility model is as follows: first, input the 8-bit header code 0000 1010 and the 8-bit address code 0000 0000 to the DIN2 pin of the first chip of the light bar. After inputting the last address code and waiting for 20us, when the LOAD signal in the figure becomes a high level, the chip address burning circuit module 40 will burn the fuse. The high level time of the LOAD signal can be controlled by the data input by DIN1 to ensure that the fuse can be burned. After the burning is completed, the LOAD signal becomes a low level, and at this time DOUT will output the next header code + address code 0000 1010 + 0000 0001, and the address code is burned for each chip in a cycle. The purpose of staggering the burning time of the chips is to ensure that the burning current of each chip is more sufficient to avoid the burning failure caused by insufficient power driving capability.

[0087] The above are only preferred specific embodiments of the utility model and are not intended to limit the protection scope of the utility model; any equivalent changes, modifications, substitutions and variations made by technicians in this technical field based on the concept of the utility model through logical analysis, reasoning or limited experiments on the basis of the existing technology should be within the protection scope determined by the claims.

Claims

1. An LED parallel control chip with a built-in self-checking address code burning circuit, comprising a voltage stabilizing module (10), an oscillating circuit (20), a logic control module (30) and an output control module (50), wherein the output end of the logic control module (30) is connected to the LED signal output end through the output control module (50), and is characterized in that: It also includes a single-line parallel control input terminal (DIN1) and a self-checking address code burning circuit, wherein the self-checking address code burning circuit includes a self-checking address burning input terminal (DIN2), an address code output module (60) and a chip address burning circuit module (40); The voltage stabilizing module (10), the oscillating circuit (20), the logic control module (30), the output control module (50) and the address code output module (60) are connected to the positive pole of the power supply (VDD) in a single-line parallel manner; the single-line parallel control input terminal (DIN1) is used to input the address code and the control data signal and is connected to an input terminal of the logic control module (30); the self-checking address burning input terminal (DIN2) and the single-line parallel control input terminal (DIN1) are independently input-set, the self-checking address burning input terminal (DIN2) is used to input the start burning code signal and is respectively connected to the other input terminal of the logic control module (30) and the input terminal of the chip address burning circuit module (40); the chip address burning circuit module (40) is bidirectionally connected to the logic control module (30), and the output terminal of the logic control module (30) is connected to the input terminal of the address code output module (60).

2. The LED parallel control chip with built-in self-checking address code burning circuit according to claim 1, characterized in that: The logic control module (30) comprises an address logic judgment circuit (31), a decoder circuit (32), a data decoding function circuit (33), an address code function circuit (34) and an address code burning control time function circuit (35); An input end of the address logic judgment circuit (31) is connected to the single-line parallel control input end (DIN1), and an output end of the address logic judgment circuit (31) is respectively connected to an input end of a decoder circuit (32) and an input end of an address code burning control function circuit (35) through a data decoding function circuit (33), an input end of the decoder circuit (32) is connected to an output end of an oscillating circuit (20), and an output end of the decoder circuit (32) is connected to an input end of an output control module (50); Another input end of the address logic judgment circuit (31) is connected to the self-checking address burning input end (DIN2), the address logic judgment circuit (31) is bidirectionally connected to the chip address burning circuit module (40) via the address code function circuit (34), and the output end of the address logic judgment circuit (31) is connected to the input end of the address code output module (60).

3. The LED parallel control chip with built-in self-checking address code burning circuit according to claim 2, characterized in that: The address code function circuit (34) comprises an address data decoding module (341) and a burning time control module (342).

4. The LED parallel control chip with built-in self-checking address code burning circuit according to claim 2, characterized in that: The output control module (50) comprises a grayscale control circuit (51) and an output drive circuit (52) connected to the positive pole of a power supply (VDD) in a single-line parallel manner, and the output end of the decoder circuit (32) is connected to the LED signal output end through the grayscale control circuit (51) and the output drive circuit (52) in sequence.

5. The LED parallel control chip with built-in self-checking address code burning circuit according to claim 1, characterized in that: The LED signal output end includes a red light signal output end (LEDR), a green light signal output end (LEDG) and a blue light signal output end (LEDB).

6. The LED parallel control chip with built-in self-checking address code burning circuit according to claim 1, characterized in that: The chip address burning circuit module (40) comprises a fuse, a first MOS tube (M1) and a weak pull-down circuit, wherein the gate of the first MOS tube (M1) is connected to a self-checking address burning input terminal (DIN2), the drain of the first MOS tube (M1) is connected to a positive power supply (VDD) through a fuse, the drain of the first MOS tube (M1) is connected to a logic control module (30) through a weak pull-down circuit, and the source of the first MOS tube (M1) is grounded.

7. The LED parallel control chip with built-in self-checking address code burning circuit according to claim 6, characterized in that: The weak pull-down circuit comprises a first resistor (R1), a second resistor (R2), a second MOS transistor (M2), a third MOS transistor (M3) and a fourth MOS transistor (M4); One end of the first resistor (R1) is connected to the drain of the first MOS tube (M1), and the other end of the first resistor (R1) is respectively connected to the drain of the second MOS tube (M2), the gate of the third MOS tube (M3) and the gate of the fourth MOS tube (M4); the gate of the second MOS tube (M2) is connected to the positive power supply (VDD) through the second resistor (R2); the source of the second MOS tube (M2) and the source of the third MOS tube (M3) are respectively grounded; the drain of the third MOS tube (M3) and the drain of the fourth MOS tube (M4) are respectively connected to the logic control module (30); and the source of the fourth MOS tube (M4) is connected to the positive power supply (VDD).

8. The LED parallel control chip with built-in self-checking address code burning circuit according to claim 6, characterized in that: The fuse is a polycrystalline silicon fuse.

9. The LED parallel control chip with built-in self-checking address code burning circuit according to claim 1, characterized in that: The voltage stabilizing module comprises an external resistor and a Zener circuit for dividing the power supply voltage.

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