Grid associated transistor with groove type grid polycrystalline silicon structure

Abstract

The utility model relates to a gate associated transistor with a groove-type gate polycrystalline silicon structure, which is characterized in that an N-type low-resistivity layer is arranged on the lower layer of the gate associated transistor, a plurality of parallel strip-shaped N-type emitter regions with high doping concentration are arranged on the upper surface of a silicon substrate slice of an N-type high-resistivity layer is arranged on the upper layer of the gate associated transistor, and a doped polycrystalline silicon layer is connected onto the emitter regions. A groove of the groove type gate region is filled with polycrystalline silicon. Compared with the prior art, the gate associated transistor has the advantage that the failure rate is reduced by one order of magnitude.

Description

Technical Field

[0001] The utility model relates to a tandem gate transistor, belonging to the technical field of silicon semiconductor devices. Background Art

[0002] In 1979, Hisao Kondo proposed the gate associated transistor (GAT), and then conducted a detailed analysis (see IEEE Trans. Electron Device, vol. ED-27, PP. 373-379. 1980). In 1994, Chen Fuyuan, Jin Wenxin, and Wu Zhonglong further analyzed the gate associated transistor (see Power Electronics Technology, 1994, No. 4, 1994.11. pp52-55), pointing out that the gate associated transistor device exhibits excellent characteristics such as high withstand voltage, fast switching, and low saturation voltage drop.

[0003] Early GAT transistors all used a planar structure. In 2000, China's invention patent ZL00100761.0 (hereinafter referred to as prior art 1) proposed a trench-gate polysilicon GAT transistor. The principle of its structure is as follows: Figure 1 As shown in the figure: on the upper surface of a silicon substrate 4 having a first conductive type low resistivity layer 42 as the lower layer and a first conductive type high resistivity layer 41 as the upper layer, there are a plurality of emitter regions 3 of the first conductive type with a high doping concentration, the emitter regions 3 are connected to an emitter metal layer 1 through a doped polysilicon layer 9, each emitter region 3 is surrounded by a second conductive type base region 2, the side of the base region 2 is connected to a gate region 6 having a second conductive type doping concentration higher than that of the base region 2 and a depth deeper than that of the base region 2, the gate region 6 is connected to the gate metal layer, and the silicon substrate 4 has a plurality of emitter regions 3 of the first conductive type with a high doping concentration. The upper layer 41 below the base region 2 and the gate region 6 is the collector region, the lower layer 42 of the silicon substrate 4 is the collector, and the lower surface of the collector 42 is connected to the collector metal layer 8, wherein: the gate region 6 is groove-shaped, and the bottom of the groove 5 is a second conductive type highly doped region; the emitter region 3 is connected to the first conductive type doped polysilicon layer 9, and the doped polysilicon layer 9 is connected to the emitter metal layer 1; the bottom and side surfaces of each groove 5 are covered with an insulating layer 7, and the insulating layer 7 on the side extends to the upper surface of the silicon substrate 4. This groove-gate polysilicon structured duo-gate transistor can obtain a larger current density, a more uniform current distribution, a faster switching speed, and a higher reliability than a planar structured duo-gate transistor.

[0004] Later experiments found the problem. Using a high-power microscope to observe the surface of various devices after burning, it was found that the failure point of the trench-gate polysilicon emitter-gate transistor was near the emitter pressure pad, while the distance between the failure point and the emitter pressure pad of the traditional planar bipolar transistor was quite large, about 1 / 4 of the distance between the emitter pressure pad and the base pressure pad. Applying transistor principles and thermodynamics theory for analysis, it can be concluded that the closer the failure point is to the emitter pressure pad, the greater the resistance of the emitter metal strip, the more uneven the distribution of the collector-emitter current density Jce along the emitter metal strip, the greater the current density Jce in the area closer to the emitter pressure pad, and the easier it is to fail under large current impact. The above analysis is only applicable to current-driven transistors such as bipolar transistors and gate transistors, and is not applicable to voltage-driven transistors, that is, field-controlled transistors such as power MOS tubes and IGBTs. In order to improve the uniformity of current distribution and improve the ability to resist large current impacts, it is necessary to reduce the resistance of the emitter metal strip. Therefore, the thickness of the emitter metal layer was doubled in the experiment. It was found that the ability of the trench-gate polysilicon emitter-gate transistor to withstand large current shocks did not improve much. The microscopic results showed that the failure point was still near the emitter pad. Then, a scanning electron microscope image SEM was used for further research to check the image of the aluminum layer near the trench gate. The schematic diagram is shown in the figure below. Figure 2-4 The results and analysis are as follows: 1. The aluminum layer on the side wall is very thin: Although the aluminum layer thickness reaches 4 microns (D1), the aluminum layer on the side wall is only 0.3 microns (T1). Figure 2 As shown; 2, the aluminum layer is thickened to 8 microns (D2), and the aluminum layer on the side wall is still 0.3 microns (T2). Figure 3 As shown; 3, in the chip peripheral area, the aluminum layer of the side wall of the groove gate close to the inside (i.e., close to the center of the wafer) is thinner, only 0.2 microns (T3), while the thickness of the aluminum layer of the side wall close to the outside (i.e., close to the periphery of the wafer) increases to 0.35 microns (T4), as shown Figure 4As shown. The phenomenon that the aluminum layer of the inner side wall of the groove in the peripheral area of ​​the chip is thinner can be explained by the fact that the sputtering source is located in front of the middle of the chip, and the sputtered aluminum beam is at an oblique angle to the peripheral part of the chip. Due to the influence of the sputtering angle, the aluminum layer of the peripheral side wall of the chip is thinner. The resistance value of the aluminum strip on the periphery is 3 times higher than that in the center through the test pattern test set on the chip. The electron scanning microscope photo shows that the aluminum layer of the peripheral side wall is as thin as 0.1 micron. In order to save the area of ​​the groove area, increase the current area, and increase the current capacity, the groove gate area is often made narrower, making the aluminum layer of the side wall thinner. Analyzing the 3-micron groove, the oxide layer is 0.6 micron*2, the polysilicon is 0.6 micron*2, and the gap is only 0.8 micron. The aluminum layer is only 0.3 micron. In the groove-gate polysilicon emitter-gate transistor, the emitter metal strip must cross multiple steps, and the resistance of the emitter metal strip is equal to the sum of the resistance of the table and the resistance of the side wall. The aluminum layer on the table is very thick and has a small resistance, while the aluminum layer on the side wall is very thin and has a large resistance. Therefore, the resistance of the entire emitter metal strip is mainly determined by the resistance of the side wall. If the thickness of the side wall does not increase, the resistance of the entire emitter metal strip will not change much. Therefore, although the thickness of the emitter metal strip has doubled, its resistance has not decreased significantly, resulting in the failure point still being near the emitter pad.

[0005] Whether it is a bipolar transistor or a gate transistor, the conventional die shape is a square. The die area of ​​the trench gate polysilicon emitter gate transistor is 0.25mm², its single side size is 0.5mm, and the single side size of the active area of ​​the die reaches 300μm. If the repeating unit is 13μm, the emitter metal aluminum layer needs to cross over more than 40 steps formed by the bottom of the trench and the table top. The resistance of the thin aluminum layer on the side walls of more than 40 trenches is added up, which has a serious adverse effect on the uniformity of the die current. Therefore, gate transistors with a die area greater than 0.25mm² need to adopt other structures to solve the existing problems. Summary of the invention

[0006] In view of the above, the purpose of the utility model is to provide a new trench-gate polysilicon structured gate transistor to address the deficiencies of the prior art, which can provide a more uniform current distribution and improve the power consumption of the transistor.

[0007] In order to achieve the purpose of the utility model, the technical solution adopted by the utility model is:

[0008] A gate transistor with a trench-type gate polysilicon structure has a plurality of parallel long strip N-type high-doping concentration emitter regions on the upper surface of a silicon substrate with an N-type low-resistivity layer at the lower layer and an N-type high-resistivity layer at the upper layer, and an N-type doped polysilicon layer is connected to the emitter metal layer above the emitter region, a P-type base region is arranged around each emitter region, and a P-type trench-type gate region with a higher doping concentration and a deeper depth than the base region is connected to the side of the base region, the bottom and side of each trench are covered with an insulating layer, and the side insulating layer extends to the upper surface of the silicon substrate, the gate region is connected to the gate metal layer, the upper layer of the silicon substrate below the base region and the gate region is a collector region, the lower layer of the silicon substrate is a collector, and the lower surface of the collector is connected to the collector metal layer, and the transistor is characterized in that:

[0009] The groove width of the grooved gate region is less than 1.5 μm;

[0010] The trench of the trench-type gate region is filled with polysilicon.

[0011] The technical solution of the utility model is improved over the prior art in that:

[0012] First, the resistance of the emitter metal strip of the tube core is reduced, the uniformity of the distribution of the collector-emitter current density Jce of the transistor along the emitter metal strip is improved, and the ability to resist large current impact is enhanced.

[0013] Second, the degree of reduction in the resistance of the emitter metal strip of the tube core in different parts of the whole chip, the degree of improvement in the uniformity of the distribution of the collector-emitter current density Jce of the transistor along the direction of the emitter metal strip, and the degree of enhancement in the ability to resist large current shocks are all consistent. However, the resistance of the emitter metal strip of the tube core at the peripheral part of the chip of the prior art is significantly increased, the uniformity of the distribution of the collector-emitter current density Jce of the transistor along the direction of the emitter metal strip is significantly deteriorated, and the ability to resist large current shocks is significantly reduced.

[0014] The beneficial effects of the utility model are:

[0015] The manufactured dual-gate transistor product can provide more uniform current distribution, has stronger impact resistance, can be applied to higher power, and has higher reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the structure of a dual-gate transistor in the prior art.

[0017] Figure 2 The schematic diagram is a structural diagram drawn from a scanning electron microscope image of a dual-gate transistor with an aluminum layer thickness of 4 microns according to the prior art.

[0018] Figure 3The schematic diagram is a structural diagram drawn from a scanning electron microscope image of a dual-gate transistor with an aluminum layer thickness of 8 microns according to the prior art.

[0019] Figure 4 for Figure 2 Schematic diagram of the chip periphery based on the scanning electron microscope image.

[0020] Figure 5 The figure is a schematic structural diagram of a preferred embodiment of the utility model.

[0021] Attached photos

[0022] 1: emitter metal layer; 2: P-type base region; 3: N-type emitter region; 4: silicon substrate; 41: N-type high resistivity layer; 42: N-type low resistivity layer; 5: silicon trench; 6: trench-type gate region; 7: oxide layer; 8: collector metal layer; 9: doped polysilicon layer; w: trench width of the trench-type gate region. DETAILED DESCRIPTION

[0023] First, it should be noted that the width of the silicon trench in the P-type trench gate region is Figure 5 As shown in w.

[0024] Secondly, it should be noted that the P-type trench gate region and the gate metal layer are connected behind the view, so the view cannot show them.

[0025] exist Figure 5 In the embodiment of the trench-gate polysilicon structured gate transistor shown in the figure, the lower layer 42 of the silicon substrate 4 is the collector, which is N-type silicon with a thickness of 420 μm and a resistivity of 0.01 Ω·cm, and the upper layer 41 is N-type silicon with a thickness of 65 μm and a resistivity of 40 Ω·cm. A plurality of parallel long strip grooves 5 are opened on the upper surface of the silicon substrate 4, the spacing between two adjacent grooves 5 is 18 μm, and the width of the groove 5 is 1.2 μm. The bottom of the groove is formed by injecting boron ions and pushing them forward to form a P-type high-concentration trench-type gate region 6, and the surface concentration of boron is 5E19-1E20 / cm 3 The upper surface of the silicon substrate upper layer 41 is implanted and diffused with boron ions to form a P-type base region 2. The surface concentration of boron in the P-type base region 2 is 1E18-3E18 / cm 3 The upper surface of the silicon substrate upper layer 41 is covered with a doped polysilicon layer 9 with a thickness of 0.7 μm. An insulating layer 7 composed of silicon dioxide, phosphorus silicon glass, silicon nitride or a composite thereof is separated from the doped polysilicon layer 9 and the bottom and side of the groove 5. The insulating layer 7 extends to the upper surface of the silicon substrate 4. The thickness of the insulating layer 7 is 0.3 μm. The upper surface of the silicon substrate upper layer 41 between two adjacent grooves 5 has a doping concentration of up to 1-2E20 / cm 3The N-type emitter region 3 has a depth of 3.0 μm. The N-type emitter region 3 is formed by opening a hole in the insulating layer 7, connecting the doped polysilicon layer 9 to the upper surface of the silicon substrate upper layer 41, and diffusing the N-type impurities into the upper surface of the silicon substrate upper layer 41 through the doped polysilicon layer 9. The emitter metal layer 1 is an aluminum layer with a thickness of 4 μm, and the collector metal layer 8 is a titanium, nickel, and silver three-layer metal with a thickness of 1 μm.

[0026] The following is the Figure 1 The tandem gate transistor (A for short) and Figure 5 The comparison results of the failure of the tandem gate transistor (B tube for short) of the utility model used in the electronic ballast of energy-saving lamps are shown as follows:

[0027] 1. High voltage switch impact test

[0028] The electronic ballast used for 3U energy-saving lamps has a tube length of 110mm, a tube diameter of Φ11mm, and a power of 24w. The test conditions are: input voltage 300V, 6 switches per minute, 100 tubes A and B, respectively. The results show that the average impact resistance of tube A is 100 times, and the average impact resistance of tube B is 2.2×10 4 The failure rate of tube B is 2 orders of magnitude lower than that of tube A. Therefore, the utility model can achieve higher reliability compared with the prior art.

[0029] 2. Thermal shock test

[0030] The electronic ballast for 3U energy-saving lamps has a tube length of 110mm and a tube diameter of Φ11mm. Tube A and tube B are used respectively and the circuit is adjusted accordingly to detect the maximum power that can withstand 270V shock 20 times at an ambient temperature of 85°C. The result: Tube A can only reach 20-21W, while tube B can reach 25-26W. The power of tube B is equivalent to the power of tube A, but the tube core area must be increased by 60%. It can be seen that compared with the existing technology, the utility model has a significant effect of reducing costs and improving cost performance.

[0031] It should be noted that the above embodiments are only used to illustrate the present invention rather than to limit the present invention. Therefore, for those skilled in the art, various obvious changes to the present invention without departing from the spirit and scope of the present invention should be within the scope of protection of the present invention.

Claims

1. A gate transistor with a trench-type gate polysilicon structure, wherein the upper surface of a silicon substrate having an N-type low resistivity layer as the lower layer and an N-type high resistivity layer as the upper layer has a plurality of parallel long strips of N-type high-doping concentration emitter regions, the emitter regions are connected to an N-type doped polysilicon layer, the doped polysilicon layer is connected to an emitter metal layer, each emitter region is surrounded by a P-type base region, the side of the base region is connected to a P-type trench-type gate region with a higher doping concentration and a deeper depth than the base region, the bottom and side of each trench are covered with an insulating layer, the side insulating layer extends to the upper surface of the silicon substrate, the gate region is connected to the gate metal layer, the upper layer of the silicon substrate below the base region and the gate region is a collector region, the lower layer of the silicon substrate is a collector, and the lower surface of the collector is connected to the collector metal layer, characterized in that: The groove width of the grooved gate region is less than 1.5 μm; The trench of the trench-type gate region is filled with polysilicon.

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