Inverted light emitting diode

Abstract

The utility model relates to the field of semiconductors, and discloses a flip light-emitting diode, which comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate, and the P-type semiconductor layer is provided with a groove extending to the middle of the N-type semiconductor layer; the CBL column, the transparent conductive layer and the P connection electrode are sequentially stacked on the P-type semiconductor layer, and the P connection electrode is electrically connected with the P-type semiconductor layer through the transparent conductive layer; the N connection electrode is located in the groove and is electrically connected with the N-type semiconductor layer; and the DBR layer and the reflecting interlayer are sequentially laminated and covered on other areas except the N connecting electrode and the P connecting electrode. According to the utility model, the reflectivity of each angle can be improved, so that the chip has higher brightness.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a flip-chip light emitting diode. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor diode that can convert electrical energy into light energy. The heart of LED is a semiconductor wafer, called LED chip. LED chips can be divided into upright structure, flip-chip structure and vertical structure according to different packaging methods. Compared with traditional upright structure chips, flip-chip structure chips do not require gold wire welding during the packaging process, can be driven by large current, have low chip thermal resistance and high reliability. Therefore, flip-chip structure chips have very good applications in general lighting, backlight, flash, and automotive lighting fields, and are increasingly favored by customers, and their application scope is also constantly expanding.

[0003] The DBR flip chip has good mechanical strength and mature technology. The reflectivity of DBR is higher at vertical incidence, but the reflection effect at large angles is slightly worse. Although the overall reflectivity of the metal reflective film is lower, the reflectivity at each angle is well maintained, which can make up for the lack of oblique reflection of DBR. At the same time, the active area of ​​the LED epitaxial layer emits light in a 360° circle. If the light emitted by the chip directly reaches the welding area without being processed, most of the light will be absorbed by the welding material and filling material at the bottom and cannot escape. Therefore, how to improve the reflectivity at each angle plays an important role in improving the external quantum efficiency. Utility Model Content

[0004] Purpose of the utility model: In view of the problems existing in the prior art, the utility model provides a flip-chip light emitting diode, which can improve the reflectivity at all angles and make the chip have higher brightness.

[0005] Technical solution: The utility model provides a flip-chip light-emitting diode, comprising a substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer stacked on the substrate in sequence, wherein the P-type semiconductor layer is provided with a groove extending to the middle of the N-type semiconductor layer; a CBL column, a transparent conductive layer, and a P-connecting electrode are stacked in sequence on the P-type semiconductor layer, and the P-connecting electrode is electrically connected to the P-type semiconductor layer through the transparent conductive layer; the N-connecting electrode is located in the groove and is electrically connected to the N-type semiconductor layer; a DBR layer is arranged on the P-type semiconductor layer and in the groove; a reflective interlayer is arranged on the BDR layer, and is provided with a first through hole and a second through hole for respectively exposing the N-connecting electrode and the P-connecting electrode The first insulating layer covers the reflective interlayer and the first through hole and the second through hole, and the DBR layer and the first insulating layer are provided with a third through hole and a fourth through hole respectively exposing the N connection electrode and the P connection electrode; the N electrode is electrically connected to the N connection electrode through the third through hole, and the P electrode is electrically connected to the P connection electrode through the fourth through hole; the second insulating layer covers the N electrode, the P electrode, the third through hole and the fourth through hole, and is provided with a fifth through hole and a sixth through hole respectively exposing the N electrode and the P electrode, the N pad is electrically connected to the N electrode through the fifth through hole, and the P pad is electrically connected to the P electrode through the sixth through hole, and the N connection electrode, the first through hole and the third through hole are coaxial and centrally symmetrically arranged;

[0006] And / or, the CBL column, the P connection electrode, the second through hole, and the fourth through hole are coaxial and centrally symmetrically arranged.

[0007] Furthermore, the N connection electrode and the N electrode are cylindrical structures, the first through hole and the third through hole are circular through holes, and the radius of the N connection electrode is defined as r1, the radius of the first through hole is r2, and the radius of the third through hole is r3, then r2>r1>r3 is satisfied.

[0008] Further, the CBL column, the P connection electrode and the P electrode are cylindrical structures, and the radius of the CBL column is defined as r5, the radius of the P connection electrode is defined as r6, the radius of the second through hole is defined as r7, and the radius of the fourth through hole is defined as r8, then r8<r6<r7, r6<r5, wherein the difference between r5 and r7 ranges from 0μm to 10μm,

[0009] Preferably, 1 μm<r7-r5<10 μm.

[0010] Furthermore, the first insulating layer is a single-layer structure, and the second insulating layer is a SiO2 layer or a TiO2 layer or a SiN layer;

[0011] Or, the first insulating layer is a double-layer structure, and the first insulating layer is a SIN+SIO structure or an ALD+SIO structure;

[0012] Or, the first insulating layer is a three-layer composite structure, and the first insulating layer is an ALD layer, a SIN layer and a SiO2 layer stacked in sequence;

[0013] Alternatively, the first insulating layer is a reflective layer formed by alternately stacking two different materials, and the material of the first insulating layer may be the same as or different from the material of the DBR layer.

[0014] Furthermore, the projected area of ​​the P electrode>the projected area of ​​the P pad>the projected area of ​​the CBL column>the projected area of ​​the P connection electrode.

[0015] Further, the reflective interlayer is sandwiched between the DBR layer and the first insulating layer and is not electrically connected to the flip-chip light-emitting diode;

[0016] Preferably, the reflective interlayer is a highly reflective metal layer containing Ag or Al, and the material of the reflective interlayer does not contain Au.

[0017] Furthermore, the thickness of the reflective interlayer is T4<3 μm, preferably 2KÅ<T<1 μm.

[0018] The reflectivity of the reflective interlayer at each angle is greater than 85% within the visible light range; this design can achieve preferential reflection of large-angle light, avoid DBR reflection being weak at large angles and reduce absorption of large-angle light, thereby improving light extraction efficiency.

[0019] The side wall inclination angle of the reflective interlayer is a, 5°<a<60°, preferably 5°<a<30°.

[0020] The area of ​​the reflective interlayer accounts for no less than 80% of the area of ​​the entire chip, ranging from 80% to 95%, and can be 80%, 85%, 90%, 95% or any value between any two values.

[0021] Furthermore, the inclination angle B of the third through hole is less than 60°. To ensure that the slope angle of the through hole etched in the first insulating layer is optimal, the etching angle B of the third through hole is less than 60° to avoid the upper insulating layer from breaking.

[0022] Furthermore, the DBR layer includes a TiO2 layer and a Bragg reflector DBR, and the thickness of the Bragg reflector DBR is T1<4.5 μm, and 20%<the thickness of the TiO2 layer / T1<35%.

[0023] Preferably, the thickness T1 of the Bragg reflector DBR is 2.5 μm-4 μm. In the whole design, 20%<the thickness of the TiO2 layer / T1<35%.

[0024] Furthermore, the second insulating layer is a single-layer structure, and the second insulating layer is a SiO2 layer or a TiO2 layer or a SiN layer;

[0025] Or, the second insulating layer is a double-layer structure, and the second insulating layer is a SIN+SIO structure or an ALD+SIO structure;

[0026] Or, the second insulating layer is a three-layer composite structure, and the second insulating layer is an ALD layer, a SIN layer and a SiO2 layer stacked in sequence. The second insulating layer is preferably a three-layer composite or double-layer structure, which can prevent the penetration of water vapor, etc., thereby improving product reliability; more preferably a SIN+SIO structure, because it has the function of a DBR reflective layer, which can improve brightness; the second insulating layer is most preferably an ALD, SiN, SiO2 three-layer composite insulating layer.

[0027] Furthermore, the thickness T2 of the second insulating layer is less than the thickness T3 of the first insulating layer.

[0028] Beneficial effects:

[0029] 1. The pad electrode does not avoid the through-hole design to maximize the pad area and improve the solid crystal effect. At the same time, it can realize multi-layer metal reflection and improve the large-angle light output efficiency.

[0030] 2. Setting a reflective interlayer can solve the light transmission problem caused by the lack of metal in the PN split electrode between the P electrode and the N electrode; it can achieve preferential reflection of large-angle light, avoid DBR reflection at large angles and reduce large-angle light absorption, thereby improving light extraction efficiency; it can achieve large-angle one-time reflection, and the DBR design can be optimized, and the large-angle light extraction does not need to be strengthened, so that the DBR thickness can be thinned, which can further reduce the angle of the etched through hole, thereby improving product reliability. In addition, the concentric circle design of the light-emitting diode, which is coaxial and symmetrically arranged above and below, can design the non-reflective structure on a central axis, thereby relatively increasing the relative area of ​​the reflective interlayer and further improving the reflection effect. From the plan view, the reflective interlayer is a continuous structure with a plurality of first through holes and second through holes.

[0031] 3. Setting a second insulating layer can further enhance reflection and prevent water vapor penetration, thereby improving reliability and light output. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of a top view of the flip-chip light emitting diode in this embodiment;

[0033] Figure 2 This is a schematic diagram of the AA cross-sectional structure of a flip-chip light-emitting diode in this embodiment;

[0034] Figure 3 This is a schematic diagram of the cross-sectional structure of the flip-chip light-emitting diode BB in this embodiment;

[0035] Figure 4 This is a schematic diagram of the cross-sectional structure of the flip-chip light-emitting diode CC in this embodiment;

[0036] Illustration description: 100: substrate; 200: epitaxial layer; 210: N-type semiconductor layer; 220: active layer; 230: P-type semiconductor layer; 310: CBL column; 320: transparent conductive layer; 400: DBR layer; 500: reflective interlayer; 511: first through hole; 512: second through hole; 610: first insulating layer; 611: third through hole; 612: fourth through hole; 620: second insulating layer; 621: fifth through hole; 622: sixth through hole; 710: P connecting electrode; 720: P electrode; 721: gap between P electrode and N electrode; 730: P pad; 810: N connecting electrode; 820: N electrode; 830: N pad. DETAILED DESCRIPTION

[0037] The utility model is described in detail below in conjunction with the accompanying drawings.

[0038] Implementation 1:

[0039] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings, so that those skilled in the art of the present invention can fully understand the spirit of the present invention. The present invention is not limited to the following embodiments, but can be implemented in other forms. In this specification, there are some identical symbols, which represent elements with the same or similar structures, functions, and principles, and can be inferred by those with general knowledge in the industry based on the teachings of this specification. For the sake of brevity of the specification, elements with the same symbols will not be repeated.

[0040] This embodiment provides a flip-chip light emitting diode, such as Figure 1-4As shown, it includes a substrate 100, an N-type semiconductor layer 210, an active layer 220, a P-type semiconductor layer 230, a CBL column 310, a transparent conductive layer 320 and a P-connecting electrode 710 sequentially stacked on the substrate 100, and the P-connecting electrode 710 is electrically connected to the P-type semiconductor layer 230 through the transparent conductive layer 320; a groove extending to the middle of the N-type semiconductor layer 210 is provided on the P-type semiconductor layer 230, and the N-connecting electrode 810 is located in the groove and is electrically connected to the N-type semiconductor layer 210; the DBR layer 400 is arranged on the P-type semiconductor layer 230 and in the groove; the reflective interlayer 500 is arranged on the BDR layer 400, and is provided with a first through hole 511 and a second through hole 512 for respectively exposing the N-connecting electrode 810 and the P-connecting electrode 710; the first insulating layer 610 covers the reflective interlayer 500 and the first through hole 511 and the second through hole 512, and the DBR layer 400 and the first insulating layer 6 The third through hole 611 and the fourth through hole 612 are respectively provided on the N-connecting electrode 810 and the P-connecting electrode 710; the N-electrode 820 is electrically connected to the N-connecting electrode 810 through the third through hole 611, and the P-electrode 720 is electrically connected to the P-connecting electrode 710 through the fourth through hole 612; the second insulating layer 620 covers the N-electrode 820, the P-electrode 720 and the third through hole 611 and the fourth through hole 612, and is provided with holes respectively exposing the N-electrode 820 The fifth through hole 621 and the sixth through hole 622 of the P electrode 720, the N pad 830 is electrically connected to the N electrode 820 through the fifth through hole 621, and the P pad 730 is electrically connected to the P electrode 720 through the sixth through hole 622; the projection area of ​​the P electrode 720 > the projection area of ​​the P pad 730 > the projection area of ​​the CBL column 310 > the projection area of ​​the P connection electrode 710; the thickness T2 of the second insulating layer 620 is less than the thickness T3 of the first insulating layer 610.

[0041] Specifically, as shown in the cross-sectional structure diagram of the flip-chip light-emitting diode BB surface Figure 3 As shown, the CBL column 310, the P connection electrode 710, the second through hole 512 and the fourth through hole 612 are coaxial and centrally symmetrically arranged. The CBL column 310, the P connection electrode 710 and the P electrode 720 are cylindrical structures, the radius of the CBL column 310 is r5, the radius of the P connection electrode 710 is r6, the radius of the second through hole 512 is r7, and the radius of the fourth through hole 612 is r8, then r8<r6<r5<r7, and 0μm<r7-r5<10μm.

[0042] Specifically, as shown in the CC cross-sectional structure diagram of the flip-chip light-emitting diode Figure 4As shown, the N connection electrode 810, the first through hole 511 and the third through hole 611 are coaxial and centrally symmetrically arranged; the N connection electrode 810 and the N electrode 820 are cylindrical structures, the first through hole 511 and the third through hole 611 are circular through holes, the radius of the N connection electrode 810 is r1, the radius of the first through hole 511 is r2, and the radius of the third through hole 611 is r3, then r2>r1>r3 is satisfied.

[0043] from Figure 1 From the top view, the reflective interlayer 500 is a continuous structure having a plurality of first through holes 511 and second through holes 512. The concentric circle design in the flip-chip light-emitting diode, which is coaxial and centrally symmetrical, can design the non-reflective structure on a central axis, thereby relatively increasing the relative area of ​​the reflective interlayer 500 and further improving the reflection effect.

[0044] The above-mentioned reflective interlayer 500 is a non-conductive, high-reflectivity metal layer, and its thickness T4 is less than 3μm, preferably 2KA<T<1μm; in this embodiment, the reflective interlayer 500 is a two-layer composite structure, and its bottom layer material can be selected from Al or Ag, and its upper layer material can be selected from one or more of Ti / Ni / Cr / PT. The reflective interlayer 500 plays a reflective role. The reflective interlayer 500 covers the gap 721 between the P electrode and the N electrode. This design can solve the problem of light transmission caused by the lack of metal in the PN split electrode between the P electrode 720 and the N electrode 820; the reflectivity of the reflective interlayer 500 at each angle is greater than 85% in the visible light range; this design can achieve preferential reflection of large-angle light, avoid DBR reflection at large angles and reduce large-angle light absorption, thereby improving light extraction efficiency.

[0045] The side wall inclination angle of the reflective interlayer 500 is a, 5°<a<60°. Preferably 5°<a<30°. The area of ​​the reflective interlayer 500 accounts for no less than 80% of the area of ​​the entire chip, ranging from 80%-95%, and can be 80%, 85%, 90%, 95% or any value between any two values. The inclination angle B of the third through hole 611 is less than 60°. In order to ensure that the slope angle of the through hole etched in the first insulating layer is optimal, the inclination angle B of the third through hole 611 is less than 60° to avoid the upper insulating layer from breaking.

[0046] The DBR layer 400 includes a TiO2 layer and a Bragg reflector DBR, the thickness T1 of the Bragg reflector DBR is less than 4.5 μm, and 20% is less than the thickness of the TiO2 layer / T1 is less than 35%. Preferably, the thickness T1 of the Bragg reflector DBR is 2.5 μm-4 μm. In the entire design, 20% is less than the thickness of the TiO2 layer / T1 is less than 35%. The DBR layer 400 and the first insulating layer 610 are etched, and a fourth through hole 612 is opened by ICP etching once, and the etching bevel of the fourth through hole 612 includes the DBR layer etching bevel and the first insulating layer etching bevel, that is, the DBR layer etching bevel and the first insulating layer etching bevel are the same bevel.

[0047] In one embodiment, the second insulating layer is a SiO 2 layer, a TiO 2 layer, or a SiN layer.

[0048] In the second embodiment, the second insulating layer is a SIN+SIO structure or an ALD+SIO structure. The SIN+SIO structure is preferred because it has the function of a DBR reflective layer and can improve brightness.

[0049] In the third embodiment, the second insulating layer is a three-layer composite structure of an ALD layer, a SIN layer and a SiO2 layer stacked in sequence.

[0050] Due to the characteristics of Ag metal being active and easy to precipitate, the insulating layer that the P electrode is most directly in contact with is silicon oxide, silicon nitride, ALD, etc. Among them, directly using the ALD layer for coverage can achieve defect-free coverage of the steps. From a practical point of view, the material that is in direct contact with the ALD layer can be a single layer of silicon oxide, a single layer of silicon nitride material, a single layer of silicon nitride and a single layer of silicon nitride combined film layer, or a silicon nitride / silicon oxide composite laminate structure.

[0051] In the fourth embodiment, the first insulating layer is a SiO 2 layer, a TiO 2 layer, or a SiN layer.

[0052] In the fifth embodiment, the first insulating layer is a SIN+SIO structure or an ALD+SIO structure.

[0053] In the sixth embodiment, the first insulating layer is a composite structure of an ALD layer, a SIN layer and a SiO2 layer stacked in sequence.

[0054] In the seventh embodiment, the first insulating layer is a reflective layer formed by alternately stacking two different materials. Here, the material of the first insulating layer is not limited and can be the same as or different from the material of the DBR layer.

[0055] The above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Anyone with ordinary knowledge in the technical field to which the present application belongs may modify and change the above embodiments without violating the technical principles and spirit of the present application. All equivalent changes and modifications made according to the shapes, structures, features, and spirits described in the claims of the present application shall be included in the claims of the present application.

[0056] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent transformation or modification made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A flip-chip light emitting diode, characterized in that: The invention comprises a substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer which are sequentially stacked on the substrate, wherein the P-type semiconductor layer is provided with a groove extending to the middle of the N-type semiconductor layer; a CBL column, a transparent conductive layer, and a P-connecting electrode are sequentially stacked on the P-type semiconductor layer, and the P-connecting electrode is electrically connected to the P-type semiconductor layer through the transparent conductive layer; and an N-connecting electrode is located in the groove and is electrically connected to the N-type semiconductor layer; The DBR layer is arranged on the P-type semiconductor layer and in the groove; the reflective interlayer is arranged on the DBR layer, and is provided with a first through hole and a second through hole for respectively exposing the N connection electrode and the P connection electrode; the first insulating layer covers the reflective interlayer and the first through hole and the second through hole, and the DBR layer and the first insulating layer are provided with a third through hole and a fourth through hole for respectively exposing the N connection electrode and the P connection electrode; the N electrode is electrically connected to the N connection electrode through the third through hole, and the P electrode is electrically connected to the P connection electrode through the fourth through hole; the second insulating layer covers the N electrode, the P electrode, and the third through hole and the fourth through hole, and is provided with a fifth through hole and a sixth through hole for respectively exposing the N electrode and the P electrode, the N pad is electrically connected to the N electrode through the fifth through hole, and the P pad is electrically connected to the P electrode through the sixth through hole; The N connection electrode, the first through hole, and the third through hole are coaxial and centrally symmetrically arranged vertically; And / or, the CBL column, the P connection electrode, the second through hole, and the fourth through hole are coaxially arranged vertically and centrally symmetrically.

2. The flip-chip light emitting diode according to claim 1, characterized in that: The N connection electrode is a cylindrical structure, the first through hole and the third through hole are circular through holes, and the radius of the N connection electrode is defined as r1, the radius of the first through hole is r2, and the radius of the third through hole is r3, then r2>r1>r3 is satisfied.

3. The flip-chip light emitting diode according to claim 1, characterized in that: The CBL column and the P connection electrode are cylindrical structures. The radius of the CBL column is defined as r5, the radius of the P connection electrode is defined as r6, the radius of the second through hole is defined as r7, and the radius of the fourth through hole is defined as r8. Then r8<r6<r7, r6<r5, and the difference between r5 and r7 ranges from 0μm to 10μm.

4. The flip-chip light emitting diode according to claim 1, characterized in that: The first insulating layer is a single-layer structure, and the first insulating layer is a SiO2 layer, a TiO2 layer, or a SiN layer; Or, the first insulating layer is a double-layer structure, and the first insulating layer is a SIN+SIO structure or an ALD+SIO structure; Or, the first insulating layer is a three-layer composite structure, and the first insulating layer is an ALD layer, a SIN layer and a SiO2 layer stacked in sequence; Alternatively, the first insulating layer is a reflective layer formed by alternately stacking two different materials.

5. The flip-chip light emitting diode according to claim 1, characterized in that: The second insulating layer is a single-layer structure, and the second insulating layer is a SiO2 layer, a TiO2 layer, or a SiN layer; Or, the second insulating layer is a double-layer structure, and the second insulating layer is a SIN+SIO structure or an ALD+SIO structure; Alternatively, the second insulating layer is a three-layer composite structure, and the second insulating layer is an ALD layer, a SIN layer and a SiO2 layer stacked in sequence.

6. The flip-chip light emitting diode according to claim 5, characterized in that: The thickness T2 of the second insulating layer is less than the thickness T3 of the first insulating layer.

7. The flip-chip light emitting diode according to claim 1, characterized in that: The reflective interlayer is sandwiched between the DBR layer and the first insulating layer, and is not electrically connected to the flip-chip light emitting diode.

8. The flip-chip light emitting diode according to claim 7, characterized in that: The thickness of the reflective interlayer is T4, 2KÅ<T4<1μm; the reflective interlayer is a high-reflective metal layer containing Ag or Al, and does not contain Au.

9. The flip-chip light emitting diode according to claim 7, characterized in that: The reflectivity of the reflective interlayer at each angle in the visible light range is greater than 85%; The side wall inclination angle of the reflective interlayer is a, 5°<a<60°.

10. The flip-chip light emitting diode according to claim 1, characterized in that: The DBR layer includes a TiO2 layer and a Bragg reflector DBR, and the thickness T1 of the Bragg reflector DBR is less than 4.5 μm, and 20% is less than the thickness of the TiO2 layer / T1 is less than 35%.

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