Semiconductor structure

Abstract

The utility model provides a semiconductor structure. Reduced interfacial defect density and low contact resistance can be provided for the thin film transistor by using a component-modulated cap layer. A stack may be formed over a substrate, the stack including a gate, a gate dielectric layer, an active layer including a semiconductor metal oxide material, and an in-process capping layer including a dielectric metal oxide material. A dielectric material layer may be formed, and a source cavity and a drain cavity may be formed through the dielectric material layer. The exposed portion of the in-process cap layer may be converted to a conductive material portion to provide a composition-modulated cap layer including a first conductive cap material portion, a second conductive cap material portion, and a dielectric cap material portion.

Description

Technical Field

[0001] An embodiment of the utility model relates to a semiconductor structure. Background Art

[0002] Transistors made of oxide semiconductors are attractive options for back-end-of-line (BEOL) integration because they can be processed at low temperatures and therefore will not cause damage to previously fabricated devices. For example, the fabrication conditions and fabrication techniques will not cause damage to previously fabricated front-end-of-line (FEOL) and middle end-of-line (MEOL) devices. Utility Model Content

[0003] In some embodiments disclosed herein, the semiconductor structure includes a field effect transistor. The field effect transistor includes a gate, a gate dielectric layer, an active layer, a composition-modulated cap layer, a dielectric material layer, a source structure, and a drain structure. The gate is located on a substrate. The gate dielectric layer is located on the gate. The active layer is located on the gate dielectric layer. The composition-modulated cap layer is above the active layer and includes a first conductive cap material portion, a second conductive cap material portion, and a dielectric cap material portion. The dielectric material layer is above the composition-modulated cap layer. The source structure extends vertically through the dielectric material layer and contacts the top surface of the first conductive cap material portion. The drain structure extends vertically through the dielectric material layer and contacts the top surface of the second conductive cap material portion.

[0004] In other embodiments of the present disclosure, the semiconductor structure includes a field effect transistor. The field effect transistor includes a gate, a gate dielectric layer, an active layer, a composition-modulated cap layer, a source structure, and a drain structure. The gate is located on a substrate. The gate dielectric layer is located on the gate. The active layer is located on the gate dielectric layer. The composition-modulated cap layer is above the active layer and includes a first conductive cap material portion, a second conductive cap material portion, and a dielectric cap material portion. The source structure contacts the top surface of the first conductive cap material portion. The drain structure contacts the top surface of the second conductive cap material portion. Each sidewall of the source structure and each sidewall of the drain structure include a corresponding bottom periphery, and the corresponding bottom periphery is spaced apart from the top periphery of the corresponding conductive cap material portion by a uniform offset distance.

[0005] In some other embodiments of the present disclosure, a method for forming a semiconductor structure includes: forming a stack on a substrate, the stack including a gate, a gate dielectric layer, an active layer including a semiconductor metal oxide material, and a process top cap layer including a dielectric metal oxide material; forming a dielectric material layer on the stack; forming a source cavity and a drain cavity through the dielectric material layer, so that multiple portions of the process top cap layer are exposed under the source cavity and the drain cavity; and converting the multiple portions of the process top cap layer into multiple conductive material portions, the multiple conductive material portions including a first conductive top cap material portion located below the source cavity and a second conductive top cap material portion located below the drain cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a vertical cross-sectional view of an exemplary structure after forming a complementary metal oxide semiconductor (CMOS) transistor, a first metal interconnect structure formed in a lower level dielectric layer, an insulating material layer, and an optional etch stop dielectric layer according to an embodiment of the present disclosure;

[0008] FIG. 2A to FIG. 2C are various views of a region of an intermediate structure after forming a gate contact via structure according to an embodiment of the present disclosure, Figure 2A It is a top view. Figure 2B It is along Figure 2A and Figure 2C A vertical cross-sectional view of the vertical plane BB' shown, and Figure 2C It is along Figure 2A and Figure 2B A vertical cross-sectional view of the vertical plane CC' shown;

[0009] FIG. 3A to FIG. 3C are various views of a region of an intermediate structure after forming a continuous gate material layer, a continuous gate dielectric material layer, a continuous semiconductor material layer, and a continuous metal layer according to an embodiment of the present disclosure, Figure 3A It is a top view. Figure 3B It is along Figure 3A and Figure 3C A vertical cross-sectional view of the vertical plane BB' shown, and Figure 3C It is along Figure 3A and Figure 3B A vertical cross-sectional view of the vertical plane CC' shown;

[0010] FIG. 4A to FIG. 4C are various views of a region of an intermediate structure after converting a continuous metal layer into a continuous cap material layer according to an embodiment of the present disclosure, Figure 4A It is a top view. Figure 4B It is along Figure 4A and Figure 4C A vertical cross-sectional view of the vertical plane BB' shown, and Figure 4C It is along Figure 4A and Figure 4B A vertical cross-sectional view of the vertical plane CC' shown;

[0011] FIG. 5A to FIG. 5C are various views of a region of an intermediate structure after forming a continuous insulating cap layer according to an embodiment of the present disclosure, Figure 5A It is a top view. Figure 5B It is along Figure 5A and Figure 5C A vertical cross-sectional view of the vertical plane BB' shown, and Figure 5C It is along Figure 5A and Figure 5B A vertical cross-sectional view of the vertical plane CC' shown;

[0012] FIG. 6A to FIG. 6C are various views of a region of an intermediate structure after forming a layer stack including a gate, a gate dielectric layer, an active layer, an in-process cap layer, and an insulating cap layer according to an embodiment of the present disclosure, Fig. 6A It is a top view. Figure 6B It is along Fig. 6A and Figure 6C A vertical cross-sectional view of the vertical plane BB' shown, and Figure 6C It is along Fig. 6A and Figure 6B A vertical cross-sectional view of the vertical plane CC' shown;

[0013] 7A to 7C are various views of a region of an intermediate structure after forming a dielectric material layer according to an embodiment of the present disclosure, Fig. 7A It is a top view. Figure 7B It is along Fig. 7A and Figure 7C A vertical cross-sectional view of the vertical plane BB' shown, and Figure 7C It is along Fig. 7A and Figure 7B A vertical cross-sectional view of the vertical plane CC' shown;

[0014] FIG. 8A to FIG. 8C are various views of a region of an intermediate structure after forming a source cavity and a drain cavity according to an embodiment of the present disclosure, Fig. 8A It is a top view. Figure 8B It is along Fig. 8A and Figure 8C A vertical cross-sectional view of the vertical plane BB' shown, and Figure 8C It is along Fig. 8A and Figure 8B A vertical cross-sectional view of the vertical plane CC' shown;

[0015] 9A to 9C are various views of a region of a first configuration of an intermediate structure after forming a conductive cap material portion according to an embodiment of the present disclosure, Fig.9A It is a top view. Fig. 9B It is along Fig.9A and Fig. 9C A vertical cross-sectional view of the vertical plane BB' shown, and Fig. 9C It is along Fig.9A and Fig. 9B A vertical cross-sectional view of the vertical plane CC' shown;

[0016] FIG. 10A to FIG. 10C are various views of a region of a first configuration of an embodiment structure after forming a source structure and a drain structure according to an embodiment of the present disclosure, Fig. 10A It is a top view. Fig. 10B It is along Fig. 10A and Fig. 10C A vertical cross-sectional view of the vertical plane BB' shown, and Fig. 10C It is along Fig. 10A and Fig. 10B A vertical cross-sectional view of the vertical plane CC' shown;

[0017] FIG. 11A to FIG. 11C are various views of a region of a second configuration of an embodiment structure after forming a conductive cap material portion according to an embodiment of the present disclosure, Fig.11A It is a top view. Fig. 11B It is along Fig.11A and Fig. 11C A vertical cross-sectional view of the vertical plane BB' shown, and Fig. 11C It is along Fig.11A and Fig. 11B A vertical cross-sectional view of the vertical plane CC' shown;

[0018] FIG. 12A to FIG. 12C are various views of a region of a second configuration of an embodiment structure after forming a source structure and a drain structure according to an embodiment of the present disclosure, Fig. 12A It is a top view. Fig. 12B It is along Fig. 12A and Fig. 12C A vertical cross-sectional view of the vertical plane BB' shown, and Fig. 12C It is along Fig. 12A and Fig. 12B A vertical cross-sectional view of the vertical plane CC' shown;

[0019] FIG. 13A to FIG. 13C are various views of a region of a third configuration of an embodiment structure after forming a conductive cap material portion according to an embodiment of the present disclosure, Fig.13A It is a top view. Fig. 13B It is along Fig.13A and Fig. 13C A vertical cross-sectional view of the vertical plane BB' shown, and Fig. 13C It is along Fig.13A and Fig. 13B A vertical cross-sectional view of the vertical plane CC' shown;

[0020] FIG. 14A to FIG. 14C are various views of a region of a third configuration of an embodiment structure after forming a source structure and a drain structure according to an embodiment of the present disclosure, Fig.14A It is a top view. Fig. 14B It is along Fig.14A and Fig. 14C A vertical cross-sectional view of the vertical plane BB' shown, and Fig. 14C It is along Fig.14A and Fig. 14B A vertical cross-sectional view of the vertical plane CC' shown;

[0021] Fig.15 is Figure 1 A vertical cross-sectional view of an exemplary structure of a complementary metal oxide semiconductor (CMOS) transistor, a first metal interconnect structure formed in a lower level dielectric layer, and an insulating material layer after forming optional additional embodiment transistors and other structures above the transistor;

[0022] Fig.16 is a first flow chart showing general processing steps for manufacturing the semiconductor device of the present disclosure;

[0023] Fig.17 is a second flow chart showing general processing steps for manufacturing the semiconductor device of the present disclosure;

[0024] Fig.18 is a third flow chart showing general processing steps for fabricating the semiconductor device of the present disclosure. DETAILED DESCRIPTION

[0025] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0026] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless expressly stated otherwise, elements with the same reference number are referred to as the same element and are assumed to have the same material composition and the same thickness range.

[0027] The current flow in semiconductor metal oxide materials is affected by the charge carrier concentration and the surface defect density (i.e., interface trap density). it ). As the channel length decreases, the short channel effect and back channel leakage current will adversely affect the current-voltage characteristics of transistors, especially thin-film transistors (TFTs). In addition, the high contact resistance between the source / drain structure and the semiconductor channel material may degrade the on-current and reliability of the transistor.

[0028] In general, the surface of the semiconducting metal oxide material is susceptible to the formation of various types of electronic defects and structural defects, which may occur during film deposition, gas treatment, plasma treatment and / or diffusion of impurities (e.g., diffusion of hydrogen, oxygen, water vapor and / or metal impurities). In the case where such defects are formed on the back side (opposite side) of the gate, a back channel layer including defects as trap centers may be formed. Such defects may cause leakage current. In negative bias operation, electrons may be captured in the back channel layer. The captured electrons may provide a short channel leakage path. Such leakage paths may cause uncontrolled initial negative threshold voltage (Vt) shifts and may degrade negative bias stress instability (NBTI). Reducing the charge carrier concentration in the semiconducting metal oxide material to reduce electron capture can achieve low on-current with a large positive threshold voltage shift.

[0029] According to aspects of the present disclosure, an active layer including a semiconductor metal oxide material may be formed as a main semiconductor channel of a transistor (i.e., a thin film transistor). An in-process capping layer including a dielectric metal oxide material may be formed on the active layer. The dielectric metal oxide material may be selected from materials that can reduce the interface trap density at the interface with a subsequently deposited insulating cap layer. In other words, the interface between the dielectric metal oxide material and the dielectric material of the insulating cap layer may be configured to provide a lower interface trap density than the interface between the semiconductor metal oxide material and the dielectric material of the insulating cap layer. The dielectric metal oxide material may have a band gap similar to that of the semiconductor metal oxide material (which may be in the range of from 2.5 electron volts to 3.5 electron volts). Further portions of the in-process capping layer exposed to the source cavity or the drain cavity are converted into conductive material portions. The dielectric metal oxide material includes a material that can be reduced to at least one metal when oxygen atoms are lost or a material that can be converted into a metal-rich non-stoichiometric conductive metal oxide material when ion implantation is performed using at least one metal element. Thus, a compositionally-modulated capping layer can be formed, which provides low contact resistance for the source and drain structures and reduces the interface trap density on the back side (i.e., the side away from the gate) of the semiconductor channel, and thus reduces leakage current and improves transistor characteristics.

[0030] Reference Figure 1 , Figure 1 An exemplary structure according to an embodiment of the present disclosure is shown. The exemplary structure includes a substrate 8. In general, the substrate 8 includes at least one material selected from an insulating material, a semiconductor material, and a metal material and / or is essentially composed of at least one material selected from an insulating material, a semiconductor material, and a metal material. In one embodiment, the substrate 8 may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may include a semiconductor material layer 9 at least at an upper portion of the substrate 8. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate, or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single crystal semiconductor material (e.g., single crystal silicon). In one embodiment, the substrate 8 may include a single crystal silicon substrate including a single crystal silicon material. The first exemplary structure may include a memory area 100 and a logic area 200.

[0031] A shallow trench isolation structure 720 including a dielectric material (e.g., silicon oxide) may be formed in an upper portion of the semiconductor material layer 9. A suitable doped semiconductor well (e.g., a p-type well and an n-type well) may be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 720. A field effect transistor 701 may be formed on the top surface of the semiconductor material layer 9. For example, each field effect transistor 701 may include a source 733, a drain 738, a semiconductor channel 735 including a surface portion of the substrate 8 extending between the source 733 and the drain 738, and a gate structure 750. The semiconductor channel 735 may include a single crystalline semiconductor material. Each gate structure 750 may include a gate dielectric layer 753, a gate 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 743 may be formed on each source 733, and a drain-side metal-semiconductor alloy region 748 may be formed on each drain 738.

[0032] One or more field effect transistors 701 in the CMOS circuit system 700 may include a semiconductor channel 735, which includes a portion of a semiconductor material layer 9 located in a substrate 8. In an embodiment in which the semiconductor material layer 9 includes a single crystal semiconductor material (e.g., single crystal silicon), the semiconductor channel 735 of each field effect transistor 701 in the CMOS circuit system 700 may include a single crystal semiconductor channel (e.g., a single crystal silicon channel). In one embodiment, multiple field effect transistors 701 in the CMOS circuit system 700 may include corresponding nodes, which are then electrically connected to the nodes of corresponding ferroelectric memory cells to be formed subsequently. For example, multiple field effect transistors 701 in the CMOS circuit system 700 may include corresponding sources 733 or corresponding drains 738, which are then electrically connected to the nodes of corresponding ferroelectric memory cells to be formed subsequently.

[0033] In one embodiment, the substrate 8 may include a single crystal silicon substrate, and the field effect transistor 701 may include a corresponding portion of the single crystal silicon substrate as a semiconductor channel. The "semiconducting" element used herein may refer to a device with a dielectric constant ranging from 1.0×10 -6 Siemens / cm (S / cm) to 1.0×10 5 Siemens / cm. As used herein, "semiconductor material" may refer to a semiconductor material having a conductivity ranging from 1.0×10 -6 Siemens / cm to 1.0×10 5Siemens / cm range, and when properly doped with electrical dopants, can form a conductivity ranging from 1.0 Siemens / cm to 1.0×10 5 Siemens / cm range of doped materials. As used herein, dielectric materials or insulating materials refer to materials with a conductivity less than 1.0 × 10 -6 Siemens / cm of material. All measurements were made under standard conditions (ie, at 0 degrees Celsius and 1 atmosphere pressure).

[0034] Various metal interconnect structures formed in the dielectric layer may then be formed over the substrate 8 and the semiconductor device (e.g., field effect transistor 701) located on the substrate 8. In an exemplary embodiment, the dielectric layer may include, for example, a first dielectric layer 601 (sometimes referred to as a contact level dielectric layer 601), which may be a layer surrounding the contact structure connected to the source and drain, a first interconnect level dielectric layer 610, and a second interconnect level dielectric layer 630. The metal interconnect structure may include a device contact via structure 613 formed in the first dielectric layer 601 and contacting a corresponding component of the CMOS circuit system 700, a first metal line structure 618 formed in the first interconnect level dielectric layer 610, a first metal via structure 633 formed in a lower portion of the second interconnect level dielectric layer 630, and a second metal line structure 638 formed in an upper portion of the second interconnect level dielectric layer 630.

[0035] Each of the dielectric layers (601, 610, 630) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (613, 618, 633, 638) may include at least one conductive material, which may be a combination of a metal liner (e.g., a metal nitride or a metal carbide) and a metal fill material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liners and metal fill materials within the contemplated scope of the present disclosure may also be used. In one embodiment, the first metal via structure 633 and the second metal line structure 638 may be formed as an integrated line and via structure by a dual damascene process. The dielectric layers (601, 610, 630) are referred to herein as lower level dielectric layers. The metal interconnect structures (613, 618, 633, 638) formed within the lower level dielectric layers are referred to herein as lower level metal interconnect structures.

[0036] Although the present disclosure is described using an embodiment in which transistors (e.g., thin film transistors) can be formed on the second interconnect level dielectric layer 630, other embodiments in which arrays of memory cells can be formed at different metal interconnect levels are clearly contemplated herein. In addition, although the present disclosure is described using an embodiment in which a semiconductor substrate is used as substrate 8, embodiments in which an insulating substrate or a conductive substrate is used as substrate 8 are clearly contemplated herein.

[0037] The set of all dielectric layers formed before forming an array of transistors (e.g., thin film transistors (TFTs)) or an array of memory cells (e.g., ferroelectric memory cells) is collectively referred to as lower-level dielectric layers (601, 610, 630). The set of all metal interconnect structures formed within the lower-level dielectric layers (601, 610, 630) is referred to herein as metal interconnect structures (613, 618, 633, 638). In general, the metal interconnect structures (613, 618, 633, 638) formed within at least one lower-level dielectric layer (601, 610, 630) may be formed on a semiconductor material layer 9 located in a substrate 8.

[0038] According to aspects of the present disclosure, transistors (e.g., thin film transistors (TFTs)) may then be formed in the metal interconnect level, which is above the metal interconnect level containing the lower level dielectric layer (601, 610, 630) and the metal interconnect structure (613, 618, 633, 638). In one embodiment, a planar dielectric layer having a uniform thickness may be formed above the lower level dielectric layer (601, 610, 630). The planar dielectric layer is referred to herein as an insulating material layer 635. The insulating material layer 635 includes a dielectric material (e.g., undoped silicate glass, doped silicate glass, organic silicate glass, or porous dielectric material) and may be deposited by chemical vapor deposition (CVD). The thickness of the insulating material layer 635 may range from 30 nanometers to 300 nanometers, but smaller thicknesses and larger thicknesses may also be used.

[0039] Generally, an interconnection-level dielectric layer (e.g., lower-level dielectric layer (601, 610, 630)) containing a metal interconnection structure (e.g., metal interconnection structure (613, 618, 633, 638)) may be formed on the semiconductor device. An insulating material layer 635 may be formed on the interconnection-level dielectric layer.

[0040] In one embodiment, the substrate 8 may include a single crystal silicon substrate, and a lower level dielectric layer (601, 610, 630) embedded with a lower level metal interconnect structure (613, 618, 633, 638) may be located above the single crystal silicon substrate. A field effect transistor 701 including a corresponding portion of the single crystal silicon substrate as a channel may be embedded in the lower level dielectric layer (601, 610, 630). The field effect transistor may then be electrically connected to at least one of the gate, source, and drain of one or more or each of the transistors (e.g., thin film transistors) to be formed subsequently.

[0041] An etch stop dielectric layer 636 may be formed over the insulating material layer 635, if desired. The etch stop dielectric layer 636 includes an etch stop dielectric material that provides increased etch resistance to etching chemistries during a subsequent anisotropic etching process of a dielectric material that is subsequently deposited over the etch stop dielectric layer 636. For example, the etch stop dielectric layer 636 may include silicon carbonitride, silicon nitride, silicon oxynitride, or a dielectric metal oxide such as aluminum oxide. The thickness of the etch stop dielectric layer 636 may range from 3 nanometers to 40 nanometers, such as 4 nanometers to 30 nanometers, although lesser thicknesses and greater thicknesses may also be used.

[0042] Reference FIG. 2A to FIG. 2C , FIG. 2A to FIG. 2C The region of the intermediate structure for forming a transistor (eg, a thin film transistor) after forming the gate contact via structure 12 is shown. For example, the underlying metal interconnect structure (not shown in FIG. 1 ) may be formed through the gate contact via structure 12. FIG. 2A to FIG. 2C ) and the insulating layer 635 on the corresponding one of the etching stop dielectric layer 636 and the insulating layer 635 (shown in FIG. 1 ), and at least one metal material may be deposited in the via cavity. An excess portion of the at least one metal material may be removed from above a horizontal plane (e.g., a horizontal plane formed by the direction hd1 and the direction hd2) including the top surface of the etching stop dielectric layer 636 by a planarization process (e.g., a chemical mechanical planarization process). The remaining portion of the at least one metal material constitutes the gate contact via structure 12.

[0043] Reference FIG. 3A to FIG. 3C , a continuous gate material layer 15L, a continuous gate dielectric material layer 10L, a continuous semiconductor material layer 20L and a continuous metal layer 27L may be sequentially deposited on the etching stop dielectric layer 636 .

[0044] The continuous gate material layer 15L includes at least one conductive gate material. The at least one conductive gate material may include, for example, a metal barrier liner material (e.g., TiN, TaN and / or WN) and a metal fill material (e.g., Cu, W, Mo, Co, Ru, etc.). Other suitable metal barrier liners and metal fill materials are also within the contemplated scope of the present disclosure. The continuous gate material layer 15L may be deposited by chemical vapor deposition or physical vapor deposition. The thickness of the continuous gate material layer 15L may be in the range of from 20 nanometers to 200 nanometers, but smaller thicknesses and larger thicknesses may also be used.

[0045] The continuous gate dielectric material layer 10L may be formed on the continuous gate material layer 15L. The continuous gate dielectric material layer 10L may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, etc.), or stacks thereof. Other suitable dielectric materials are also within the intended scope of the present disclosure. In a non-limiting exemplary embodiment, the continuous gate dielectric material layer 10 may include and / or may essentially consist of the following materials: at least one dielectric metal oxide material (e.g., aluminum oxide, hafnium oxide, titanium oxide, tantalum oxide, lanthanum oxide, hafnium silicate, etc.), silicon oxide, silicon nitride, oxide / nitride / oxide (ONO) stack, ferroelectric material layer, or other memory material layer known in the art. The continuous gate dielectric material layer 10L may be deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD). The thickness of the continuous gate dielectric material layer 10L may range from 1 nm to 13 nm, such as from 3 nm to 6 nm, although smaller thicknesses and larger thicknesses may also be used.

[0046] In one embodiment, the continuous semiconductor material layer 20L comprises a semiconductor metal oxide material. The continuous semiconductor material layer 20L may be an unpatterned (i.e., blanket) semiconductor material layer. In one embodiment, the continuous semiconductor material layer 20L may comprise a compound semiconductor material. In one embodiment, the semiconductor material comprises a semiconductor material that provides a voltage between 1.0 Siemens / cm and 1.0×10 5Materials with a conductivity within the range of Siemens / cm. Exemplary semiconductor materials that can be used for the continuous semiconductor material layer 20L include, but are not limited to, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. Generally, the continuous semiconductor material layer 20L may include oxides of at least one metal (e.g., at least two metals and / or at least three metals), and the at least one metal is selected from In, Zn, Ga, Sn, Pb, Zr, Sr, Ru, Mn, Mg, Nb, Ta, Hf, Al, La, Sc, Ti, V, Cr, Mo, W, Fe, Co, Ni, Pd, Ir, Ag, and any combination thereof. In a non-limiting example, the continuous semiconductor material layer 20L may have a composition of In x Ga y Zn z M a O w , where M may be at least one metal selected from Ti, Al, Ag, W, Ce, Sn, V, and Sc; 0 < x < 1; 0 ≤ y ≤ 1; 0 ≤ z ≤ 1; 0 ≤ a ≤ 0.5; and 1 ≤ w ≤ 1.5. The value of w can be selected such that the continuous semiconductor material layer 20L is stoichiometric or near stoichiometric. Some of the metal elements in the metal elements may be present at a certain doping concentration (e.g., atomic percentage less than 1.0%). Other suitable semiconductor materials are also within the scope of this disclosure. In one embodiment, the semiconductor material of the continuous semiconductor material layer 20L may include indium gallium zinc oxide.

[0047] In one embodiment, the continuous semiconductor material layer 20L includes a semiconductor metal oxide material having a first enthalpy of oxide formation and / or consists essentially of a semiconductor metal oxide material having a first enthalpy of oxide formation. The continuous semiconductor material layer 20L may include a polycrystalline semiconductor material or an amorphous semiconductor material that can subsequently be annealed into a polycrystalline semiconductor material with a larger average grain size. The continuous semiconductor material layer 20L can be deposited by physical vapor deposition, but other suitable deposition processes can also be used. The thickness of the continuous semiconductor material layer 20L may be in the range from 2 nanometers to 50 nanometers (e.g., from 3 nanometers to 30 nanometers and / or from 4 nanometers to 15 nanometers), but smaller and larger thicknesses can also be used.

[0048] The continuous metal layer 27L may be formed by depositing at least one metal that may subsequently be converted into a dielectric metal oxide material having a second enthalpy of formation greater than a first enthalpy of formation of the semiconductor metal oxide material of the continuous semiconductor material layer 20L. In embodiments where the continuous metal layer 27L includes at least two metals, an alloy of the at least two metals may have a second enthalpy of formation greater than the first enthalpy of formation of the semiconductor metal oxide material of the continuous semiconductor material layer 20L. The thickness of the continuous metal layer 27L may be in a range from 0.1 nanometers to 1.5 nanometers. The thickness of the continuous metal layer 27L may be greater than 0.1 nanometers, and / or greater than 0.2 nanometers, and / or greater than 0.3 nanometers, and / or greater than 0.5 nanometers, and / or greater than 0.7 nanometers, and / or greater than 1.0 nanometers, and / or greater than 1.2 nanometers. Furthermore, the thickness of the continuous metal layer 27L may be less than 1.5 nm, and / or less than 1.2 nm, and / or less than 1.0 nm, and / or less than 0.7 nm, and / or less than 0.5 nm, and / or less than 0.3 nm, and / or less than 0.2 nm.

[0049] The at least one metal of the continuous metal layer 27L may be selected such that a dielectric metal oxide material subsequently formed by oxidizing the at least one metal has a similar band gap as the semiconductor metal oxide material of the continuous semiconductor material layer 20L. In one embodiment, the at least one metal of the continuous metal layer 27L may be selected such that a dielectric metal oxide material subsequently formed by oxidizing the at least one metal has a higher dissolution bonding energy than the semiconductor metal oxide material of the continuous semiconductor material layer 20L. In one embodiment, the at least one metal of the continuous metal layer 27L may be selected such that a dielectric metal oxide material subsequently formed by oxidizing the at least one metal has a higher dissolution bonding energy than InO or ZnO. In general, the at least one metal of the continuous metal layer 27L may include and / or may consist of one or more transition metals that meet the above requirements. In one embodiment, the at least one metal of the continuous metal layer 27L may include one or more of Ti, Ba, Ta, W, Mo, Hf, Y, La, etc. and / or may essentially consist of one or more of Ti, Ba, Ta, W, Mo, Hf, Y, La, etc.

[0050] Reference FIG. 4A to FIG. 4C, an oxidation process may be performed to convert the continuous metal layer 27L into a semiconductor metal oxide layer composed of a dielectric metal oxide material. This semiconductor metal oxide layer serves as a cap layer for the continuous semiconductor material layer 20L and is referred to herein as a continuous cap material layer 26L. The oxidation process may include a plasma oxidation process and / or a thermal oxidation process. The continuous cap material layer 26L includes an oxide of at least one metal of the continuous metal layer and / or is essentially composed of an oxide of at least one metal of the continuous metal layer. In one embodiment, the continuous cap material layer 26L may include titanium oxide, barium oxide, tantalum oxide, tungsten oxide, molybdenum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, another transition metal oxide or an alloy thereof and / or may essentially be composed of titanium oxide, barium oxide, tantalum oxide, tungsten oxide, molybdenum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, another transition metal oxide or an alloy thereof.

[0051] The duration of the oxidation process can be selected so that the entire continuous metal layer 27L is converted into a continuous cap material layer 26L. The thickness of the continuous cap material layer 26L can be in the range of from 0.1 nanometers to 2.0 nanometers. The thickness of the continuous cap material layer 26L can be greater than 0.1 nanometers, and / or greater than 0.2 nanometers, and / or greater than 0.3 nanometers, and / or greater than 0.5 nanometers, and / or greater than 0.7 nanometers, and / or greater than 1.0 nanometers, and / or greater than 1.2 nanometers, and / or greater than 1.5 nanometers. In addition, the thickness of the continuous cap material layer 26L can be less than 2.0 nanometers, and / or less than 1.5 nanometers, and / or less than 1.2 nanometers, and / or less than 1.0 nanometers, and / or less than 0.7 nanometers, and / or less than 0.5 nanometers, and / or less than 0.3 nanometers, and / or less than 0.2 nanometers. The ratio of the thickness of the continuous cap material layer 26L to the thickness of the continuous semiconductor material layer 20L may be in a range from 0.005 to 0.5, such as from 0.01 to 0.25 and / or from 0.02 to 0.1.

[0052] In one embodiment, the semiconductor metal oxide material of the continuous semiconductor material layer 20L may have a first enthalpy of formation, and the dielectric metal oxide material of the continuous cap material layer 26L may have a second enthalpy of formation greater than the first enthalpy of formation. In one embodiment, in a temperature range greater than 400 degrees Celsius, the dielectric metal oxide material of the continuous cap material layer 26L may have greater thermal stability than InO, ZnO, and the semiconductor metal oxide material of the continuous semiconductor material layer 20L.

[0053] In general, the dielectric metal oxide material of the continuous cap material layer 26L may have a band gap that is approximately the same as the band gap of the semiconductor metal oxide material of the continuous semiconductor material layer 20L. For example, both the semiconductor metal oxide material of the continuous semiconductor material layer 20L and the dielectric metal oxide material of the continuous cap material layer 26L may have a band gap ranging from 2.5 electron volts to 3.5 electron volts. Therefore, the stack of the continuous semiconductor material layer 20L and the continuous cap material layer 26L may be used as a heterojunction semiconductor structure in which the continuous semiconductor material layer 20L is used as a main channel material and the continuous cap material layer 26L is used as a back channel surface layer that controls the magnitude of the back channel current.

[0054] In one embodiment, the dielectric metal oxide material of the continuous cap material layer 26L provides a lower interface defect density than the semiconductor metal oxide material of the continuous semiconductor material layer 20L. In an exemplary embodiment, the semiconductor metal oxide material of the continuous semiconductor material layer 20L can provide a dielectric material with a density greater than 5×10 11 / (square centimeters×electron volts), and the dielectric metal oxide material of the continuous cap material layer 26L can provide a dielectric constant between 1×10 11 / (square centimeter × electron volt) to 5×10 11 In general, the dielectric metal oxide material of the continuous cap material layer 26L can provide an interface defect density of less than 5×10 11 / (square centimeter×electron volt) of interface trap density.

[0055] By using the dielectric metal oxide material of the continuous cap material layer 26L as the back channel material in the transistor, the threshold voltage shift can suppress the shift of the threshold voltage during the operation of the transistor. For example, it is estimated that when the thin film transistor operates at 1.0×10 6 After 100 s, the threshold voltage shift in the thin film transistor using the dielectric metal oxide material of the continuous cap material layer 26L is less than 200 mV.

[0056] Reference FIG. 5A to FIG. 5C , a continuous insulating cap layer 30L may be deposited on the continuous cap material layer 26L as needed. The continuous insulating cap layer 30L includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. The continuous insulating cap layer 30L may be deposited by a chemical vapor deposition process. The thickness of the continuous insulating cap layer 30L may range from 2 nanometers to 30 nanometers (e.g., from 4 nanometers to 15 nanometers), but smaller thicknesses and larger thicknesses may also be used.

[0057] Reference FIG. 6A to FIG. 6C , a photoresist layer (not shown) may be applied on the continuous insulating cap layer 30L, and the photoresist layer may be patterned in a lithographic manner to form at least one discrete photoresist material portion, such as a two-dimensional array of discrete photoresist material portions. An anisotropic etching process may be performed to etch the unshielded portions of the continuous insulating cap layer 30L, the continuous cap material layer 26L, the continuous semiconductor material layer 20L, the continuous gate dielectric material layer 10L, and the continuous gate material layer 15L. Each patterned portion of the continuous insulating cap layer 30L includes an insulating cap layer 30. Each patterned portion of the continuous cap material layer 26L includes a cap layer 26 in the process. Each patterned portion of the continuous semiconductor material layer 20L includes an active layer 20, which is an active layer including an oxide of a binary metal alloy. Each patterned portion of the continuous gate dielectric material layer 10L includes a gate dielectric layer 10. Each patterned portion of the continuous gate material layer 15L includes a gate 15. As used herein, an "in-process" component refers to a component that is subsequently modified in shape or material composition.

[0058] Each vertical stack of gate 15, gate dielectric layer 10, active layer 20, in-process cap layer 26, and insulating cap layer 30 may have sidewalls that overlap in the vertical direction, i.e., sidewalls that are located in the same vertical plane. Each stack of gate 15 and gate dielectric layer 10 is referred to herein as gate stack (15, 10). The photoresist layer may then be removed, for example, by ashing or dissolving with a solution.

[0059] In one embodiment, each layer in the vertical stack of the gate 15, the gate dielectric layer 10, the active layer 20, the in-process cap layer 26, and the insulating cap layer 30 may have the same area in a plan view (e.g., a perspective top view) along a vertical direction perpendicular to the interface between the active layer 20 and the gate dielectric layer 10. In one embodiment, the gate 15 extends horizontally in the lateral direction with a uniform gate thickness and has the same area as the active layer 20, the gate dielectric layer 10, the in-process cap layer 26, and the insulating cap layer 30 in a plan view.

[0060] Reference 7A to 7CA dielectric material (e.g., undoped silicate glass, doped silicate glass, or organosilicate glass) may be deposited on each stack of the gate 15, the gate dielectric layer 10, the active layer 20, the in-process cap layer 26, and the insulating cap layer 30 to form a dielectric material layer 40. The dielectric material layer 40 may be deposited by a self-planarizing deposition method (e.g., spin coating), or the dielectric material layer 40 may be planarized after deposition (e.g., by performing a chemical mechanical polishing process). The vertical distance between the top surface of each insulating cap layer 30 and the top surface of the dielectric material layer 40 may be in the range of from 20 nanometers to 200 nanometers, but smaller thicknesses and larger thicknesses may also be used.

[0061] Reference FIG. 8A to FIG. 8C A photoresist layer (not shown) may be applied on the dielectric material layer 40, and the photoresist layer may be patterned by lithography to form discrete openings in the photoresist layer. The pattern of the discrete openings in the photoresist layer may be transferred through the dielectric material layer 40 and the insulating cap layer 30 by an anisotropic etching process to form a source cavity 51 and a drain cavity 59 on each active layer 20.

[0062] According to aspects of the present disclosure, the anisotropic etching process may have an etching chemistry that selectively etches the material of the dielectric material layer 40 and the material of the insulating cap layer 30 relative to the material of the process cap layer 26. In other words, the anisotropic etching process may etch the material of the dielectric material layer 40 and the material of the insulating cap layer 30 without etching the material of the process cap layer 26. In this embodiment, the process cap layer 26 is used as an etching stop layer for the anisotropic etching process. Portions of the process cap layer 26 may be physically exposed at the bottom of the source cavity 51 and the bottom of the drain cavity 59. The top surface of the active layer 20 may be covered by the process cap layer 26. The process cap layer 26 may have a uniform thickness throughout.

[0063] The lateral spacing between the bottom periphery of the source cavity 51 and the bottom periphery of the drain cavity 59 defines the channel length of the transistor (e.g., TFT) to be subsequently formed. The channel length may be in the range of 1 nanometer to 100 nanometers (e.g., 2 nanometers to 50 nanometers), but smaller channel lengths and larger channel lengths may also be used. The top cap layer 26 protects the active layer 20 from plasma damage during the process. Therefore, the defect density of the semiconductor metal oxide material in the active layer 20 is not increased due to the anisotropic etching process for forming the source cavity 51 and the drain cavity 59. In addition, relative to the hypothetical structure in which the active layer 20 is in direct contact with the insulating top cap layer 30, the dielectric metal oxide material of the top cap layer 26 during the process provides a reduced interface defect density D at the interface with the insulating top cap layer 30.it For example, the cap layer 26 has a thickness of less than 5×10 11 / (square centimeter×electron volt) of interface trap density.

[0064] During the formation of the source cavity 51 and the drain cavity 59, the in-process cap layer 26 may be used as an etch stop layer. During the anisotropic etching process to form the source cavity 51 and the drain cavity 59, the collateral etching of the material of the in-process cap layer 26 is preferably minimized. In one embodiment, the thickness of the remaining portion of the in-process cap layer 26 located below the source cavity 51 or the drain cavity 59 may be greater than 30%, and preferably greater than 50%, and even more preferably greater than 70%, and / or greater than 80%, and / or greater than 90%, and / or greater than 95% of the thickness of the in-process cap layer 26 before the anisotropic etching process.

[0065] Reference 9A to 9C , 9A to 9C A region of a first configuration of an embodiment structure after forming a composition-modulated cap layer 28 is shown. Specifically, a reduction process may be performed on the exposed portion of the in-process cap layer 26. The dielectric metal oxide material within the exposed portion of the in-process cap layer 26 is reduced to at least one metal without oxygen. In other words, during the reduction process, oxygen atoms in the exposed portion of the in-process cap layer 26 are removed, thereby reducing the dielectric metal oxide material of the physically exposed portion of the in-process cap layer 26 to a metallic material portion essentially consisting of the at least one metal (such as the at least one metal provided in the continuous cap material layer 26L). In one embodiment, the reduction process includes a hydrogen plasma treatment process. The hydrogen plasma reacts with the oxygen atoms in the in-process cap layer 26 to produce water vapor, which is volatilized and pumped out of the plasma treatment chamber. The atoms of the at least one metal that has lost the oxygen atoms coalesce to form a metal plate, which includes the conductive cap material portion 28M.

[0066] The plasma intensity and duration of the hydrogen plasma treatment process may be selected so that each portion of the cap layer 26 that has an areal overlap with the source cavity 51 or with the drain cavity 59 in a plan view is converted into a metal material portion, which is referred to herein as a conductive cap material portion 28M. The conductive cap material portion 28M may have the same material composition as the continuous metal layer 27L. For example, the conductive cap material portion 28M may include titanium, barium, tantalum, tungsten, molybdenum, hafnium, yttrium, lanthanum, another transition metal or an alloy thereof and / or may consist essentially of titanium, barium, tantalum, tungsten, molybdenum, hafnium, yttrium, lanthanum, another transition metal or an alloy thereof. Each conductive cap material portion 28M may consist essentially of the at least one metal and may provide a sheet resistance of less than 100 Ohms per square.

[0067] The portion of the cap layer 26 that is not reduced to the metal material during the process constitutes the dielectric cap material portion 28D. In general, the loss of oxygen atoms may reduce the thickness of the conductive cap material portion 28M relative to the thickness of the dielectric cap material portion 28D. The thickness of each conductive cap material portion 28M may be in the range of 40% to 70% of the thickness of the dielectric cap material portion 28D.

[0068] In general, the physically exposed portion of the cap layer 26 during the process can be converted into a first conductive cap material portion 28M located below the source cavity 51 and converted into a second conductive cap material portion 28M located below the drain cavity 59. The dielectric cap material portion 28D includes the remaining portion of the dielectric metal oxide material. The combination of the dielectric cap material portion 28D and the conductive cap material portion 28M constitutes a composition-modulated cap layer 28. Therefore, during the process, the cap layer 26 can be converted into a composition-modulated cap layer 28.

[0069] The composition-modulated cap layer 28 is on the active layer 20 and includes a first conductive cap material portion 28M, a second conductive cap material portion 28M, and a dielectric cap material portion 28D. The dielectric metal oxide material is an oxide of at least one metal, and the first conductive cap material portion 28M and the second conductive cap material portion 28M include the at least one metal and / or consist essentially of the at least one metal. In one embodiment, the first conductive cap material portion 28M and the second conductive cap material portion 28M are formed by reducing the dielectric metal oxide to the at least one metal. Reducing the dielectric metal oxide to the at least one metal is achieved by performing a hydrogen plasma treatment process.

[0070] The plasma reduction process isotropically reduces the material of the physically exposed portion of the in-process cap layer 26. The plasma energy and plasma duration during the plasma reduction process may be selected such that the boundary between the reduced portion of the in-process cap layer 26 (i.e., the conductive cap material portion 28M) and the unreduced portion of the in-process cap layer 26 (i.e., the dielectric cap material portion 28D) is offset by a distance greater than the thickness of the in-process cap layer 26. In one embodiment, each sidewall of the source structure 52 and each sidewall of the drain structure 56 include a respective bottom perimeter that is spaced apart from the top perimeter of the respective conductive cap material portion 28M by a uniform offset distance uod, which is the plasma reduction distance. The plasma reduction distance may be in the range of 100% to 150% (e.g., 100% to 120%) of the thickness of the in-process cap layer 26 (the same as the thickness of the dielectric cap material portion 28D). Each sidewall of the source cavity 51 and the drain cavity 59 includes a respective bottom perimeter that is spaced apart from a top perimeter of a respective conductive cap material portion 28M by a uniform offset distance uod, which may be a plasma reduction distance.

[0071] In general, the material composition of the conductive cap material portion 28M may be the same as the material composition of the continuous metal layer 27L and may be composed of the at least one metal of the continuous metal layer 27L. If the continuous metal layer 27L includes at least two metals, the conductive cap material portion 28M may also include the at least two metals. Each atomic ratio between the at least two metals in the conductive cap material portion 28M may be the same as the corresponding atomic ratio between the at least two metals in the continuous metal layer 27L. In addition, each atomic ratio between the at least two metals in the dielectric cap material portion 28D is equal to the corresponding atomic ratio between the at least two metals in the first conductive cap material portion 28M and in the second conductive cap material portion 28M. In one embodiment, the first conductive cap material portion 28M and the second conductive cap material portion 28M may be metal portions without oxygen atoms.

[0072] As discussed above, during the anisotropic etching process to form the source cavity 51 and the drain cavity 59, incidental etching of the material of the top cap layer 26 in the process is preferably minimized. After the anisotropic etching process, the thickness of the conductive top cap material portion 28M is proportional to the thickness of the remaining portion of the top cap layer 26 in the process located below the source cavity 51 or the drain cavity 59. The area density of the at least one metal in the conductive top cap material portion 28M may be greater than that in the anisotropic etching process. FIG. 4A to FIG. 4C30%, and preferably greater than 50%, and even more preferably greater than 70%, and / or greater than 80%, and / or greater than 90%, and / or greater than 95% of the areal density of the at least one metal within the continuous cap material layer 26L formed in the process step shown. In one embodiment, the first areal density of the at least one metal obtained by integrating the volume density of the at least one metal along the vertical direction within the first conductive cap material portion 28M is in the range of 30% to 100% (e.g., 50% to 90% and / or 60% to 80%) of the second areal density of the at least one metal obtained by integrating the volume density of the at least one metal along the vertical direction within the dielectric cap material portion 28D. The areal density of an element as used herein refers to the value generated by integrating the volume density of the element along the thickness direction (e.g., the vertical direction).

[0073] Reference FIG. 10A to FIG. 10C , FIG. 10A to FIG. 10C A region of a first configuration of an embodiment structure is shown after forming a source structure 52 and a drain structure 56. At least one conductive material may be deposited in the source cavity 51 and the drain cavity 59 and on the dielectric material layer 40. The at least one conductive material may include a metal liner material and a metal fill material. The metal liner material may include a conductive metal nitride or a conductive metal carbide, such as TiN, TaN, WN, TiC, TaC and / or WC. The metal fill material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof and / or combinations thereof. Other suitable metal liner materials and metal fill materials within the contemplated scope of the present disclosure may also be used.

[0074] Excess portions of the at least one conductive material may be removed from above a level including the top surface of the dielectric material layer 40 by a planarization process, which may use a chemical mechanical polishing (CMP) process and / or a recess etch process. Other suitable planarization processes may also be used. Each remaining portion of the at least one conductive material filling the source cavity 51 constitutes a source structure 52. Each remaining portion of the at least one conductive material filling the drain cavity 59 constitutes a drain structure 56. In one embodiment, the at least one conductive material may include a combination of the above-mentioned metal liner material and the metal fill material.

[0075] In one embodiment, each source structure 52 may include a source metal liner 53 as a remaining portion of the metal liner material and a source metal fill material portion 54 as a remaining portion of the metal fill material. Each drain structure 56 may include a drain metal liner 57 as a remaining portion of the metal liner material and a drain metal fill material portion 58 as a remaining portion of the metal fill material.

[0076] The composition-modulated cap layer 28 is on the active layer 20 and includes a first conductive cap material portion 28M, a second conductive cap material portion 28M, and a dielectric cap material portion 28D. The insulating cap layer 30 is on the composition-modulated cap layer 28. The dielectric material layer 40 is on the insulating cap layer 30 and laterally surrounds the source structure 52, the drain structure 56, the active layer 20 on the gate dielectric layer 10, and the composition-modulated cap layer 28.

[0077] The source structure 52 may be formed in the source cavity 51, and the drain structure 56 may be located in the drain cavity 59. The source structure 52 and the drain structure 56 may be formed on the first conductive cap material portion 28M and the second conductive cap material portion 28M, respectively. The source structure 52 may extend vertically through the dielectric material layer 40 and the insulating cap layer 30 and may contact the top surface of the first conductive cap material portion 28M. The drain structure 56 may extend vertically through the dielectric material layer 40 and the insulating cap layer 30 and may contact the top surface of the second conductive cap material portion 28M. In one embodiment, each sidewall of the source structure 52 and the drain structure 56 includes a corresponding bottom perimeter, and the corresponding bottom perimeter is spaced apart from the top perimeter of the corresponding conductive cap material portion 28M by a uniform offset distance uod.

[0078] Reference FIG. 11A to FIG. 11C , FIG. 11A to FIG. 11C The second configuration of the embodiment structure is shown after forming the conductive cap material portion 28I. FIG. 8A to FIG. 8CThe exemplary structure shown in the second configuration of the exemplary structure is obtained, and the ion implantation process implants atoms of at least one additional metal into the portion of the top cap layer 26 in the process that is physically exposed. The at least one additional metal may include any transition metal, aluminum, indium, or gallium. The at least one additional metal may be the same as one or more of the at least one metal in the top cap layer 26 in the process or may be different from one or more of the at least one metal in the top cap layer 26 in the process. In one embodiment, the at least one additional metal implanted into the portion of the top cap layer 26 in the process that is physically exposed may be different from each of the at least one metal in the top cap layer 26 in the process. In one embodiment, the at least one additional metal may include one or more transition metal elements (such as refractory metal elements (refractory metal elements) (e.g., tungsten, niobium, molybdenum, tantalum, and rhenium)) that exhibit low diffusion rates.

[0079] By introducing atoms of the at least one additional metal into the exposed portion of the in-process cap layer 26, the exposed portion of the in-process cap layer 26 may not be converted into a metal-rich metal oxide material portion. The atoms of the at least one additional metal may be introduced into the in-process cap layer 26 by performing an ion implantation process. According to aspects of the present disclosure, the energy of the ions of the at least one additional metal may be selected so that a major portion (i.e., greater than 50%) of the implanted ions are implanted into the physically exposed portion of the in-process cap layer 26. In addition, the dose of the implanted ions may be selected so that the metal-rich metal oxide material portion becomes conductive. The metal-rich conductive metal oxide material portion is referred to herein as a conductive cap material portion 28I.

[0080] The oxygen deficiency ratio of the conductive cap material portion 28I can be defined as the ratio of a first number, which is the number of additional oxygen atoms required to convert the material of the conductive cap material portion 28I into a stoichiometric dielectric metal oxide material, to a second number, which is the total number of oxygen atoms in the stoichiometric dielectric metal oxide material. The oxygen deficiency ratio of the conductive cap material portion 28I can be in a range from 0.1 to 0.8 (e.g., from 0.15 to 0.6, and / or from 0.2 to 0.5, and / or from 0.25 to 0.4).

[0081] In general, the physically exposed portion of the cap layer 26 during the process may be converted into a conductive material portion, the conductive material portion including a first conductive cap material portion 28I located below the source cavity 51 and a second conductive cap material portion 28I located below the drain cavity 59. The portion of the cap layer 26 during the process into which the atoms of the at least one additional metal are not implanted is referred to herein as a dielectric cap material portion 28D. In one embodiment, the dielectric metal oxide material of the dielectric cap material portion 28D is an oxide of at least one metal, and the first conductive cap material portion 28I and the second conductive cap material portion 28I include the at least one metal in the dielectric metal oxide material and further include atoms of the at least one additional metal introduced by an ion implantation process. In one embodiment, the first conductive cap material portion 28I and the second conductive cap material portion 28I may be non-stoichiometric conductive metal oxide portions and may be formed by implanting atoms of the at least one additional metal different from the at least one metal.

[0082] In one embodiment, the energy of the ion implantation may be selected such that the atomic concentration of the at least one additional metal in the first conductive cap material portion 28I and the second conductive cap material portion 28I decreases with vertical distance downward from a horizontal plane including the top surface of the first conductive cap material portion 28I and the top surface of the second conductive cap material portion 28I. In one embodiment, the implanted atoms of the at least one additional metal generally increase the thickness of the implanted portion of the cap layer 26 during the process. In one embodiment, the dose of the ion implantation process may be selected such that the conductive cap material portion 28I has a thickness greater than the thickness of the dielectric cap material portion 28D.

[0083] The top surfaces of the first conductive cap material portion 28I and the second conductive cap material portion 28I include atoms of the at least one metal present in the dielectric cap material portion 28D. In one embodiment, a portion of the implanted ions of the at least one additional metal may remain in a portion of the active layer 20 near the conductive cap material portion 28I, and the implanted portion of the active layer is rendered non-stoichiometric (i.e., metal-rich) due to the presence of the atoms of the at least one additional metal. In this embodiment, a source-side metal-rich metal oxide region 22S may be formed under the first conductive cap material portion 28I located under the source cavity 51, and a drain-side metal-rich metal oxide region 22D may be formed under the second conductive cap material portion 28I located under the drain cavity 59. The thickness of the source-side metal-rich metal oxide region 22S and the thickness of the drain-side metal-rich metal oxide region 22D may be in a range from 0.1 nanometers to 2 nanometers (e.g., from 0.2 nanometers to 1 nanometer). In one embodiment, the atomic concentration of atoms of the at least one additional metal may decrease with downward distance from a horizontal plane including the top surface of the conductive cap material portion 28I.

[0084] As discussed above, during the anisotropic etching process to form the source cavity 51 and the drain cavity 59, incidental etching of the material of the in-process cap layer 26 is preferably minimized. After the anisotropic etching process, the thickness of the conductive cap material portion 28I is generally proportional to the thickness of the remaining portion of the in-process cap layer 26 located below the source cavity 51 or the drain cavity 59. The areal density of the at least one metal in the conductive cap material portion 28I may be greater than that during the anisotropic etching process. FIG. 4A to FIG. 4C 30%, and preferably greater than 50%, and even more preferably greater than 70%, and / or greater than 80%, and / or greater than 90%, and / or greater than 95% of the areal density of the at least one metal in the continuous cap material layer 26L formed in the process step shown. In one embodiment, the first areal density of the at least one metal obtained by integrating the volume density of the at least one metal along the vertical direction in the first conductive cap material portion 28I is in the range of 30% to 100% (e.g., 50% to 90% and / or 60% to 80%) of the second areal density of the at least one metal obtained by integrating the volume density of the at least one metal along the vertical direction in the dielectric cap material portion 28D.

[0085] In one embodiment, the number of metal atoms implanted in the conductive cap material portion 28I may be greater than the number of pre-existing metal atoms provided in the physically exposed portion of the cap layer 26 in the process. In this embodiment, the surface density of the at least one metal obtained by integrating the density of the at least one metal in the first conductive cap material portion 28I (or in the second conductive cap material portion 28I) along the vertical direction may be less than the total surface density of the at least one additional metal obtained by integrating the volume density of the at least one additional metal in the first conductive cap material portion 28I (or in the second conductive cap material portion 28I) along the vertical direction. In some embodiments, the oxygen deficiency ratio of the conductive cap material portion 28I may be in the range of from 0.5 to 0.8.

[0086] Reference FIG. 12A to FIG. 12C , FIG. 12A to FIG. 12C A region of a second configuration of the exemplary structure is shown after forming source structure 52 and drain structure 56. In general, reference may be made to FIG. 10A to FIG. 10C The processing steps described are used to form source structures 52 and drain structures 56. In one embodiment, each source structure 52 may include a source metal liner 53 and a source metal fill material portion 54. Each drain structure 56 may include a drain metal liner 57 and a drain metal fill material portion 58.

[0087] The composition-modulated cap layer 28 is on the active layer 20 and includes a first conductive cap material portion 28I, a second conductive cap material portion 28I and a dielectric cap material portion 28D. The insulating cap layer 30 is on the composition-modulated cap layer 28. The dielectric material layer 40 is on the insulating cap layer 30 and laterally surrounds the source structure 52, the drain structure 56, the active layer 20 on the gate dielectric layer 10, and the composition-modulated cap layer 28.

[0088] The source structure 52 may be formed in the source cavity, and the drain structure 56 may be located in the drain cavity. The source structure 52 and the drain structure 56 may be formed on the first conductive cap material portion 28I and the second conductive cap material portion 28I, respectively. The source structure 52 may extend vertically through the dielectric material layer 40 and the insulating cap layer 30 and may contact the top surface of the first conductive cap material portion 28I. The drain structure 56 may extend vertically through the dielectric material layer 40 and the insulating cap layer 30 and may contact the top surface of the second conductive cap material portion 28I. In one embodiment, each sidewall of the source structure 52 and each sidewall of the drain structure 56 include a corresponding bottom periphery, and the corresponding bottom periphery is spaced apart from the top periphery of the corresponding conductive cap material portion 28I by a uniform offset distance uod.

[0089] Reference FIG. 13A to FIG. 13C , FIG. 13A to FIG. 13C A third configuration of the exemplary structure after forming the conductive cap material portion 28I according to an embodiment of the present disclosure is shown. The third configuration of the exemplary structure can be obtained from the second configuration of the exemplary structure by adjusting the energy of the ion implantation process, and the ion implantation process is performed to implant atoms of the at least one additional metal. Specifically, the energy of the ion implantation process can be reduced so that the implanted ions do not enter the active layer 20. In this embodiment, the source-side metal-rich metal oxide region 22S and the drain-side metal-rich metal oxide region 22D are not formed in the third configuration of the exemplary structure. The conductive cap material portion 28I can be in direct contact with the top surface of the active layer 20. In general, the third configuration of the exemplary structure can have the same structural features and compositional features as the second configuration of the exemplary structure, except that the second configuration of the exemplary structure has the source-side metal-rich metal oxide region 22S and the drain-side metal-rich metal oxide region 22D.

[0090] The atomic concentration of the at least one additional metal in the first conductive cap material portion 28I and the second conductive cap material portion 28I decreases with the vertical distance downward from a horizontal plane including the top surface of the first conductive cap material portion 28I and the top surface of the second conductive cap material portion 28I. In one embodiment, the implanted atoms of the at least one additional metal generally increase the thickness of the implanted portion of the cap layer 26 during the process. In one embodiment, the dose of the ion implantation process can be selected so that the conductive cap material portion 28I has a thickness greater than the thickness of the dielectric cap material portion 28D.

[0091] Reference FIG. 14A to FIG. 14C , FIG. 14A to FIG. 14C A region of a third configuration of the embodiment structure is shown after forming source structure 52 and drain structure 56. In general, reference may be made to FIG. 10A to FIG. 10C The processing steps described are used to form source structures 52 and drain structures 56. In one embodiment, each source structure 52 may include a source metal liner 53 and a source metal fill material portion 54. Each drain structure 56 may include a drain metal liner 57 and a drain metal fill material portion 58.

[0092] The composition-modulated cap layer 28 is on the active layer 20 and includes a first conductive cap material portion 28I, a second conductive cap material portion 28I and a dielectric cap material portion 28D. The insulating cap layer 30 is on the composition-modulated cap layer 28. The dielectric material layer 40 is on the insulating cap layer 30 and laterally surrounds the source structure 52, the drain structure 56, the active layer 20 on the gate dielectric layer 10, and the composition-modulated cap layer 28.

[0093] The source structure 52 may be formed in the source cavity, and the drain structure 56 may be located in the drain cavity. The source structure 52 and the drain structure 56 may be formed on the first conductive cap material portion 28I and the second conductive cap material portion 28I, respectively. The source structure 52 may extend vertically through the dielectric material layer 40 and the insulating cap layer 30 and may contact the top surface of the first conductive cap material portion 28I. The drain structure 56 may extend vertically through the dielectric material layer 40 and the insulating cap layer 30 and may contact the top surface of the second conductive cap material portion 28I. In one embodiment, each sidewall of the source structure 52 and each sidewall of the drain structure 56 include a corresponding bottom periphery, and the corresponding bottom periphery is spaced apart from the top periphery of the corresponding conductive cap material portion 28I by a uniform offset distance uod.

[0094] Reference Fig.15 , Fig.15 The embodiment structure is shown after performing additional processing steps. FIG. 10A to FIG. 10C , FIG. 12A to FIG. 12C or FIG. 14A to FIG. 14C The additional structure is formed on any configuration of the embodiment structure shown in the embodiment and obtained from any of the configurations Fig.15 In some embodiments, the second metal via structure 632 may be formed through the dielectric material layer 40 and the insulating material layer 635 on a respective one of the third metal line structures 639 at the same time, before, or after forming the source structure 52 and the drain structure 56 .

[0095] A dielectric layer referred to herein as a third line level dielectric layer 637 may be deposited over dielectric material layer 40. A third metal line structure 639 may be formed in third line level dielectric layer 637 on a respective one of the metal structures (52, 56, 632) embedded within dielectric material layer 40.

[0096] An additional metal interconnect structure embedded in the additional dielectric layer may then be formed over the transistor (e.g., thin film transistor) and the third line-level dielectric layer 637. In an exemplary embodiment, the dielectric layer may include, for example, a fourth interconnect-level dielectric layer 640, a fifth interconnect-level dielectric layer 650, etc. The additional metal interconnect structure may include a third metal via structure (not shown) and a fourth metal line 648 embedded in the fourth interconnect-level dielectric layer 640, a fourth metal via structure 652 and a fifth metal line structure 658 embedded in the fifth interconnect-level dielectric layer 650, etc.

[0097] The memory cell 150 may be formed below the transistor, above the transistor, or at the same level as the transistor as desired. In an embodiment in which the transistor is formed as a two-dimensional periodic array, the memory cell 150 may be formed as a two-dimensional periodic array of memory cells 150. Each memory cell 150 may include a magnetic tunnel junction, a ferroelectric tunnel junction, a phase change memory material, or a vacancy-modulated conductive oxide material portion. In addition, each memory cell 150 may include a first electrode 126 containing a metal material and a second electrode 158 containing a metal material and protecting an underlying data storage portion of the memory cell 150. A memory element is disposed between the first electrode 126 (i.e., the bottom electrode) and the second electrode 158 (i.e., the top electrode).

[0098] In an exemplary example, in an embodiment in which the memory cell 150 includes a magnetic tunneling junction, the memory cell 150 may include a layer stack including, from bottom to top, a first electrode 126, a metal seed layer 128 that facilitates crystalline growth of an overlying material layer, a synthetic antiferromagnet (SAF) structure 140, a tunnel barrier layer 146, a free magnetic layer 148, and a second electrode 158. Although the present disclosure is described using an embodiment in which a transistor (e.g., a thin film transistor) is used as an access transistor of the memory cell 150, embodiments in which the transistor is used as a logic device, as a component of a peripheral circuit of a memory array, or for any other semiconductor circuit system are also expressly contemplated herein.

[0099] In one embodiment, the substrate 8 may include a single crystal silicon substrate. A lower level dielectric layer (601, 610, 630) embedded with a lower level metal interconnect structure (613, 618, 633, 638) may be located between the single crystal silicon substrate and the insulating layer 635. A field effect transistor 701 including a corresponding portion of the single crystal silicon substrate as a channel may be embedded in the lower level dielectric layer (601, 610, 630) and may be electrically connected to at least one of the gate 15, the source structure 52, and the drain structure 56.

[0100] Reference Fig.16 , a first flow chart illustrates general processing steps for manufacturing the semiconductor device of the present disclosure.

[0101] Refer to step 1610 and Figures 1 to 6CA stack may be formed on the substrate 8. The stack includes a gate 15, a gate dielectric layer 10, an active layer 20 including a semiconductor metal oxide material, and an in-process cap layer 26 including a dielectric metal oxide material.

[0102] Refer to step 1620 and 7A to 7C , a dielectric material layer 40 may be formed over the stack.

[0103] Refer to step 1630 and FIG. 8A to FIG. 8C , a source cavity 51 and a drain cavity 59 may be formed through the dielectric material layer 40 , such that portions of the in-process cap layer 26 are exposed below the source cavity 51 and the drain cavity 59 .

[0104] Refer to step 1640 and FIG. 9A to FIG. 1 4. The multiple portions of the top cap layer 26 in the process can be converted into conductive material portions, wherein the conductive material portions include a first conductive top cap material portion (28M, 28I) located below the source cavity 51 and a second conductive top cap material portion (28M, 28I) located below the drain cavity 59.

[0105] In one embodiment, the method may further include: forming a source structure 52 in the source cavity 51; and forming a drain structure 56 in the drain cavity 59. In one embodiment, the method may further include performing a reduction process on the exposed portions of the in-process cap layer 26, thereby reducing the dielectric metal oxide material within the portions of the in-process cap layer 26 to at least one metal without oxygen. In one embodiment, the reduction process includes a hydrogen plasma treatment process.

[0106] In one embodiment, the method further includes converting the exposed portions of the in-process cap layer 26 into metal-rich metal oxide material portions by introducing atoms of at least one metal into the exposed portions of the in-process cap layer 26. In one embodiment, the atoms of the at least one metal are introduced into the in-process cap layer 26 by performing an ion implantation process.

[0107] Reference Fig.17 , the second flow chart illustrates general processing steps for manufacturing the semiconductor device of the present disclosure.

[0108] Refer to step 1710 and Figures 1 to 6C A stack may be formed on the substrate 8, the stack including a gate 15, a gate dielectric layer 10, an active layer 20 including a semiconductor metal oxide material, and an in-process cap layer 26 including a dielectric metal oxide material.

[0109] Refer to step 1720 and 7A to 9C , FIG. 11A to FIG. 11C and FIG. 13A to FIG. 13C , the in-process cap layer 26 can be converted into a composition-modulated cap layer 28. The composition-modulated cap layer includes a first conductive cap material portion (28M, 28I) and a second conductive cap material portion (28M, 28I) formed by converting multiple portions of dielectric metal oxide into conductive material portions and includes a dielectric cap material portion 28D which is a remaining portion of the dielectric metal oxide material.

[0110] Refer to step 1730 and FIG. 10A to FIG. 10C , FIG. 12A to FIG. 12C , FIG. 14A to FIG. 14C and Fig.15 , a source structure 52 and a drain structure 56 may be formed on the first conductive cap material portion ( 28M, 28I) and the second conductive cap material portion ( 28M, 28I), respectively.

[0111] In one embodiment, the method further includes: forming a dielectric material layer 40 over the stack; and forming a source cavity 51 and a drain cavity 59 through the dielectric material layer 40, wherein the portions of the dielectric metal oxide that are subsequently converted to the conductive material portions are exposed below the source cavity 51 and the drain cavity 59. In one embodiment, a source structure 52 is formed in the source cavity 51; and a drain structure 56 is formed in the drain cavity 59. In one embodiment, the stack includes an insulating cap layer 30 over the in-process cap layer 26; and the source cavity 51 and the drain cavity 59 are formed by performing an anisotropic etch chemistry that selectively etches the material of the dielectric material layer 40 and the material of the insulating cap layer 30 relative to the dielectric metal oxide.

[0112] In one embodiment, the dielectric metal oxide material is an oxide of at least one metal; and the first conductive cap material portion (28M, 28I) and the second conductive cap material portion (28M, 28I) include the at least one metal. In one embodiment, the first conductive cap material portion 28M and the second conductive cap material portion 28M consist essentially of the at least one metal. In one embodiment, the first conductive cap material portion 28M and the second conductive cap material portion 28M are formed by reducing the dielectric metal oxide to the at least one metal. In one embodiment, reducing the dielectric metal oxide to the at least one metal is achieved by performing a hydrogen plasma treatment process.

[0113] In one embodiment, the first conductive top cap material portion 28I and the second conductive top cap material portion 28I are non-stoichiometric metal oxide portions. In one embodiment, the first conductive top cap material portion 28I and the second conductive top cap material portion 28I are formed by implanting atoms of at least one additional metal different from the at least one metal. In one embodiment, the atomic concentration of the at least one additional metal in the first conductive top cap material portion 28I decreases with the vertical distance downward from the horizontal plane including the top surface of the first conductive top cap material portion 28I.

[0114] Reference Fig.18 , the third flow chart shows general processing steps for manufacturing the semiconductor device of the present disclosure.

[0115] Refer to step 1810 and Figures 1 to 6C A stack may be formed on the substrate 8, wherein the stack includes a gate 15, a gate dielectric layer 10, and an active layer 20 including a semiconductor metal oxide material.

[0116] Refer to step 1820 and 7A to 9C , FIG. 11A to FIG. 11C and FIG. 13A to FIG. 13C , a composition-modulated cap layer 28 may be formed, wherein the composition-modulated cap layer 28 is on the active layer 20 and includes a first conductive cap material portion (28M, 28I), a second conductive cap material portion (28M, 28I) and a dielectric cap material portion 28D.

[0117] Refer to step 1830 and FIG. 10A to FIG. 10C , FIG. 12A to FIG. 12C , FIG. 14A to FIG. 14C and Fig.15 , a source structure 52 may be formed in contact with the top surface of the first conductive cap material portion ( 28M, 28I).

[0118] Refer to step 1840 and FIG. 10A to FIG. 10C , FIG. 12A to FIG. 12C , FIG. 14A to FIG. 14C and Fig.15 , a drain structure 56 can be formed in contact with the top surface of the second conductive cap material portion (28M, 28I). Each sidewall of the source structure 52 and each sidewall of the drain structure 56 include a corresponding bottom perimeter, and the corresponding bottom perimeter is spaced apart from the top perimeter of the corresponding conductive cap material portion (28M, 28I) by a uniform offset distance uod.

[0119] In one embodiment, the method includes: forming an in-process cap layer 26 including a dielectric metal oxide material on an active layer 20; and converting a plurality of portions of the in-process cap layer 26 into a first conductive cap material portion (28M, 28I) and a second conductive cap material portion (28M, 28I), wherein the dielectric cap material portion 28D includes a remaining portion of the dielectric metal oxide material. In one embodiment, the active layer 20 includes a semiconductor metal oxide material having a first oxide formation enthalpy; the dielectric cap material portion 28D includes a dielectric metal oxide material having a second oxide formation enthalpy higher than the first oxide formation enthalpy; and the dielectric cap material portion provides an interface trap density of less than 5×1011 / (square centimeter×electron volt) at an interface with an overlying insulating material.

[0120] With reference to all the drawings and according to various aspects of the present disclosure, a semiconductor structure including a field effect transistor is provided. The field effect transistor includes: a gate 15 located on a substrate 8; a gate dielectric layer 10 located on the gate 15; an active layer 20 located on the gate dielectric layer 10; a composition-modulated cap layer 28 located on the active layer 20 and including a first conductive cap material portion (28M, 28I), a second conductive cap material portion (28M, 28I) and a dielectric cap material portion 28D; a dielectric material layer 40 located on the composition-modulated cap layer 28; a source structure 52 extending vertically through the dielectric material layer 40 and contacting the top surface of the first conductive cap material portion (28M, 28I); and a drain structure 56 extending vertically through the dielectric material layer 40 and contacting the top surface of the second conductive cap material portion (28M, 28I).

[0121] In one embodiment, the dielectric cap material portion 28D includes a dielectric metal oxide material, which is an oxide of at least one metal; and the first conductive cap material portion (28M, 28I) and the second conductive cap material portion (28M, 28I) include the at least one metal. In one embodiment, the first surface density of the at least one metal obtained by integrating the volume density of the at least one metal along the vertical direction within the first conductive cap material portion (28M, 28I) is in the range of 30% to 100% (e.g., 50% to 90% and / or 60% to 80%) of the second surface density of the at least one metal obtained by integrating the volume density of the at least one metal along the vertical direction within the dielectric cap material portion 28D. In one embodiment, the at least one metal includes at least two metals; and each atomic ratio between the at least two metals within the dielectric cap material portion 28D is equal to the corresponding atomic ratio between the at least two metals within the first conductive cap material portion (28M, 28I). In one embodiment, the first conductive cap material portion 28M and the second conductive cap material portion 28M are metal portions without oxygen atoms. In one embodiment, the first conductive cap material portion 28M and the second conductive cap material portion 28M are composed of the at least one metal.

[0122] In one embodiment, the first conductive cap material portion 28I and the second conductive cap material portion 28I are non-stoichiometric metal oxide portions. In one embodiment, the first conductive cap material portion 28I and the second conductive cap material portion 28I include at least one additional metal different from the at least one metal. In one embodiment, the surface density of the at least one metal obtained by integrating the volume density of the at least one metal along the vertical direction within the first conductive cap material portion 28I is less than the total surface density of the at least one additional metal obtained by integrating the volume density of the at least one additional metal along the vertical direction within the first conductive cap material portion 28I.

[0123] In one embodiment, the active layer 20 comprises a semiconductor metal oxide material having a first oxide formation enthalpy; and the dielectric cap material portion 28D comprises a dielectric metal oxide material having a second oxide formation enthalpy higher than the first oxide formation enthalpy. In one embodiment, the dielectric cap material portion provides a dielectric conductivity of less than 5×10 11 / (square centimeter×electron volt) of interface trap density.

[0124] According to another aspect of the present disclosure, a semiconductor structure including a field effect transistor is provided. The field effect transistor includes: a gate 15 located on a substrate 8; a gate dielectric layer 10 located on the gate 15; an active layer 20 located on the gate dielectric layer 10; a composition-modulated cap layer 28 located on the active layer 20 and including a first conductive cap material portion (28M, 28I), a second conductive cap material portion (28M, 28I) and a dielectric cap material portion 28D; a source structure 52 in contact with a top surface of the first conductive cap material portion (28M, 28I); and a drain structure 56 in contact with a top surface of the second conductive cap material portion (28M, 28I), wherein each sidewall of the source structure 52 and each sidewall of the drain structure 56 include a corresponding bottom perimeter, and the corresponding bottom perimeter is spaced apart from the top perimeter of the corresponding conductive cap material portion (28M, 28I) by a uniform offset distance uod.

[0125] In one embodiment, the semiconductor structure includes: an insulating cap layer 30 on the composition-modulated cap layer 28; and a dielectric material layer 40 on the insulating cap layer 30 and laterally surrounding the source structure 52, the drain structure 56, the active layer 20 on the gate dielectric layer 10, and the composition-modulated cap layer 28. In one embodiment, the dielectric cap material portion 28D includes a dielectric metal oxide material, which is an oxide of at least one metal; and the first conductive cap material portion (28M, 28I) and the second conductive cap material portion (28M, 28I) include the at least one metal.

[0126] According to another aspect of the present disclosure, a semiconductor structure including a field effect transistor is provided. The field effect transistor includes: a gate 15 located on a substrate 8; a gate dielectric layer 10 located on the gate 15; an active layer 20 located on the gate dielectric layer 10 and including a semiconductor metal oxide material; a composition-modulated cap layer 28 located on the active layer 20 and including a first conductive cap material portion (28M, 28I), a second conductive cap material portion (28M, 28I) and a dielectric cap material portion 28D including a dielectric metal oxide material, wherein the dielectric metal oxide material is an oxide of at least one metal; a source structure 52 in contact with the top surface of the first conductive cap material portion (28M, 28I); and a drain structure 56 in contact with the second conductive cap material portion. The top surface of the dielectric top cover material portion (28M, 28I) is in contact with the top surface of the dielectric top cover material portion (28M, 28I), wherein: the first conductive top cover material portion (28M, 28I) and the second conductive top cover material portion (28M, 28I) include the at least one metal; and the first surface density of the at least one metal obtained by integrating the volume density of the at least one metal along the vertical direction in the first conductive top cover material portion (28M, 28I) is within the range of 30% to 100% (for example, 50% to 90% and / or 60% to 80%) of the second surface density of the at least one metal obtained by integrating the volume density of the at least one metal along the vertical direction in the dielectric top cover material portion 28D.

[0127] In one embodiment, the semiconductor structure includes a dielectric material layer 40, which is above the composition-modulated cap layer 28 and laterally surrounds the source structure 52 and the drain structure 56. In one embodiment, the at least one metal includes at least two metals; and each atomic ratio between the at least two metals within the dielectric cap material portion 28D is equal to the corresponding atomic ratio between the at least two metals within the first conductive cap material portion (28M, 28I).

[0128] In one embodiment, the first conductive cap material portion 28M and the second conductive cap material portion 28M are metal portions without oxygen atoms. In one embodiment, the first conductive cap material portion 28M and the second conductive cap material portion 28M are composed of the at least one metal. In one embodiment, the first conductive cap material portion 28I and the second conductive cap material portion 28I are non-stoichiometric metal oxide portions, and the non-stoichiometric metal oxide portions include at least one additional metal different from the at least one metal.

[0129] According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a stack on a substrate, the stack comprising a gate, a gate dielectric layer, an active layer comprising a semiconductor metal oxide material, and a process top cap layer comprising a dielectric metal oxide material; forming a dielectric material layer on the stack; forming a source cavity and a drain cavity through the dielectric material layer, so that multiple portions of the process top cap layer are exposed below the source cavity and the drain cavity; and converting the multiple portions of the process top cap layer into multiple conductive material portions, the multiple conductive material portions comprising a first conductive top cap material portion located below the source cavity and a second conductive top cap material portion located below the drain cavity.

[0130] In one embodiment, the method of forming a semiconductor structure further includes: forming a source structure in the source cavity; and forming a drain structure in the drain cavity. In one embodiment, the method of forming a semiconductor structure further includes performing a reduction process on the exposed multiple portions of the top cap layer in the process, thereby reducing the dielectric metal oxide material in the multiple portions of the top cap layer in the process to at least one metal without oxygen. In one embodiment, the reduction process includes a hydrogen plasma treatment process. In one embodiment, the method of forming a semiconductor structure further includes converting the exposed multiple portions of the top cap layer in the process into multiple metal-rich metal oxide material portions by introducing atoms of at least one metal into the exposed multiple portions of the top cap layer in the process. In one embodiment, atoms of at least one metal are introduced into the top cap layer in the process by performing an ion implantation process.

[0131] Various embodiments of the present disclosure may be used to provide a thin film transistor that reduces short channel effects in the backside channel region by reducing interface defect density while providing reduced contact resistance between the active layer 20 and each of the source structure 52 and the drain structure 56. The thin film transistor of the present disclosure may be integrated with various additional types of semiconductor devices in the same semiconductor structure, non-limiting examples of which include metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), sensor devices, various cache devices, and micro-electro-mechanical-system (MEMS) devices.

[0132] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Unless otherwise explicitly disclosed herein, each embodiment described using the term "comprises" also inherently discloses additional embodiments in which the term "comprises" is replaced with "consists essentially of" or the term "consists of". Whenever two or more elements are listed as alternatives in the same paragraph or in different paragraphs, a Markush group including the list of the two or more elements is also implicitly disclosed. Whenever the auxiliary verb "can" is used in the present disclosure to describe the formation of an element or the performance of a processing step, it is also explicitly expected that there are embodiments in which such an element or such a processing step is not performed, as long as the resulting device or apparatus can provide equivalent results. As such, whenever omitting a forming element or a processing step can provide the same or equivalent results, the auxiliary verb "may" applied to forming such an element or performing such a processing step should also be interpreted as "may" or "may, or may not", and the equivalent results include better results to some extent and worse results to some extent. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications thereto without departing from the spirit and scope of the present disclosure.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A semiconductor structure, characterized in that: A field effect transistor is included, wherein the field effect transistor includes: A gate, located on the substrate; A gate dielectric layer, located on the gate; An active layer, located on the gate dielectric layer; A composition-modulated top cover layer is located on the active layer, wherein the composition-modulated top cover layer comprises: a first conductive cap material portion; a second conductive cap material portion; and Dielectric top cover material section; a dielectric material layer on the composition-modulated cap layer; a source structure extending vertically through the dielectric material layer and contacting a top surface of the first conductive cap material portion; and A drain structure vertically extends through the dielectric material layer and contacts a top surface of the second conductive cap material portion.

2. The semiconductor structure according to claim 1, wherein: The dielectric cap material portion comprises a dielectric metal oxide material, the dielectric metal oxide material being an oxide of at least one metal; and The first conductive cap material portion and the second conductive cap material portion include the at least one metal.

3. The semiconductor structure according to claim 2, characterized in that: The first surface density of the at least one metal is in the range of 30% to 100% of the second surface density of the at least one metal, the first surface density of the at least one metal is obtained by integrating the volume density of the at least one metal along the vertical direction in the first conductive top cover material portion, and the second surface density of the at least one metal is obtained by integrating the volume density of the at least one metal along the vertical direction in the dielectric top cover material portion.

4. The semiconductor structure according to claim 2, wherein: The at least one metal comprises at least two metals; and Each atomic ratio between the at least two metals within the dielectric cap material portion is equal to a corresponding atomic ratio between the at least two metals within the first conductive cap material portion.

5. The semiconductor structure according to claim 2, characterized in that: The first conductive cap material portion and the second conductive cap material portion are metal portions without oxygen atoms.

6. The semiconductor structure according to claim 2, characterized in that: The first conductive cap material portion and the second conductive cap material portion include at least one additional metal different from the at least one metal.

7. The semiconductor structure according to claim 6, characterized in that: The surface density of the at least one metal is less than the total surface density of the at least one additional metal, and the surface density of the at least one metal is obtained by integrating the volume density of the at least one metal along the vertical direction within the first conductive top cover material portion, and the total surface density of the at least one additional metal is obtained by integrating the volume density of the at least one additional metal along the vertical direction within the first conductive top cover material portion.

8. A semiconductor structure, characterized in that: A field effect transistor is included, wherein the field effect transistor includes: a gate, located on the substrate; A gate dielectric layer, located on the gate; An active layer, located on the gate dielectric layer; A composition-modulated top cover layer is located on the active layer, wherein the composition-modulated top cover layer comprises: a first conductive cap material portion; a second conductive cap material portion; and Dielectric top cover material section; a source structure in contact with a top surface of the first conductive cap material portion; and a drain structure in contact with a top surface of the second conductive cap material portion, Each sidewall of the source structure and each sidewall of the drain structure includes a respective bottom perimeter that is spaced apart from a top perimeter of a respective conductive cap material portion by a uniform offset distance.

9. The semiconductor structure according to claim 8, characterized in that: Also includes: an insulating cap layer on the composition-modulated cap layer; and A dielectric material layer is disposed on the insulating cap layer and laterally surrounds the source structure, the drain structure, the active layer on the gate dielectric layer, and the composition-modulated cap layer.

10. The semiconductor structure according to claim 8, characterized in that: The dielectric cap material portion comprises a dielectric metal oxide material, the dielectric metal oxide material being an oxide of at least one metal; and The first conductive cap material portion and the second conductive cap material portion include the at least one metal.

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