Substrate for WBGA packaging and packaging structure
By setting a drain hole at the corner of the WBGA package substrate and setting a drain groove in the protective layer, the problem of chip failure caused by voltage overload during the packaging process is solved, and the substrate is high reliability.
Patent Information
- Application Number
- CN202421292779.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-06
- Publication Date
- 2025-02-25
- Estimated Expiration
- 2034-06-06
AI Technical Summary
During WBGA packaging, the substrate is prone to voltage overload (EOS), resulting in chip failure.
Design a substrate for WBGA packaging, by setting multiple drain holes at the corners of the substrate and setting multiple drain grooves extending along the thickness direction of the substrate in the protective layer, voltage overload grounding design, absorption and transfer Voltage overload.
Effectively prevent the chip from failing due to voltage overload during packaging, improving the reliability of the substrate.
Smart Images
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Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a substrate for WBGA packaging and a packaging structure. Background Art
[0002] In the integrated circuit manufacturing process, the window ball grid array (WBGA) packaging products are growing day by day.
[0003] In the related art, the substrate used for WBGA packaging usually has a slot window that penetrates the substrate, the chip is set on the slot, and the metal wires led from the chip pass through the slot to connect with the metal fingers on the substrate. However, during the packaging process, the substrate is prone to electrical over stress (EOS), causing chip failure. Utility Model Content
[0004] The present disclosure provides a substrate and a packaging structure for WBGA packaging, which at least to a certain extent overcome the problem in the related art that EOS occurs during the packaging process of the substrate for WBGA packaging, resulting in chip failure.
[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.
[0006] According to one aspect of the present disclosure, there is provided a substrate for WBGA packaging, comprising:
[0007] a substrate having opposing first and second surfaces;
[0008] A first conductive layer is disposed on the first surface of the substrate;
[0009] A first protective layer, disposed on the first conductive layer;
[0010] A second conductive layer is disposed below the second surface of the substrate;
[0011] A second protective layer, disposed below the second conductive layer;
[0012] A plurality of discharge holes are arranged at the corners of the substrate, each of the discharge holes is connected to the first conductive layer and the second conductive layer, and each of the discharge holes is provided with a metal material;
[0013] A plurality of discharge grooves are arranged in the first protective layer and / or the second protective layer, each of the discharge grooves extends along the thickness direction of the substrate and exposes a portion of the first conductive layer and / or a portion of the second conductive layer.
[0014] In one embodiment of the present disclosure, the first protective layer of the substrate includes a plurality of chip placement areas; and
[0015] The substrate further includes an auxiliary area disposed on the first protection layer and / or below the second protection layer at the periphery of the plurality of chip placement areas, and the plurality of discharge grooves are disposed in the auxiliary area.
[0016] In one embodiment of the present disclosure, the auxiliary area includes a first pair of sub-auxiliary areas, the first pair of sub-auxiliary areas are relatively distributed on the long sides of the substrate, and the multiple discharge grooves are arranged in at least one sub-auxiliary area of the first pair of sub-auxiliary areas.
[0017] In one embodiment of the present disclosure, the plurality of discharge grooves are arranged along the long sides of the substrate.
[0018] In one embodiment of the present disclosure, the auxiliary area further includes a second pair of sub-auxiliary areas, the second pair of sub-auxiliary areas are relatively distributed on the wide sides of the substrate, and the multiple discharge grooves are arranged in at least one sub-auxiliary area of the second pair of sub-auxiliary areas.
[0019] In one embodiment of the present disclosure, at least one discharge hole is disposed at each corner of the substrate.
[0020] In one embodiment of the present disclosure, a slot is provided on the substrate of each chip placement area, and the slot runs through two lateral surfaces of the substrate;
[0021] Wherein, the aperture of the discharge hole is the same as the aperture of the slot hole.
[0022] In one embodiment of the present disclosure, the discharge groove penetrates the side wall of the corresponding protective layer.
[0023] According to another aspect of the present disclosure, a packaging structure is further provided, including the above-mentioned substrate for WBGA packaging.
[0024] In one embodiment of the present disclosure, the first protective layer of the substrate includes a plurality of chip placement areas, each of the chip placement areas is provided with a slot hole on the substrate, and the slot hole penetrates two lateral surfaces of the substrate;
[0025] The packaging structure also includes a plurality of chips, which are mounted in the plurality of chip placement areas respectively, and each of the chips covers a slot in a corresponding chip placement area.
[0026] In an embodiment of the present disclosure, a substrate for WBGA packaging includes a substrate having a first surface and a second surface relative to each other; a first conductive layer, arranged on the first surface of the substrate; a first protective layer, arranged on the first conductive layer; a second conductive layer, arranged below the second surface of the substrate; a second protective layer, arranged below the second conductive layer; a plurality of discharge holes, arranged at corners of the substrate, each discharge hole connecting the first conductive layer and the second conductive layer, and each discharge hole having a metal material therein; a plurality of discharge grooves, arranged in the first protective layer and / or the second protective layer, each discharge groove extending along the thickness direction of the substrate and exposing a portion of the first conductive layer and / or a portion of the second conductive layer. By arranging the discharge holes and the discharge grooves, a voltage overload grounding design of the WBGA packaging substrate is realized, voltage overload is effectively absorbed and transferred, and the reliability of the substrate is improved.
[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0029] Figure 1 A partial cross-sectional view of a substrate for WBGA packaging provided by an embodiment of the present disclosure is shown.
[0030] Figure 2 A schematic structural diagram of a substrate for WBGA packaging provided by an embodiment of the present disclosure is shown.
[0031] Figure 3 Show Figure 2 Enlarged view of point A in the middle.
[0032] Figure 4 A schematic structural diagram of a substrate for WBGA packaging implementing the EOS principle provided by an embodiment of the present disclosure is shown.
[0033] Figure 5 A partial cross-sectional view showing a substrate for WBGA packaging according to an embodiment of the present disclosure that implements the EOS principle.
[0034] The reference numerals are described as follows:
[0035] 100, substrate; 110, base material; 111, discharge hole; 120, first conductive layer; 130, first protective layer; 131, 131', discharge groove; 140, second conductive layer; 150, second protective layer; 160, chip placement area; 161, slot hole; 162, pad. DETAILED DESCRIPTION
[0036] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.
[0037] The terms "first" and "second" in this document are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly stated that it is a limitation.
[0038] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0039] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.
[0040] As used in the present disclosure, the term "substrate" refers to a material on which subsequent materials are added or otherwise arranged. The substrate may also be referred to as a core layer. The material arranged on the substrate (e.g., the first surface and the second surface of the substrate) may be patterned or may remain unpatterned. In addition, the substrate may include a glass fiber double-sided board, a ceramic board, and a polyimide board, etc. The material type of the substrate may be determined according to the application scenario.
[0041] As used in the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness, and a layer may extend over the entirety of a structure below or above, or may have a range that is less than the range of the structure below or above. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. A layer may extend horizontally, vertically and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers thereon, above and / or below. A layer may include multiple layers. For example, a stacked layer may include one or more conductors and contact layers (wherein contacts, interconnects and / or vias are formed) and one or more dielectric layers.
[0042] As used in this disclosure, a "substrate for WBGA packaging" has a plurality of material layers oriented vertically on a substrate oriented horizontally, so that the material layers extend in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" means perpendicular to the lateral surface of the substrate.
[0043] As used herein, the terms “horizontal / horizontally / lateral / laterally” represent a lateral surface parallel to a substrate, such as a first surface or a second surface having relative positions of the substrate, i.e., a surface defined by a plane in which a first direction D1 and a second direction D2 are located in the accompanying drawings; and the terms “vertical” or “vertically” represent a lateral surface perpendicular to the substrate, such as a direction represented by a third direction D3 in the accompanying drawings.
[0044] A chip, also known as an integrated circuit chip, integrates electronic components such as transistors, resistors, capacitors, etc. on a thin sheet-like substrate and is a basic component of electronic equipment.
[0045] In the related art, the substrate used for WBGA packaging is not designed for EOS, and the substrate may be exposed to EOS events during the chip packaging process. When the chip is subjected to EOS exceeding the preset current and / or voltage upper limit, the chip may be damaged.
[0046] In one scenario, such as an electrostatic discharge event, which can be caused by a sudden discharge of charge from an object or person to the chip, or by a voltage / current spike in the power supply that powers the chip, an EOS event may occur regardless of whether the chip is powered on or not.
[0047] In order to at least prevent the chip from being exposed to EOS events during the packaging process, designing an EOS-proof substrate for WBGA packaging has become a key technology to improve the chip packaging yield.
[0048] In order to at least solve the technical problem of chip failure caused by EOS during the packaging process, the present disclosure provides a substrate for WBGA packaging, including: a substrate having a first surface and a second surface relative to each other; a first conductive layer, arranged on the first surface of the substrate; a first protective layer, arranged on the first conductive layer; a second conductive layer, arranged below the second surface of the substrate; a second protective layer, arranged below the second conductive layer; a plurality of discharge holes, arranged at the corners of the substrate, each discharge hole connecting the first conductive layer and the second conductive layer, and each discharge hole having a metal material therein; a plurality of discharge grooves, arranged in the first protective layer and / or the second protective layer, each discharge groove extending along the thickness direction of the substrate and exposing part of the first conductive layer and / or part of the second conductive layer. The present disclosure implements a voltage overload grounding design for a WBGA packaging substrate by arranging discharge holes and discharge grooves, effectively absorbing and transferring voltage overloads, and improving the reliability of the substrate. This is specifically described through the following embodiments:
[0049] Figure 1 A partial cross-sectional view of a substrate for WBGA packaging provided by an embodiment of the present disclosure is shown. Figure 2 A schematic structural diagram of a substrate for WBGA packaging provided by an embodiment of the present disclosure is shown. Figure 3 Show Figure 2 Enlarged view of point A in the middle.
[0050] Combination Figure 1 to Figure 3 The substrate 100 for WBGA packaging in the embodiment of the present disclosure includes a base material 110 , a first conductive layer 120 , a first protective layer 130 , a second conductive layer 140 and a second protective layer 150 .
[0051] In the present disclosure, the first direction D1 is the long side direction of the substrate 110 , the second direction D2 is the short side direction of the substrate 110 , and the third direction D3 is the thickness direction of the substrate 110 , wherein the first direction, the second direction and the third direction are perpendicular to each other.
[0052] The substrate 110 is the main part of the substrate 100 and can be used as a platform to support the chip. The substrate 110 can be a rectangular block. The substrate 110 has a first surface and a second surface opposite to each other, and the first surface and the second surface are surfaces arranged along the third direction D3. The type of the substrate 110 can include any one of a glass fiber double-sided board, a ceramic board, and a polyimide board, which is not specifically limited in the present disclosure.
[0053] The first conductive layer 120 is disposed on the first surface of the substrate 110; the second conductive layer 140 is disposed under the second surface of the substrate 110. The materials of the first conductive layer 120 and the second conductive layer 140 may include one or more combinations of copper, silver, and gold.
[0054] It should be noted that the first conductive layer 120 and the second conductive layer 140 may be patterned circuit layers formed by etching the conductive layers according to actual needs.
[0055] The first protective layer 130 is disposed on the first conductive layer 120, a portion of the first protective layer 130 covers the first conductive layer 120, and another portion of the first protective layer 130 surrounds the side wall of the first conductive layer 120 and covers the periphery of the first surface of the substrate 110; the second protective layer 150 is disposed under the second conductive layer 140, a portion of the second protective layer 150 covers the second protective layer 150, and another portion of the second protective layer 150 surrounds the side wall of the second conductive layer 140 and covers the periphery of the second surface of the substrate 110.
[0056] The first protective layer 130 and the second protective layer 150 can be patterned protective layers formed by etching according to actual needs, so as to expose a portion of the circuit layer, so that the circuit layer and the connection points of the chip can be connected through metal wires during the chip packaging process.
[0057] The first protective layer 130 and the second protective layer 150 can be made of ink or insulating materials such as epoxy resin, polyimide film and polyurethane. On the one hand, they can isolate circuits and electronic components at different levels to avoid circuit breaks and failures. On the other hand, they can prevent thermal stress and mechanical stress in the circuit lines from causing damage and cracks to the packaging substrate 100, thereby improving the yield of the chip.
[0058] The substrate 100 further includes a plurality of discharge holes 111 . The plurality of discharge holes 111 are disposed at corners of the substrate 110 , each discharge hole 111 connects the first conductive layer 120 and the second conductive layer 140 , and each discharge hole 111 is provided with a metal material.
[0059] The discharge hole 111 may be a circular hole, an elliptical hole, or a through hole of other shapes, such as Figure 1 The two cross-sections shown in the figure are cylindrical through holes of isosceles trapezoidal shape. It should be noted that the present disclosure does not specifically limit the shape of the discharge hole 111.
[0060] In a feasible embodiment, the substrate 100 includes at least two discharge holes 111 , wherein at least one discharge hole 111 is used to transmit input EOS, and at least one of the remaining discharge holes 111 is used to transmit derived EOS, so as to form a path for conducting EOS inside the substrate 100 .
[0061] The metal material may include one or more combinations of copper, gold, silver, etc., which is not specifically limited in the present disclosure.
[0062] The substrate 100 further includes a plurality of discharge grooves 131 disposed in the first protective layer 130 and / or the second protective layer 150 , each of which extends along the thickness direction of the substrate 100 and exposes a portion of the first conductive layer 120 and / or a portion of the second conductive layer 140 .
[0063] It should be noted that the plurality of discharge grooves 131 may be provided only on the first protective layer 130 ; or may be provided only on the second protective layer 150 .
[0064] Multiple discharge grooves 131 can also be set in the first protective layer 130 and the second protective layer 150 at the same time, and each protective layer includes at least two discharge grooves 131. When WBGA is packaged, the substrate 100 needs to be turned over: that is, when the bare chip is bonded to Diebond, the device pressing tool tool contacts the first protective layer 130 (or the front of the substrate Strip); after the bare chip is bonded to Diebond, the wire bond is performed, and the substrate Strip needs to be turned over. At this time, the device pressing tool tool contacts the back of the substrate Strip. By setting the discharge grooves 131 in the two protective layers, EOS can be discharged to the greatest extent, and the impact of EOS can be minimized.
[0065] In one embodiment, the discharge groove 131 penetrates the side wall of the corresponding protective layer. That is, when the discharge groove 131 is disposed in the first protective layer 130 , the discharge groove 131 penetrates the side wall of the first protective layer 130 ; when the discharge groove 131 is disposed in the second protective layer 150 , the discharge groove 131 penetrates the side wall of the second protective layer 150 .
[0066] The cross section of the discharge groove 131 may be a rectangle, for example, the cross section of the discharge groove 131 may be a rectangle of 3 mm×2 mm; the cross section of the discharge groove 131 may also be other shapes, which is not specifically limited in the present disclosure.
[0067] The substrate 100 may include at least two discharge grooves 131 , at least one of which may receive the input EOS, and at least one of the remaining discharge grooves 131 may be connected to a grounding element to form a conduction path of the EOS.
[0068] In the embodiment of the present disclosure, the substrate 100 for WBGA packaging includes: a substrate 110 having a first surface and a second surface opposite to each other; a first conductive layer 120 disposed on the first surface of the substrate 110; a first protective layer 130 disposed on the first conductive layer 120; a second conductive layer 140 disposed under the second surface of the substrate 110; a second protective layer 150 disposed under the second conductive layer 140; a plurality of discharge holes 111 disposed at the corners of the substrate 110, each discharge hole 111 connecting the first conductive layer 120 and the second conductive layer 140; The conductive layer 120 and the second conductive layer 140, each discharge hole 111 is provided with a metal material; a plurality of discharge grooves 131 are provided in the first protective layer 130 and / or the second protective layer 150, each discharge groove 131 extends along the thickness direction of the substrate 100 and exposes a portion of the first conductive layer 120 and / or a portion of the second conductive layer 140. By providing the discharge holes 111 and the discharge grooves 131, a voltage overload grounding design of the WBGA package substrate 100 is realized, which effectively absorbs and transfers voltage overload, thereby improving the reliability of the substrate 100.
[0069] In some embodiments, the first protective layer 130 of the substrate 100 includes multiple chip placement areas 160; the first protective layer 130 of the substrate 100 and / or below the second protective layer 150 also includes an auxiliary area arranged on the periphery of the multiple chip placement areas 160, and multiple discharge grooves 131 are arranged in the auxiliary area.
[0070] The plurality of chip placement areas 160 may be arranged in M rows×N columns, where M, N ≥ 1, for example Figure 2 The middle chip placement area 160 is 5 rows×18 columns. It should be noted that the surface above the first protection layer 130 of the substrate 100 is the surface of the first protection layer 130 away from the first conductive layer 120 , and the surface below the second protection layer 150 of the substrate 100 is the surface of the second protection layer 150 away from the second conductive layer 140 .
[0071] The periphery of the plurality of chip placement areas 160 refers to the periphery of the M-row×N-column chip placement areas 160 as a whole, and the auxiliary area is arranged around the plurality of chip placement areas 160 .
[0072] The auxiliary area may be provided with alignment marks and other basic information, among which the alignment marks may be cross-shaped patterns, which may be used to align adjacent film layers; other basic information may include packaging project name, packaging type information, date, etc., which are not limited in the present disclosure.
[0073] The contour of the auxiliary region may be consistent with the outer contour of the plurality of chip placement regions 160 .
[0074] In the embodiment of the present disclosure, by setting a plurality of discharge grooves 131 in the auxiliary area, the design of a single unit (such as each chip placement area 160) does not need to be changed, and only the first conductive layer 120 needs to be appropriately exposed and holes need to be punched to fill the metal material on the overall substrate 100, which does not increase any cost and improves the reliability of the packaging substrate 100.
[0075] In some embodiments, Figure 2 As shown, the auxiliary area includes a first pair of sub-auxiliary areas, which are relatively distributed on the long sides of the substrate 100, and a plurality of discharge grooves 131 are disposed in at least one of the first pair of sub-auxiliary areas.
[0076] The first pair of auxiliary areas can be found in Figure 2 The second pair of sub-auxiliary areas may be rectangular sub-auxiliary areas distributed along the first direction D1 and located above and below the plurality of chip placement areas 160 , and the second pair of sub-auxiliary areas may be rectangular sub-auxiliary areas distributed along the first direction D1 and located to the left and right of the plurality of chip placement areas 160 .
[0077] Exemplarily, the plurality of discharge grooves 131 may be disposed in a sub-auxiliary area above the plurality of chip placement areas 160 , or in a sub-auxiliary area below the plurality of chip placement areas 160 , or may be disposed in sub-auxiliary areas both above and below the plurality of chip placement areas 160 .
[0078] In a feasible implementation, a plurality of discharge grooves 131 are arranged along the long side of the substrate 100. The plurality of discharge grooves 131 may be arranged at a fixed pitch, or may be arranged at a suitable position according to actual needs, which is not specifically limited in the present disclosure.
[0079] For example, in Figure 2 In the figure, a total of five discharge grooves 131 are arranged in the sub-auxiliary area below the multiple chip placement areas 160. The five discharge grooves 131 are arranged in sequence along the long side of the substrate 100. The discharge grooves 131 are rectangular grooves. The long sides of the discharge grooves 131 are set corresponding to the long sides of the substrate 100, and the short sides of the discharge grooves 131 are set corresponding to the short sides of the substrate 100.
[0080] In the embodiment of the present disclosure, by providing a plurality of discharge grooves 131 in at least one of the first pair of sub-auxiliary areas, the EOS protection performance in the chip packaging process is further improved, thereby improving the chip packaging yield.
[0081] In some embodiments, the second pair of sub-auxiliary regions are relatively distributed on the wide side of the substrate 100 , and a plurality of discharge grooves 131 are disposed in at least one of the second pair of sub-auxiliary regions.
[0082] In a feasible implementation, a plurality of discharge grooves 131 are arranged along the short side of the substrate 100 . The plurality of discharge grooves 131 may be arranged at a fixed interval, or may be disposed at a suitable position according to actual needs, which is not specifically limited in the present disclosure.
[0083] For example, three rectangular discharge grooves 131 are arranged in the sub-auxiliary area on the right side of the multiple chip placement area 160, and the three discharge grooves 131 are arranged in sequence along the short side of the substrate 100, and the long side of the discharge groove 131 is set corresponding to the short side of the substrate 100, and the short side of the discharge groove 131 is set corresponding to the long side of the substrate 100.
[0084] It should be noted that the above-mentioned location and arrangement of the plurality of discharge grooves 131 are only for illustration, and the location of the plurality of discharge grooves 131 in the embodiment of the present disclosure is not limited to the above-mentioned method. The above-mentioned solution of setting in the first pair of sub-auxiliary areas or the solution of setting in the second pair of sub-auxiliary areas can be implemented separately or in combination, and the embodiment of the present disclosure does not limit this.
[0085] In the embodiment of the present disclosure, by providing a plurality of discharge grooves 131 in at least one of the second pair of sub-auxiliary areas, the EOS protection performance in the chip packaging process is further improved, thereby improving the chip packaging yield.
[0086] In some embodiments, at least one discharge hole 111 is disposed at each corner of the substrate 110. Figure 2 and Figure 3 In the embodiment, eight discharge holes 111 are arranged at the corners of the substrate 100 , two discharge holes 111 are arranged at each corner, and the discharge holes 111 are filled with metal material.
[0087] Continue to refer Figure 3 A slot 161 is provided on the substrate 100 of each chip placement area 160, and the slot 161 passes through two lateral surfaces of the substrate 100. A plurality of pads 162 are provided on both sides of the slot 161 along the second direction; wherein the aperture of the discharge hole 111 is the same as the aperture of the slot 161.
[0088] The slot hole 161 is a strip-shaped hole. The size of the slot hole 161 and the distance between the slot hole 161 and the chip placement area 160 can be determined according to actual needs, and the present disclosure does not make specific limitations.
[0089] It should be noted that the diameter of the discharge hole 111 is consistent with the short side size of the strip hole.
[0090] The discharge hole 111 and the slot 161 can be obtained by etching the substrate 110 through a single etching process. The metal material can be the same as the material used for the conductive layer, or can be different.
[0091] In the present disclosure, the filling process of the metal material and the preparation of the first conductive layer 120 and the second conductive layer 140 are performed simultaneously.
[0092] In order to illustrate the EOS protection function of the WBGA package substrate 100 disclosed in the present invention, the following is combined with Figure 4 and Figure 5 Provide detailed explanation.
[0093] like Figure 4 As shown, the substrate 100 is placed on the equipment track, and the pressure relief groove 131 is pressed by the tooling of the workstation equipment such as die attatch and wire bonding, so that the substrate 100 can be fixed while the relief circuit is turned on. Among them, the EOS generated by the abnormal equipment acts on the substrate 100 Strip and is absorbed by the relief groove 131.
[0094] like Figure 5 As shown, the discharge groove 131 absorbs EOS generated abnormally by the equipment and releases it through the first conductive layer 120, a discharge hole 111, the second conductive layer 140, another discharge hole 111, the first conductive layer 120, and the pressing block tool at the discharge groove 131' in sequence.
[0095] The embodiment of the present disclosure also provides a packaging structure, which includes the substrate 100 for WBGA packaging in the above embodiment. Thus, in combination with the above substrate 100 for WBGA packaging, by providing the discharge hole 111 and the discharge groove 131, the voltage overload grounding design of the WBGA packaging substrate 100 is realized, the voltage overload is effectively absorbed and transferred, and the reliability of the substrate 100 is improved.
[0096] In one embodiment, the first protection layer 130 of the substrate 100 includes a plurality of chip placement areas 160 ; and
[0097] The first protection layer 130 and / or the second protection layer 150 of the substrate 100 further includes an auxiliary area disposed at the periphery of the plurality of chip placement areas 160 , and the plurality of discharge grooves 131 are disposed in the auxiliary area.
[0098] In one embodiment, the auxiliary region includes a first pair of sub-auxiliary regions, the first pair of sub-auxiliary regions are oppositely distributed on the long sides of the substrate 100, and the plurality of discharge grooves 131 are disposed in at least one of the first pair of sub-auxiliary regions.
[0099] In one embodiment, the plurality of discharge grooves 131 are arranged along the long side of the substrate 100 .
[0100] In one embodiment, the auxiliary area further includes a second pair of sub-auxiliary areas, which are relatively distributed on the wide sides of the substrate 100 , and a plurality of discharge grooves 131 are disposed in at least one of the second pair of sub-auxiliary areas.
[0101] In one embodiment, the discharge groove 131 penetrates through the side wall of the corresponding protection layer.
[0102] In one embodiment, at least one discharge hole 111 is disposed at each corner of the substrate 110 .
[0103] In one embodiment, a slot hole 161 is provided on the substrate 100 of each chip placement area 160 , and the slot hole 161 penetrates two lateral surfaces of the substrate 100 ;
[0104] The diameter of the discharge hole 111 is the same as the diameter of the through hole 162 .
[0105] In some embodiments, the first protection layer 130 of the substrate 100 includes a plurality of chip placement areas 160 , and each chip placement area 160 has a slot 161 on the substrate 100 , and the slot 161 penetrates two lateral surfaces of the substrate 100 ;
[0106] The packaging structure further includes a plurality of chips mounted in a plurality of chip placement areas 160 , respectively, and each chip covers a slot 161 in a corresponding chip placement area 160 .
[0107] When packaging the chip, the first protective layer 130 of the substrate 100 is fixed upward on the equipment track, the chip is attached to the chip placement area 160 of the substrate 100 upside down, and the chip bumps are placed in the slots 161. At this time, the device pressing tool tool can be contacted with the discharge groove 131 of the first protective layer 130 to perform EOS discharge. When all chips are fixed in the chip placement area 160, the substrate is turned over and fixed on the equipment track. At this time, the chip faces downward, and the second protective layer 150 of the substrate 100 faces upward. The device pressing tool tool is contacted with the discharge groove 131 of the second protective layer 150 to perform EOS discharge. The wire bonding process is performed to form metal wires, which are led out from the bumps of the chip and pass through the slots 161 to connect with the metal fingers (not shown in the figure) exposed on the second surface of the substrate 100. A first plastic package is formed on the first protective layer 130 of the substrate 100, and the first plastic package wraps the chip; a second plastic package is formed under the second protective layer 150 of the substrate 100, and the second plastic package wraps the metal wire cut filling slot 161, the ball planting area in the second protective layer 150 of the substrate 100 is exposed from the second plastic package, and a solder ball is set on the ball planting area, and the solder ball can be specifically set on the solder pad exposed on the second surface.
[0108] In the application embodiments, the terms "first", "second", and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance; the term "plurality" refers to two or more, unless otherwise expressly defined. The terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; "connected" can be a direct connection or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the application embodiments can be understood according to the specific circumstances.
[0109] In the description of the application embodiments, it should be understood that the directions or positional relationships indicated by the terms "up", "down", "left", "right", "front", "back", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the application embodiments and simplifying the description, rather than indicating or implying that the device or unit referred to must have a specific direction, be constructed and operated in a specific orientation, and therefore, should not be understood as a limitation on the application embodiments.
[0110] In the description of this specification, the description of the terms "one embodiment", "some embodiments", "specific embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the application embodiment. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0111] The above are only preferred embodiments of the application embodiments and are not intended to limit the application embodiments. For those skilled in the art, the application embodiments may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application embodiments shall be included in the protection scope of the application embodiments.
Claims
1. A substrate for WBGA packaging, characterized in that: include: a substrate having opposing first and second surfaces; A first conductive layer is disposed on the first surface of the substrate; A first protective layer, disposed on the first conductive layer; A second conductive layer is disposed below the second surface of the substrate; A second protective layer, disposed below the second conductive layer; A plurality of discharge holes are arranged at the corners of the substrate, each of the discharge holes is connected to the first conductive layer and the second conductive layer, and each of the discharge holes is provided with a metal material; A plurality of discharge grooves are arranged in the first protective layer and / or the second protective layer, each of the discharge grooves extends along the thickness direction of the substrate and exposes a portion of the first conductive layer and / or a portion of the second conductive layer.
2. The substrate for WBGA packaging according to claim 1, characterized in that: The first protective layer of the substrate includes a plurality of chip placement areas; and The substrate further includes an auxiliary area disposed on the first protection layer and / or below the second protection layer at the periphery of the plurality of chip placement areas, and the plurality of discharge grooves are disposed in the auxiliary area.
3. The substrate for WBGA packaging according to claim 2, characterized in that: The auxiliary area includes a first pair of sub-auxiliary areas, the first pair of sub-auxiliary areas are relatively distributed on the long sides of the substrate, and the plurality of discharge grooves are arranged in at least one sub-auxiliary area of the first pair of sub-auxiliary areas.
4. The substrate for WBGA packaging according to claim 3, characterized in that: The plurality of discharge grooves are arranged along the long sides of the substrate.
5. The substrate for WBGA packaging according to claim 2, characterized in that: The auxiliary area includes a second pair of sub-auxiliary areas, the second pair of sub-auxiliary areas are relatively distributed on the wide side of the substrate, and the plurality of discharge grooves are arranged in at least one sub-auxiliary area of the second pair of sub-auxiliary areas.
6. The substrate for WBGA packaging according to claim 2, characterized in that: At least one discharge hole is respectively arranged at each corner of the substrate.
7. The substrate for WBGA packaging according to claim 6, characterized in that: A slot is provided on the substrate of each chip placement area, and the slot runs through two lateral surfaces of the substrate; Wherein, the aperture of the discharge hole is the same as the aperture of the slot hole.
8. The substrate for WBGA packaging according to any one of claims 1 to 7, characterized in that: The discharge groove penetrates through the side wall of the corresponding protective layer.
9. A packaging structure, characterized in that: The invention comprises a substrate for WBGA packaging as described in any one of claims 1 to 8.
10. The packaging structure according to claim 9, characterized in that: The first protective layer of the substrate includes a plurality of chip placement areas, each of the chip placement areas is provided with a slot hole on the substrate, and the slot hole penetrates two lateral surfaces of the substrate; The packaging structure also includes a plurality of chips, which are mounted in the plurality of chip placement areas respectively, and each of the chips covers a slot in a corresponding chip placement area.