Analog-to-digital conversion circuit and analog-to-digital conversion system
By using programmable logic devices and low voltage differential signal ports in the analog-to-digital conversion circuit, the problems of poor flexibility and high cost of existing analog-to-digital conversion circuits are solved, and high flexibility and low cost analog-to-digital conversion effects are achieved.
Patent Information
- Application Number
- CN202421041523.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-13
- Publication Date
- 2025-02-25
- Estimated Expiration
- 2034-05-13
AI Technical Summary
Existing analog-to-digital conversion circuits need to be built with a variety of electronic components, which are less flexible and cost-effective.
An analog-to-digital conversion circuit is designed, including adjustment module, comparison module, sampling module and filter module. All modules are set in programmable logic devices and use low voltage differential signal ports to realize analog-to-digital conversion.
Through the design based on programmable logic devices, the flexibility of the analog-to-digital conversion circuit is improved, effectively saving board-level costs and shortening project development cycle.
Smart Images
Figure CN222531676U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of circuit signal processing, and more specifically, to an analog-to-digital conversion circuit and an analog-to-digital conversion system. Background Art
[0002] Real-world analog signals need to be converted into digital signals for easy processing and storage. In related technologies, analog signals can be converted into digital signals through analog-to-digital conversion circuits. However, analog-to-digital conversion circuits require the use of a variety of electronic components to build and implement them, which has poor flexibility and high cost. Utility Model Content
[0003] In view of the above problems, the utility model proposes an analog-to-digital conversion circuit and an analog-to-digital conversion system.
[0004] In a first aspect, an embodiment of the present application provides an analog-to-digital conversion circuit, which includes: an adjustment module, a comparison module, a sampling module and a filtering module; wherein the input end of the adjustment module is used to receive a signal to be tested, the feedback end of the adjustment module is used to receive a sampled feedback signal, and is used to generate a first input signal and a second input signal according to the signal to be tested and the feedback signal; wherein the signal to be tested is an analog signal; the first input end of the comparison module is used to receive a first input signal, and the second input end of the comparison module is used to receive a second input signal; the comparison module is used to generate a comparison signal according to the first input signal and the second input signal; the output end of the comparison module is used to output a comparison signal; the input end of the sampling module is connected to the output end of the comparison module, and the sampling module is used to generate a sampled feedback signal according to the comparison signal; the feedback end of the sampling module is connected to the feedback end of the adjustment module; the filtering module is connected to the output end of the sampling module, and the filtering module is used to filter the sampled feedback signal to generate a conversion signal; wherein the comparison module, the sampling module and the filtering module are arranged in a programmable logic device, and the first input end and the second input end are low voltage differential signal ports of the programmable logic device.
[0005] In the second aspect, an embodiment of the present application also provides an analog-to-digital conversion system, which includes: multiple analog-to-digital conversion circuits as described in the first aspect above, and the analog-to-digital conversion system also includes an observation module, the observation module is used to receive conversion signals of the multiple analog-to-digital conversion circuits, and the observation module is also used to determine a target signal among the multiple conversion signals based on the observation operation, and output the target signal.
[0006] The utility model provides a technical solution, the analog-to-digital conversion circuit includes an adjustment module, a comparison module, a sampling module and a filtering module; wherein the input end of the adjustment module is used to receive a signal to be tested, the feedback end of the adjustment module is used to receive a sampling feedback signal, and is used to generate a first input signal and a second input signal according to the signal to be tested and the feedback signal; wherein the signal to be tested is an analog signal; the first input end of the comparison module is used to receive a first input signal, and the second input end of the comparison module is used to receive a second input signal; the comparison module is used to generate a comparison signal according to the first input signal and the second input signal; the output end of the comparison module is used to output the comparison signal; the input end of the sampling module is connected to the output end of the comparison module, and the sampling module is used to generate a sampling feedback signal according to the comparison signal; the feedback end of the sampling module is connected to the feedback end of the adjustment module; the filtering module is connected to the output end of the sampling module, and the filtering module is used to filter the sampling feedback signal to generate a conversion signal; wherein the comparison module, the sampling module and the filtering module are arranged in a programmable logic device, and the first input end and the second input end are low voltage differential signal ports; thereby, the analog-to-digital conversion function is realized based on the programmable logic device, the flexibility is high, and the board-level cost is effectively saved, and the project development cycle is shortened. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, not all embodiments. Based on the embodiments of the present application, all other embodiments and drawings obtained by ordinary technicians in this field without creative work are within the scope of protection of the present utility model.
[0008] Figure 1 A structural schematic diagram of an analog-to-digital conversion circuit provided in an embodiment of the present application is shown.
[0009] Figure 2 A structural schematic diagram of an adjustment module provided in an embodiment of the present application is shown.
[0010] Figure 3 A structural schematic diagram of another adjustment module provided in an embodiment of the present application is shown.
[0011] Figure 4 A structural schematic diagram of another adjustment module provided in an embodiment of the present application is shown.
[0012] Figure 5 A structural schematic diagram of another adjustment module provided in an embodiment of the present application is shown.
[0013] Figure 6 A structural schematic diagram of another adjustment module provided in an embodiment of the present application is shown.
[0014] Figure 7 A structural schematic diagram of another adjustment module provided in an embodiment of the present application is shown.
[0015] Figure 8 A structural schematic diagram of another adjustment module provided in an embodiment of the present application is shown.
[0016] Fig. 9 A structural schematic diagram of another adjustment module provided in an embodiment of the present application is shown.
[0017] Fig.10 A structural schematic diagram of yet another adjustment module provided in an embodiment of the present application is shown.
[0018] Fig.11 A structural schematic diagram of yet another adjustment module provided in an embodiment of the present application is shown.
[0019] Fig.12 A structural schematic diagram of yet another adjustment module provided in an embodiment of the present application is shown.
[0020] Fig.13 A structural schematic diagram of yet another adjustment module provided in an embodiment of the present application is shown.
[0021] Fig.14 A structural schematic diagram of a filtering module provided in an embodiment of the present application is shown.
[0022] Fig.15 A structural schematic diagram of an analog-to-digital conversion system provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0023] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.
[0024] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.
[0025] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0026] Real-world analog signals (such as temperature, voltage, sound or images, etc.) need to be converted into digital signals for easy processing and storage. In related technologies, analog signals can be converted into digital signals through analog-to-digital conversion circuits. However, analog-to-digital conversion circuits need to be built and implemented using a variety of electronic components, which has poor flexibility and high cost.
[0027] In order to improve the above-mentioned problems, the inventors have proposed the analog-to-digital conversion circuit and the analog-to-digital conversion system provided in the present application, wherein the analog-to-digital conversion circuit includes an adjustment module, a comparison module, a sampling module and a filtering module; wherein the input end of the adjustment module is used to receive a signal to be tested, the feedback end of the adjustment module is used to receive a sampled feedback signal, and is used to generate a first input signal and a second input signal according to the signal to be tested and the feedback signal; wherein the signal to be tested is an analog signal; the first input end of the comparison module is used to receive a first input signal, and the second input end of the comparison module is used to receive a second input signal; the comparison module is used to generate a comparison signal according to the first input signal and the second input signal The output end of the comparison module is used to output a comparison signal; the input end of the sampling module is connected to the output end of the comparison module, and the sampling module is used to generate a sampling feedback signal according to the comparison signal; the feedback end of the sampling module is connected to the feedback end of the adjustment module; the filtering module is connected to the output end of the sampling module, and the filtering module is used to filter the sampling feedback signal to generate a conversion signal; wherein the comparison module, the sampling module and the filtering module are arranged in a programmable logic device, and the first input end and the second input end are low voltage differential signal ports; thereby, the analog-to-digital conversion function is realized based on the programmable logic device, which has high flexibility, effectively saves board-level costs, and shortens the project development cycle.
[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.
[0029] See also Figure 1The embodiment of the present application provides an analog-to-digital conversion circuit 100, which includes an adjustment module 110, a comparison module 120, a sampling module 130 and a filtering module 140. The comparison module 120 is connected to the adjustment module 110, the sampling module 130 is connected to the comparison module 120 and the adjustment module 110 respectively, and the filtering module 140 is connected to the sampling module 130. The adjustment module 110 is used to receive a signal to be tested VIN, which is an analog signal. After signal processing by the adjustment module 110, the comparison module 120, the sampling module 130 and the filtering module 140, the signal to be tested VIN is converted into a conversion signal swing_out, and the conversion signal swing_out is a digital signal, thereby realizing an analog-to-digital conversion function; wherein the comparison module 120, the sampling module 130 and the filtering module 140 are arranged in a programmable logic device, and the signal input of the comparison module 120 is realized by a low voltage differential signal port of the programmable logic device, thereby effectively saving board-level costs, shortening the project development cycle, and having high flexibility while realizing the analog-to-digital conversion function.
[0030] Specifically, the input end of the adjustment module 110 is used to receive the test signal VIN, the feedback end of the adjustment module 110 is used to receive the sampled feedback signal PWM_out, and is used to generate a first input signal and a second input signal according to the test signal VIN and the feedback signal PWM_out; wherein the test signal VIN is an analog signal.
[0031] The first input terminal of the comparison module 120 is used to receive a first input signal, and the second input terminal of the comparison module 120 is used to receive a second input signal; the comparison module 120 is used to generate a comparison signal according to the first input signal and the second input signal; and the output terminal of the comparison module 120 is used to output a comparison signal.
[0032] The input end of the sampling module 130 is connected to the output end of the comparison module 120, and the sampling module 130 is used to generate a sampling feedback signal PWM_out according to the comparison signal; the feedback end of the sampling module 120 is connected to the feedback end of the adjustment module 110;
[0033] The filter module 140 is connected to the output end of the sampling module 130 , and the filter module 130 is used for filtering the sampled feedback signal PWM_out to generate a conversion signal swing_out.
[0034] In the embodiments of the present application, the structure of the adjustment module 110 can select the required settings according to the use requirements, and different embodiments will be provided below for detailed explanation.
[0035] In some implementations, the adjustment module 110 is used to generate a first input signal according to the signal to be measured VIN; the adjustment module 110 is also used to generate a second input signal according to the feedback signal PWM_out.
[0036] Optionally, the signal to be tested VIN can be directly used as the first input signal, such as Figure 2 As shown, the adjustment module 110 transmits the signal to be tested VIN to the first input terminal of the comparison module 120 .
[0037] Optionally, the signal to be tested VIN may be processed by the adjustment module 110 to form a first input signal. Figure 3 As shown, the adjustment module 110 may include a protection network 111 to prevent the signal to be measured VIN from being disturbed.
[0038] In some embodiments, Figure 4 As shown, the adjustment module 110 further includes a first adjustment network 112 , and the first adjustment network 112 is used to generate a second input signal according to the feedback signal PWM_out.
[0039] Alternatively, if Figure 5 As shown, the first adjustment network 112 includes a first resistor sub-network 1121 and a first capacitor sub-network 1122. One end of the first resistor sub-network 1121 is connected to the feedback end of the sampling module 130, the other end of the first resistor sub-network 1121 is connected to one end of the first capacitor sub-network 1122, and one end of the first capacitor sub-network 1122 is also connected to the second input end of the comparison module 120.
[0040] In some embodiments, Figure 6 As shown, the first resistor sub-network 1121 may include a first resistor R1, and the first capacitor sub-network 1122 may include a first capacitor C1. One end of the first resistor R1 is connected to the feedback end of the sampling module 130, the other end of the first resistor R1 is connected to one end of the first capacitor C1, one end of the first capacitor C1 is also connected to the second input end of the comparison module 120, and the other end of the first capacitor C1 is used for grounding.
[0041] like Figure 6 As shown, in this embodiment, the measured signal VIN is transmitted to the first input terminal of the comparison module 120 through the adjustment module, wherein the first input terminal of the comparison module 120 is a positive input terminal, and the second input terminal of the comparison module 120 is a negative input terminal.
[0042] like Figure 6As shown, the measured signal VIN is input from the positive input terminal of the comparison module 120, and the sampling module 130 feeds back the comparison signal output by the comparison module 120 to the negative input terminal of the comparison module 120 through the first adjustment network 112. When the circuit is finally in a balanced state, the DC levels of the positive input terminal and the negative input terminal of the comparison module 120 are equal.
[0043] The swing signal VCCIO is the output swing of the feedback signal PWM_out, and the duty cycle PWM_duty is the duty cycle of the waveform of the feedback signal PWM_out. Therefore, the positive input terminal of the comparison module 120 satisfies the following formula 1.
[0044] VIN=VCCIO*PWM_duty(Formula 1)
[0045] For applications using the differential IO (input-output port) of FPGA / CPLD as the comparison module 120, the maximum measurement range of the positive input terminal of the comparison module 120 should be slightly smaller than the swing signal VCCIO. For example, (VCCIO-0.3V) can be taken as the maximum range.
[0046] Wherein, the time constant τ=R*C, and in order to make the circuit work stably, the value of τ*Fclk needs to satisfy: 200<τ*Fclk<1000. R is the resistance of the first resistor R1, C is the capacitance of the first capacitor C1, and Fclk is the operating frequency of the system.
[0047] It can be known from equation 1 that in the embodiment of the present application, the swing signal VCCIO and PWM_duty are key factors affecting the actual measurement accuracy. To improve the measurement accuracy of the analog-to-digital conversion circuit 100, the swing signal VCCIO can use a high-precision power supply.
[0048] In some embodiments, Figure 7 As shown, the adjustment module 110 includes a protection network 111 and a first adjustment network 112 .
[0049] The protection network 111 includes a second resistor R2 and a third resistor R3. One end of the second resistor R2 is used to receive the test signal VIN, and one end of the second resistor R2 is also connected to one end of the third resistor R3; the other end of the third resistor R3 is connected to the positive input end of the comparison module 120.
[0050] The first adjustment network 112 includes a first resistor sub-network 1121 and a first capacitor sub-network 1122. One end of the first resistor sub-network 1121 is connected to the feedback end of the sampling module 130, the other end of the first resistor sub-network 1121 is connected to one end of the first capacitor sub-network 1122, and one end of the first capacitor sub-network 1122 is also connected to the second input end of the comparison module 120. The first resistor sub-network 1121 includes a first resistor R1, and the first capacitor sub-network 1122 includes a first capacitor C1.
[0051] Specifically, one end of the first resistor R1 is connected to the feedback end of the sampling module 130, the other end of the first resistor R1 is connected to one end of the first capacitor C1, one end of the first capacitor C1 is also connected to the second input end of the comparison module 120, and the other end of the first capacitor C1 is grounded.
[0052] In an embodiment of the present application, the third resistor R3 is used to protect the input and output pins of the chip (i.e., the positive input terminal of the comparison module, for example, a resistor with a resistance value of 10KΩ can be used; the second resistor R2 is used to avoid interference through a small static current, for example, a resistor with a resistance value of 510Ω can be selected. Among them, if there is a load in the circuit, the second resistor R2 can be ignored. The first resistor can be a resistor with a resistance value of 10KΩ, and the first capacitor can be a capacitor with a capacitance value of 1nF.
[0053] The test data of the monitoring voltage is shown in Table 1 below using a sampling rate of 3.8 KHz. It can be seen from Table 1 that the analog-to-digital conversion circuit provided in this embodiment can perform analog-to-digital conversion on the measurement level.
[0054] Table 1
[0055]
[0056] In some implementations, the adjustment module 110 is used to generate a first input signal according to a reference signal, and the adjustment module 110 is also used to generate a second input signal according to the signal to be measured and the feedback signal.
[0057] Alternatively, if Figure 8 As shown, the adjustment module 110 is used to receive a reference signal Vref. The reference signal Vref can be directly used as a first input signal. That is, the adjustment module 110 transmits the reference signal Vref to a first input terminal of the comparison module 120 .
[0058] Alternatively, if Fig. 9As shown, the adjustment module 110 may further include a voltage divider network 113. The input end of the voltage divider network 113 is used to receive the swing signal VCCIO. The swing signal VCCIO is the output swing of the conversion signal swing_outPWM_out. The voltage divider network 113 is used to divide the swing signal VCCIO to obtain a reference signal Vref.
[0059] In some embodiments, Fig.10 As shown, the adjustment module 110 further includes a second adjustment network 114, and the second adjustment network 114 is used to generate a second input signal according to the signal to be measured VIN and the feedback signal PWM_out.
[0060] Alternatively, if Fig.11 As shown, the second adjustment network 114 includes a second resistor sub-network 1141 and a second capacitor sub-network 1142. The first input end of the second resistor sub-network 1141 is used to receive the signal to be measured VIN, the second input end of the second resistor sub-network 1141 is used to receive the feedback signal PWM_out, the output end of the second resistor sub-network 1141 is connected to one end of the second capacitor sub-network 1142, and one end of the second capacitor sub-network 1142 is also connected to the second input end of the comparison module 120.
[0061] In some embodiments, Fig.12 As shown, the second resistor sub-network 1141 may include a fourth resistor R4 and a fifth resistor R5, and the second capacitor sub-network 1142 may include a second capacitor C2. One end of the fourth resistor R4 is used to receive the signal to be measured VIN, the other end of the fourth resistor R4 is connected to one end of the fifth resistor R5, one end of the fifth resistor R5 is also connected to one end of the second capacitor C2, the other end of the fifth resistor R5 is connected to the sampling module 130, and the other end of the fifth resistor R5 is used to receive the feedback signal PWM_out. One end of the second capacitor C2 is also connected to the second input end of the comparison module 120, and the other end of the second capacitor C2 is grounded.
[0062] In this embodiment, the reference signal Vref is transmitted to the first input terminal of the comparison module 120 through the adjustment module 110 , wherein the first input terminal of the comparison module 120 is a positive input terminal, and the second input terminal of the comparison module 120 is a negative input terminal.
[0063] like Fig.12As shown, the measured signal VIN is input from the positive input terminal of the comparison module 120 through the second adjustment network 114 of the adjustment module 110, and the sampling module 130 feeds back the comparison signal output by the comparison module 120 to the negative input terminal of the comparison module 120 through the second adjustment network 114. When the circuit is in the final balanced state, the DC levels of the first input terminal and the second input terminal of the comparison module 120 are equal. Among them, the reference signal Vref is the reference voltage of the positive input terminal of the comparison module 120, the fourth resistor R4, the fifth resistor R5 and the second capacitor C2 constitute the second adjustment network 114, and the analog signal conversion circuit provided by the embodiment of the present application has a wider range.
[0064] Assume that the maximum swing amplitude of the measured signal VIN is VINmax and the minimum value is 0; the duty cycle PWM_duty is the duty cycle of the waveform of the feedback signal PWM_out, and the swing signal VCCIO is the output swing amplitude of the feedback signal PWM_out. When the feedback circuit reaches equilibrium, the levels of the first input terminal and the second input terminal of the comparison module 120 are equal, and the level of the other end of the fifth resistor R5 is equivalent to VCCIO*PWM_duty.
[0065] When the measured signal VIN is at the maximum value VINmax, the duty cycle PWM_duty is at the minimum value of 0, and the level at the other end of the fifth resistor R5 is 0, then:
[0066] VINmax=Vref / R5*(R4+R5) (Equation 2)
[0067] When the measured signal VIN is at the minimum value 0, the value of the duty cycle PWM_duty is at the maximum value 1, and the level at the other end of the fifth resistor R5 is at the maximum value, satisfying:
[0068] Vref=VCCIO*R1 / (R4+R5) (Formula 3)
[0069] Furthermore, through equations (2) and (3), we can obtain:
[0070] VINmax=VCCIO*R4 / R5(Formula 4)
[0071] When the feedback circuit is dynamically balanced, Ohm's law gives:
[0072] VIN=Vref+(Vref-VCCIO*PWM_duty) / R5*R4(Formula 5)
[0073] From formula (5), we can get:
[0074] VIN=Vref / R5*(R4+R5)-VCCIO*R4 / R5*PWM_duty(Equation 6)
[0075] If Vref strictly satisfies equation 3, equation 6 can be simplified to:
[0076] VIN=VINmax(1-PWM_duty) (Equation 7)
[0077] For example: Assuming the maximum swing of the measured signal VIN is 0~13.2V, and the swing signal VCCIO is 3.3V, then R4 / R5=4, Vref=2.64V. Assuming PWM_duty is 23 / 256, then:
[0078] VIN=13.2*(256-23) / 256≈12.01V
[0079] In order to make the negative input feedback circuit work normally, the values of the fourth resistor R4, the fifth resistor R5 and the second capacitor C2 need to satisfy:
[0080] (1) The measurement range VINmax must be greater than the measured signal VIN, that is, equation (2) is satisfied;
[0081] (2) Input impedance R4+R5 / / (2*π*Fclk*C)-1, where Fclk is the operating frequency of the sampling circuit and should be large enough;
[0082] (3) Time constant τ=(R4 / / R5)*C, τ*Fclk needs to satisfy: 200<τ*Fclk<1000.
[0083] In the embodiment of the present application, it can be known from Formula 6 that the influencing factors of the mode conversion circuit 100 are the reference voltage Vref, the fourth resistor R4, the fifth resistor R5, the swing signal VCCIO and the actual accuracy of the duty cycle PWM_duty.
[0084] Assuming that the reference voltage Vref is generated by dividing the swing signal VCCIO through a voltage-dividing resistor, the equivalent resistance of the low voltage differential port on the editable logic device will affect the measurement accuracy. At this time, the fourth resistor R4 and the fifth resistor R5 can use small resistance and high-precision resistors, and the swing signal can use a high-precision power supply.
[0085] In some embodiments, Fig.13 As shown, the adjustment module 110 includes a voltage divider network 113 and a second adjustment network 114 .
[0086] The voltage divider network includes a sixth resistor R6 and a seventh resistor R7. One end of the sixth resistor R6 is used to receive the swing signal VCCIO, the other end of the sixth resistor R6 is connected to the positive input end of the comparison module, one end of the seventh resistor R7 is connected to the other end of the sixth resistor R6, and the other end of the seventh resistor R7 is grounded.
[0087] like Fig.13 As shown, the second adjustment network 114 includes a second resistance sub-network 1141 and a second capacitance sub-network 1142. The second resistance sub-network 1141 may include a fourth resistor R4 and a fifth resistor R5, and the second capacitance sub-network 1142 may include a second capacitor C2.
[0088] Among them, one end of the fourth resistor R4 is used to receive the signal to be measured VIN, the other end of the fourth resistor R4 is connected to one end of the fifth resistor R5, one end of the fifth resistor R5 is also connected to one end of the second capacitor C2, the other end of the fifth resistor R5 is connected to the sampling module 130, and the other end of the fifth resistor R5 is used to receive the feedback signal PWM_out. One end of the second capacitor C2 is also connected to the second input end of the comparison module 120, and the other end of the second capacitor C2 is used for grounding.
[0089] In the embodiment of the present application, in order to make the measurement value as accurate as possible, preferably, each set of measurement voltages is matched using different resistance and capacitance parameters. For example, corresponding resistance and capacitance parameters can be selected for matching at different measurement voltages with reference to Table 2.
[0090] Table 2
[0091]
[0092] Using a sampling rate of 3.8KHz, the test data of the monitoring voltage is shown in Table 3. It can be seen from Table 3 that the analog-to-digital conversion circuit provided in the embodiment of the present application can perform analog-to-digital conversion on the measurement level.
[0093] Table 3
[0094]
[0095] In some implementations, the sampling module 130 uses a high-frequency clock Fclk to sample a signal (eg, a 1-bit signal) output by the comparison module 120 , and outputs the sampled signal as a PWM feedback signal to the adjustment module 110 for feedback.
[0096] In some embodiments, Fig.14 As shown, the filtering module 140 includes a first filtering submodule 141 and a second filtering submodule 142; wherein the first filtering submodule 141 is connected to the output end of the sampling module 130, and the first filtering submodule 141 is used to perform accumulation processing on the feedback signal to obtain an accumulated signal. The second filtering submodule 142 is connected to the first filtering submodule 141, and the second filtering submodule 142 is used to perform summing and averaging processing on the accumulated signal to obtain a conversion signal.
[0097] In the embodiment of the present application, a two-stage digital filtering design is used, such as Fig.12As shown, the first filtering submodule 141 is a first-stage filtering, which samples the comparison signal of the comparison module 120 and then accumulates it, and the second filtering submodule 142 is a second-stage filtering, which sums and averages the accumulated values of the first-stage filtering to obtain the duty cycle of the output PWM_duty.
[0098] Among them, the accumulation period of the first-level filter is 2 ACCU_WIDTH , each accumulation cycle outputs 1 valid value, the effective bit width of the output is DATA_WIDTH, and the accumulation cycle of the second-stage filter is 2 LPF_WIDTH , one valid value is output in each accumulation cycle, and the effective bit width of the output is DATA_WIDTH.
[0099] Assuming the system operating frequency is Fclk, the output frequency of the first filter submodule is:
[0100] F1=Fclk / 2ACCU_WIDTH
[0101] The output frequency of the second filter, also the sampling frequency of the output, is:
[0102] F sample =F1 / 2 LPF_WIDTH =Fclk / 2 ACCU_WIDTH+LPF_WIDTH
[0103] For example: Assuming that the system operating frequency Fclk is 62.5 MHz, the accumulated bit width ACCU_WIDTH is 10, and the second-stage filter coefficient LPF_WIDTH is 4, the sampling rate Fsample = 3.814 KHz.
[0104] In the embodiment of the present application, the resolution of the analog-to-digital conversion circuit 100 depends on the data bit width of the analog-to-digital conversion circuit 100, and satisfies: resolution = ± 1 / 2 * VINmax / 2 DATA_WIDTH .
[0105] Assuming the measurement range VINmax is 12V, an 8-bit analog-to-digital conversion circuit can theoretically handle applications with 12±23mV.
[0106] Optionally, the data bit width of the conversion signal swing_out of the analog-to-digital conversion circuit can be selected to be 8 bits, 10 bits, etc.
[0107] Optionally, the data bit width of the first filtering submodule 414 is not less than the data bit width of the analog-to-digital conversion circuit 100 .
[0108] Optionally, the data bit width of the filter coefficient of the second filter submodule can be selected from 3 bits, 4 bits, 5 bits, 6 bits, 7 bits, 8 bits, etc.
[0109] See also Fig.15 The embodiment of the present application also provides an analog-to-digital conversion system 200, which includes multiple analog-to-digital conversion circuits 100 as described in the above embodiment. The analog-to-digital conversion system 200 also includes an observation module 210, which is used to receive conversion signals from multiple analog-to-digital conversion circuits. The observation module 210 is also used to determine a target signal among the multiple conversion signals according to the observation operation and output the target signal.
[0110] The analog-to-digital conversion system 200 may include a clock module for generating a working clock.
[0111] In summary, an analog-to-digital conversion circuit and an analog-to-digital conversion system are provided in an embodiment of the present application, wherein the analog-to-digital conversion circuit includes an adjustment module, a comparison module, a sampling module and a filtering module; the adjustment module is used to generate a first input signal and a second input signal according to a signal to be measured and a feedback signal; the comparison module is used to generate a comparison signal according to the first input signal and the second input signal; the sampling module is used to generate a sampling feedback signal according to the comparison signal; a feedback end of the sampling module is connected to a feedback end of the adjustment module; the filtering module is connected to an output end of the sampling module, and the filtering module is used to filter the sampling feedback signal to generate a conversion signal; wherein the comparison module, the sampling module and the filtering module are arranged in a programmable logic device, and the first input end and the second input end are low voltage differential signal ports; thereby, the analog-to-digital conversion function is realized based on the programmable logic device, which has high flexibility, effectively saves board-level costs, and shortens the project development cycle.
[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. An analog-to-digital conversion circuit, characterized in that: The circuit comprises: An adjustment module, wherein an input end of the adjustment module is used to receive a signal to be tested, a feedback end of the adjustment module is used to receive a sampled feedback signal, and is used to generate a first input signal and a second input signal according to the signal to be tested and the feedback signal; wherein the signal to be tested is an analog signal; A comparison module, wherein a first input terminal of the comparison module is used to receive the first input signal, and a second input terminal of the comparison module is used to receive the second input signal; the comparison module is used to generate a comparison signal according to the first input signal and the second input signal; and an output terminal of the comparison module is used to output the comparison signal; A sampling module, wherein the input end of the sampling module is connected to the output end of the comparison module, and the sampling module is used to generate the sampling feedback signal according to the comparison signal; the feedback end of the sampling module is connected to the feedback end of the adjustment module; A filtering module, the filtering module is connected to the output end of the sampling module, and the filtering module is used to filter the sampled feedback signal to generate a conversion signal; The comparison module, the sampling module and the filtering module are arranged in a programmable logic device, and the first input end and the second input end are low voltage differential signal ports of the programmable logic device.
2. The analog-to-digital conversion circuit according to claim 1, characterized in that: The adjustment module is used to generate the first input signal according to the signal to be tested; the adjustment module is also used to generate the second input signal according to the feedback signal.
3. The analog-to-digital conversion circuit according to claim 2, characterized in that: The adjustment module further includes a protection network, an input end of the protection network is used to receive the signal to be tested, and an output end of the protection network is connected to the first input end of the comparison module.
4. The analog-to-digital conversion circuit according to claim 2, characterized in that: The adjustment module further includes a first adjustment network, and the first adjustment network is used to generate the second input signal according to the feedback signal.
5. The analog-to-digital conversion circuit according to claim 4, characterized in that: The first adjustment network includes a first capacitor sub-network and a first resistor sub-network, one end of the first resistor sub-network is connected to the feedback end of the sampling module, the other end of the first resistor sub-network is connected to one end of the first capacitor sub-network, and one end of the first capacitor sub-network is also connected to the second input end of the comparison module.
6. The analog-to-digital conversion circuit according to claim 1, characterized in that: The adjustment module is used to generate the first input signal according to a reference signal; the adjustment module is also used to generate the second input signal according to the signal to be measured and the feedback signal.
7. The analog-to-digital conversion circuit according to claim 6, characterized in that: The adjustment module further includes a voltage divider network, an input end of the voltage divider network is used to receive a swing signal, the swing signal is the output swing of the conversion signal, and the voltage divider network is used to perform voltage division processing on the swing signal to obtain the reference signal.
8. The analog-to-digital conversion circuit according to claim 6, characterized in that: The adjustment module further includes a second adjustment network, and the second adjustment network is used to generate the second input signal according to the signal to be measured and the feedback signal.
9. The analog-to-digital conversion circuit according to claim 8, characterized in that: The second adjustment network includes a second capacitor sub-network and a second resistor sub-network; The first input end of the second resistor sub-network is used to receive the signal to be measured, the second input end of the second resistor sub-network is used to receive the feedback signal, the output end of the second resistor sub-network is connected to the input end of the second capacitor sub-network, and the input end of the second capacitor sub-network is also connected to the second input end of the comparison module.
10. The analog-to-digital conversion circuit according to any one of claims 1 to 9, characterized in that: The filtering module includes a first filtering submodule and a second filtering submodule; Wherein, the first filtering submodule is connected to the output end of the sampling module, and the first filtering submodule is used to perform accumulation processing on the feedback signal to obtain an accumulated signal; The second filtering submodule is connected to the first filtering submodule, and the second filtering submodule is used to perform summing and averaging processing on the accumulated signal to obtain the conversion signal.
11. The analog-to-digital conversion circuit according to claim 10, characterized in that: The data bit width of the first filtering submodule is not less than the data bit width of the analog-to-digital conversion circuit.
12. An analog-to-digital conversion system, characterized in that: The analog-to-digital conversion system includes multiple analog-to-digital conversion circuits as described in any one of claims 1 to 11, and the analog-to-digital conversion system also includes an observation module, which is used to receive conversion signals of the multiple analog-to-digital conversion circuits. The observation module is also used to determine a target signal among the multiple conversion signals based on an observation operation and output the target signal.