Microdisplay device with metal fence

Abstract

The utility model discloses a micro display device with a metal fence, and relates to the technical field of semiconductors. The micro-display device comprises a driving wafer, wherein the driving wafer comprises an anode contact; the display module is integrated with the driving wafer through a bonding metal layer, the display module comprises a pixel unit corresponding to the anode contact and a metal fence surrounding the pixel unit, and the metal fence is of a fence type structure generated in the process of etching the bonding metal layer through ion beams; wherein the metal fence forms a cylindrical optical resonant cavity for the pixel unit, and the optical resonant cavity is used for reflecting light waves emitted by the pixel unit back and forth in the optical resonant cavity so as to provide optical positive feedback. According to the structure disclosed by the invention, the elimination process of a metal fence is canceled, and the technological process is greatly simplified.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a micro display device with a metal fence. Background Art

[0002] In the field of monolithic integrated micro-display devices (Micro-LED), non-aligned wafer-level bonding processes have been increasingly widely used. In the conventional chip preparation process, after completing the hot compression bonding of the compound semiconductor and the driver wafer, the metal of the bonding layer needs to be completely etched away through an etching process to form electrical isolation between the pixels.

[0003] Since the metal used for hot-press bonding is usually a "non-volatile metal", its etching usually adopts ion beam etching (IBE) etching technology. In the IBE etching process, the etching system ionizes the inert gas through multiple systems such as the ion optical system to form a neutral ion beam. The neutral ion beam bombards the metal surface, thereby sputtering the atoms on the metal surface to complete the etching process. It is a purely physical bombardment process. Since the metal being etched is a "non-volatile metal", such as Figure 1 As shown in the figure, metal atoms are easily re-sputtered and deposited on the sidewalls of the photoresist mask to form metal fences. If the metal fences formed during the IBE etching process are not properly processed and removed after the etching is completed, the fences will cause a short circuit between the P and N poles of the device in the subsequent interconnection process, causing leakage, thereby greatly reducing the photoelectric performance of the device, and even causing device failure in severe cases.

[0004] Therefore, fence elimination methods are generally adopted. However, various fence elimination methods not only have complicated and cumbersome processes, but also cannot completely eliminate the metal fence, thereby affecting device performance. Utility Model Content

[0005] The utility model aims to provide a micro display device with a metal fence, which fully utilizes the metal fence generated in the IBE metal etching process to form an optical resonant cavity structure with the micro display device.

[0006] In order to achieve the above-mentioned utility model purpose, the utility model proposes the following technical solutions:

[0007] In one aspect, a micro display device having a metal fence is provided, the micro display device comprising:

[0008] A driving wafer, wherein the driving wafer includes an anode contact; a display module integrated with the driving wafer through a bonding metal layer, wherein the display module includes a pixel unit corresponding to the anode contact and a metal fence surrounding the pixel unit, wherein the metal fence is a fence-style structure generated during ion beam etching of the bonding metal layer;

[0009] The metal fence forms a cylindrical optical resonant cavity for the pixel unit, and the optical resonant cavity is used to reflect the light waves emitted by the pixel unit back and forth therein to provide optical positive feedback.

[0010] In a possible implementation, the pixel unit at least includes: the bonding metal layer, the P-type ohmic contact layer, the compound semiconductor layer and the N-type ohmic contact layer vertically stacked in sequence in a direction away from the driving wafer;

[0011] The bottom of the metal fence is connected to a side of the driving wafer close to the display module;

[0012] The sidewall of the metal fence contacts the sidewalls of the bonding metal layer and the P-type ohmic contact layer, and is spaced apart from the sidewalls of the compound semiconductor layer and the N-type ohmic contact layer.

[0013] In a possible implementation manner, a top height of the metal fence is not lower than a top height of the compound semiconductor layer.

[0014] In a possible implementation, the display module further includes:

[0015] an insulating layer, wherein the insulating layer is filled in the blank space of the display module;

[0016] A common cathode includes: a first cathode connection structure, the first cathode connection structure is covered on a side surface of the insulating layer away from the driving wafer, and is connected to the N-type ohmic contact layer.

[0017] In a possible implementation, the common cathode further includes: a second cathode connection structure, the second cathode connection structure is embedded in the insulating layer between two adjacent pixel units, and one end of the second cathode connection structure away from the driving wafer is connected to the first cathode connection structure.

[0018] In a possible implementation, the top of the insulating layer is flush with the top of the N-type ohmic contact layer, and the first cathode connection structure horizontally covers the top of the insulating layer and the N-type ohmic contact layer;

[0019] or,

[0020] The top of the insulating layer is higher than the top of the N-type ohmic contact layer, and the height of the portion of the first cathode connection structure covering the top of the insulating layer is higher than the height of the portion of the first cathode connection structure covering the top of the N-type ohmic contact layer;

[0021] or,

[0022] The insulating layer is adhered to and covered on the side wall of the pixel unit, and the first cathode connection structure covers the outer surface of the insulating layer and the top of the N-type ohmic contact layer.

[0023] In a possible implementation, the common cathode is made of a transparent conductive film.

[0024] In a possible implementation, a microlens structure is disposed on a surface of the first cathode connection structure on a side away from the driver wafer, and a projection of the metal fence on the driver wafer is within a projection of the microlens structure on the driver wafer.

[0025] Compared with the prior art, the utility model has the following beneficial effects:

[0026] The driving wafer and display module in the micro display device are bonded and integrated through a bonding metal layer. Due to the physical characteristics, a metal fence will inevitably be formed through the process of ion beam etching the bonding metal layer. This metal fence is fully utilized to form an optical resonant cavity for the pixel unit in the display module. There is no need to perform a fence elimination process, which simplifies the overall process flow and greatly improves process stability, production efficiency and capacity. At the same time, the formation of an optical resonant cavity can also improve the brightness of the micro display device.

[0027] Furthermore, the side walls of the metal fence are in contact with the side walls of the bonding metal layer and the P-type ohmic contact layer in the pixel unit, and are spaced apart from the side walls of the compound semiconductor layer and the N-type ohmic contact layer. An insulating layer is filled between the metal fence and the pixel unit to avoid a short circuit between the P and N poles of each pixel unit, thereby minimizing the pixel spacing, maximizing the pixel light-emitting area, improving the pixel density, and increasing the resolution of the microdisplay device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of forming a metal fence in the process of ion beam etching bonding metal provided in the related art;

[0029] Figure 2 It is a structural schematic diagram of a micro display device with a large pixel pitch provided in the related art;

[0030] Figure 3 is a schematic structural diagram of a micro display device provided in an embodiment of the present application;

[0031] Figure 4 is a schematic structural diagram of a micro display device provided in an embodiment of the present application;

[0032] Figure 5 is a schematic structural diagram of a micro display device provided in an embodiment of the present application;

[0033] Figure 6 is a schematic structural diagram of a micro display device with a second cathode connection structure provided in an embodiment of the present application;

[0034] Figure 7 is a schematic structural diagram of a micro display device with a second cathode connection structure provided in an embodiment of the present application;

[0035] Figure 8 is a schematic structural diagram of a micro display device with a micro lens structure provided in an embodiment of the present application;

[0036] Fig. 9 is a schematic structural diagram of a micro display device with a micro lens structure provided in an embodiment of the present application;

[0037] Fig.10 is a method flow chart of a method for preparing a micro display device provided in an embodiment of the present application;

[0038] Fig.11 It is a schematic diagram of the structure after a compound wafer and a driver wafer are bonded and integrated provided in an embodiment of the present application;

[0039] Fig.12 It is a schematic structural diagram of a compound wafer after a P-type ohmic contact layer is prepared according to an embodiment of the present application;

[0040] Fig.13 It is a schematic structural diagram of a compound wafer after a bonding metal layer is prepared according to an embodiment of the present application;

[0041] Fig.14 It is a schematic structural diagram of a driver wafer after a bonding metal layer is prepared according to an embodiment of the present application;

[0042] Fig.15 It is a schematic diagram of the structure after a compound wafer and a driver wafer are bonded and integrated provided in an embodiment of the present application;

[0043] Fig.16 is a schematic diagram of the structure of a continuous film layer in a display area provided in an embodiment of the present application;

[0044] Fig.17 It is a schematic structural diagram of a micro display device provided in an embodiment of the present application after removing the substrate of the compound wafer;

[0045] Fig.18 It is a schematic structural diagram of a micro display device provided in an embodiment of the present application that completes pixelation preparation on a compound wafer;

[0046] Fig.19 is a schematic structural diagram of a micro display device after a first photoresist layer is prepared according to an embodiment of the present application;

[0047] Fig. 20 It is a schematic structural diagram of a micro display device prepared by a metal fence provided in an embodiment of the present application;

[0048] Fig.21 is a schematic structural diagram of a micro display device after the first photoresist layer is removed provided in an embodiment of the present application;

[0049] Fig. 22 It is a schematic diagram of the structure of a micro display device after the first insulating layer is prepared according to an embodiment of the present application.

[0050] Fig.23 It is a schematic structural diagram of a micro display device after a second photoresist layer is prepared according to an embodiment of the present application.

[0051] Fig.24 It is a schematic diagram of the structure of a micro display device prepared with a metal fence provided in an embodiment of the present application.

[0052] Fig.25 It is a schematic structural diagram of a micro display device after the second photoresist layer is removed provided in an embodiment of the present application.

[0053] Fig.26 It is a schematic diagram of the structure of a micro display device after the second insulating layer is prepared according to an embodiment of the present application.

[0054] Fig. 27 It is a schematic diagram of the structure of a micro display device prepared with a metal fence provided in an embodiment of the present application.

[0055] Reference numerals:

[0056] 100-driving wafer, 200-display module, 300-compound wafer, 10-pixel unit, 11-bonding metal layer, 12-P-type ohmic contact layer, 13-compound semiconductor layer, 14-N-type ohmic contact layer, 20-metal fence, 30-insulating layer, 41-first cathode connection structure, 42-second cathode connection structure, 50-microlens structure. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0058] In the description of the present utility model, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, unless otherwise specified, "multiple" means two or more.

[0059] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] In the field of monolithic integrated micro-display devices (Micro-LED), non-aligned wafer-level bonding processes have become increasingly widely used. The conventional chip preparation process can be summarized as the following main steps: (1) Depositing bonding metal on the surface of compound (such as GaN) wafers and driver wafers → (2) Hot-press bonding of compound wafers and CMOS driver wafers → (3) Device preparation through semiconductor processes such as lithography and etching → (4) Electrically interconnecting the device and driver wafer through semiconductor interconnection processes.

[0061] Exemplarily, bonding metal is first deposited on a silicon-based GaN wafer or a sapphire-based GaN wafer and a driver wafer by electron beam evaporation, and then the GaN wafer (silicon-based or sapphire-based) and the driver wafer are integrated together by hot compression bonding, and then the GaN substrate is removed by wet etching or by laser stripping, and then the GaN is etched into independent pixels by photolithography and etching processes, and the bonding metal is completely etched away by an etching process, thereby forming electrical isolation between the pixels, and finally the N pole of the GaN is interconnected by a transparent conductive electrode.

[0062] In the above process, a very important step is to "completely etch the bonding metal through the etching process to form electrical isolation between pixels." In the IBE etching process corresponding to etching, metal atoms are easily re-sputtered and deposited on the sidewalls of the photoresist mask, forming Figure 1 Metal fences (fens) shown.

[0063] Since the 1970s, the metal fence formed by IBE etching metal has become an extremely troublesome defect in the field of semiconductor chip manufacturing. Although the industry, academia and research community have long been committed to seeking ways to eliminate the fence, due to its physical properties, no breakthrough has been made. Commonly used methods to eliminate the fence include: (1) Photoresist morphology adjustment: The main principle is to adjust the morphology of the photoresist to make it hemispherical, so that the fence sputtered to the side wall of the photoresist is etched away during the etching process; (2) IBE ion beam incident angle adjustment: The main principle is to adjust the IBE ion beam incident angle so that the fence sputtered to the side wall of the photoresist is etched away during the etching process; (3) Physical treatment elimination: The main principle is to repeatedly heat / cool the photoresist to physically disconnect the fence through thermal expansion and contraction, and then clean the fence in the subsequent stripping process.

[0064] The above-mentioned fence elimination methods not only have complicated and cumbersome processes, but also cannot completely eliminate the fence. Therefore, in the field of manufacturing monolithic integrated micro-display devices (Micro-LED), in addition to taking the above-mentioned fence elimination methods, it is also necessary to increase the spacing between pixels to reduce the short circuit risk caused by metal fences (such as Figure 2 The direct consequences of increasing the pixel pitch include: (1) the reduction of the pixel light-emitting area, which affects the brightness performance of the device; (2) the reduction of pixel density, which affects the resolution of the micro-display device.

[0065] In order to avoid the above problems, in an embodiment of the present application, a technical solution is proposed to fully utilize the metal fence generated during the IBE metal etching process to form an optical resonant cavity structure with the micro display device. This structure eliminates the process of eliminating the metal fence and greatly simplifies the process.

[0066] First, the specific structure of the micro display device proposed in this application is described.

[0067] The present application embodiment provides a micro display device, such as Figures 3 to 5 As shown, the micro display device includes:

[0068] A driving wafer 100, wherein the driving wafer 100 includes an anode contact; a display module 200 integrated with the driving wafer 100 via a bonding metal layer 11, wherein the display module 200 includes a pixel unit 10 corresponding to the anode contact, and a metal fence 20 surrounding the pixel unit 10, wherein the metal fence 20 is a fence-style structure generated during ion beam etching of the bonding metal layer.

[0069] The metal fence 20 forms a cylindrical optical resonant cavity for the pixel unit 10, and the optical resonant cavity is used to reflect the light waves emitted by the pixel unit 10 back and forth therein to provide optical positive feedback and confine the light energy corresponding to the light waves in the optical resonant cavity.

[0070] It is understandable that the driving wafer 100 and the pixel unit 10 may be in a one-to-one relationship or a one-to-many relationship, that is, the driving wafer 100 may include only one anode contact, and one pixel unit 10 electrically connected to the anode contact is correspondingly provided, or the driving wafer 100 may include multiple anode contacts, and multiple pixel units 10 electrically connected to the anode contacts are correspondingly provided. In addition, the corresponding relationship between the anode contact and the pixel unit 10 may be one-to-one, or multiple anode contacts may correspond to one pixel unit 10.

[0071] Among them, the driving wafer 100 can be an active design that combines one or more of a thin film transistor (TFT), a low temperature polycrystalline silicon (LTPS), a CMOS integrated circuit, a high mobility transistor (HEMT), etc. Specifically, the driving wafer 100 is provided with a driving circuit, and the driving circuit is provided with at least one anode contact. The driving circuit may include an active, passive or semi-passive control circuit. All anode contacts included in the driving circuit may be arranged linearly or in an array, and any anode contact is located in the middle or at the edge of the driving wafer 100, which is not limited in this embodiment.

[0072] Among them, the pixel unit 10 in the display module 200 is usually a compound wafer or a suitable size area cut from a compound wafer. Taking a compound wafer as an example, the wafer refers to a compound formed by two or more elements, including crystalline inorganic compounds (such as III-V group, II-VI group compound semiconductors) and oxide semiconductors. The compound wafer involved in the embodiment of the present application is mainly an LED epitaxial material, such as an InGaN ternary material system or an AlGaInP quaternary material system, etc., and its luminous wavelength can cover the entire band from ultraviolet, visible light and infrared, and its substrate material can be GaN, Si, SiC, Sapphire, etc.

[0073] Taking the Micro-LED field as an example, the materials of some compound wafers involved in this application are shown in the following table. In some practical applications, the film layer of the compound wafer will be more complicated, or there will be cross-use of materials. It typically mainly includes a P-type ohmic contact layer, an N-type ohmic contact layer, and a multiple quantum well (MQW) sandwiched between the two and other functional layers. In this application, the functional layer between the P-type ohmic contact layer and the N-type ohmic contact layer is recorded as a compound semiconductor layer:

[0074]

[0075] Among them, the driving wafer 100 and the display module 200 are bonded and integrated through the bonding metal layer 11. The material of the bonding metal layer 11 can be a combination of multiple metal materials, such as: Ni, Sn combination, Au, Sn combination, Cu, Sn combination, Au, In combination, Au, Au combination, Al, Al combination, Cu, Cu combination, ITO, ITO combination, etc. One or more. Further, the bonding metal layer 11 and the driving wafer 100 / display module 200 can also include an adhesion layer and a blocking depletion layer to form a bonding structure together. Among them, the adhesion layer is used to increase the adhesion between the upper and lower layers, and the material of the adhesion layer can be Cr, Ti, Ni, etc. The blocking depletion layer is used to block the migration of the metal, and the material of the blocking depletion layer can be Ni, Pt, Cu, etc. Further, the bonding structure on the driving wafer 100 and the display module 200 can be symmetrical or asymmetrical. If necessary, a reflective layer such as Al, Ag, Au, etc. can be introduced into the bonding structure.

[0076] Exemplarily, using AuSn bonding, the bonding structure on the surface of the display module 200 is Ni (10A, adhesion layer) / AlCu (80nm, reflective layer) / NiV (10nm, blocking layer) / Au (100nm) / Sn (150nm) / Au (50nm), and the bonding structure on the surface of the driving wafer 100 is Cr (10nm, adhesion layer) / Pt (50nm, blocking depletion layer) / Au (100nm) / Sn (150nm) / Au (50nm).

[0077] Exemplarily, using CuCu bonding, the bonding structure on the surface of the display module 200 is Ni (10A, adhesion layer) / AlCu (80nm, reflective layer) / NiV (10nm, barrier layer) / Cu (300nm, bonding layer), and the bonding structure on the surface of the driving wafer 100 is Ti (20nm, adhesion layer) / Cu (300nm, bonding layer).

[0078] The display module 200 is provided with a metal fence 20 surrounding the pixel unit 10, and the metal fence 20 is a fence-style structure generated in the process of IBE isolating the bonding metal layer 11. Specifically, after the display module 200 and the driving wafer 100 are integrated through the bonding metal layer 11 and the pixel unit 10 is prepared, when the bonding metal layer 11 is patterned by IBE etching, the metal atoms corresponding to the bonding metal layer 11 are re-sputtered and deposited to form the metal fence 20 surrounding the pixel unit 10.

[0079] In the present application, the metal fence 20 is fully utilized. The metal fence 20 forms a cylindrical optical resonant cavity for the pixel unit 10. The optical resonant cavity is a cavity in which light waves can reflect back and forth to provide optical positive feedback. It is usually composed of two or more optical reflective mirrors (implemented by the metal fence 20 in the present application). Because of its role in enhancing and regulating light energy, it is widely used in optical fields such as lasers. In the present application, the light waves emitted by the pixel unit 10 circle around in the optical resonant cavity, connected head to tail, forming constructive interference, and all the light energy is bound in the resonant cavity, which increases the energy density per unit volume of the resonant cavity, thereby greatly improving the luminous efficiency of the microdisplay device. At the same time, the structure does not require a fence elimination process. It can be understood that the present application does not limit the specific style of the optical resonant cavity formed by the metal fence 20, such as a rectangular column style or a cylindrical style.

[0080] In one possible implementation, Figures 3 to 5As shown, the pixel unit 10 at least includes: a bonding metal layer 11, a P-type ohmic contact layer 12, a compound semiconductor layer 13 and an N-type ohmic contact layer 14 which are vertically stacked in sequence along a direction away from the driving wafer 100; the bottom of the metal fence 20 is connected to a side of the driving wafer 100 close to the display module 200; the side walls of the metal fence 20 are in contact with the side walls of the bonding metal layer 11 and the P-type ohmic contact layer 12, and are spaced apart from the side walls of the compound semiconductor layer 13 and the N-type ohmic contact layer 14.

[0081] like Figures 3 to 5 As shown, the surface dimensions corresponding to the bonding metal layer 11 and the P-type ohmic contact layer 12 are larger than the surface dimensions corresponding to the compound semiconductor layer 13 and the N-type ohmic contact layer 14. The projections of the compound semiconductor layer 13 and the N-type ohmic contact layer 14 on the driving wafer 100 are within the projections of the bonding metal layer 11 and the P-type ohmic contact layer 12 on the driving wafer 100. Therefore, the metal fence 20 extending in the vertical direction may have a bottom sidewall in contact with the sidewalls of the bonding metal layer 11 and the P-type ohmic contact layer 12, and a top sidewall may be spaced apart from the sidewalls of the compound semiconductor layer 13 and the N-type ohmic contact layer 14, thereby preventing the P-type ohmic contact layer 12 and the N-type ohmic contact layer 14 of the pixel unit 10 from being short-circuited through the metal fence 20, thereby causing leakage.

[0082] It is understandable that since the metal fence 20 is formed by metal atoms being reversely sputtered and deposited during the IBE etching process, in practice, the thickness of the metal fence 20 may vary in the vertical direction, specifically, the thickness gradually becomes thinner from the bottom to the top.

[0083] Furthermore, the top height of the metal fence 20 is not lower than the top height of the compound semiconductor layer 13. Since the light emitted by the pixel unit 10 is emitted through the compound semiconductor layer 13, when the top height of the metal fence 20 is not lower than the top height of the compound semiconductor layer 13, the metal fence 20 can effectively reflect the light emitted by the pixel unit 10, thereby enhancing and regulating the light energy.

[0084] In a possible implementation, the display module 200 also includes: an insulating layer 30, which fills the blank space of the display module 200; a common cathode, which includes: a first cathode connection structure 41, which is covered on the side surface of the insulating layer 30 away from the driving wafer 100 and is connected to the N-type ohmic contact layer 14.

[0085] like Figures 3 to 5As shown, the insulating layer 30 is filled in the display module 200, the optical resonant cavity formed by the metal fence 20 can be fixed, and the top metal fence 20 is insulated and isolated from the pixel unit 10, further avoiding the situation where the P-type ohmic contact layer 12 and the N-type ohmic contact layer 14 of the pixel unit 10 are short-circuited through the metal fence 20 to cause leakage. Among them, the insulating layer 30 is mainly silicon oxide, and optionally includes silicon oxide, aluminum oxide, silicon nitride, aluminum nitride and a combination of these, which is not limited in the present application.

[0086] like Figures 3 to 5 As shown, an N-type ohmic contact layer 14 is exposed on the top of the pixel unit 10, and a first cathode connection structure 41 connected to the exposed N-type ohmic contact layer 14 is prepared on the surface of the insulating layer 30 away from the driving wafer 100 as a common cathode. The common cathode can be a transparent conductive film, which can prevent the common cathode from blocking the light of the pixel unit 10 and improve the brightness of the pixel unit 10. The film layer of the transparent conductive film can be a combination of one or more of an ITO (Indium Tin Oxide) film, an AZO (Antimony doped Zinc Oxide) film, an ATO (Antimony doped Tin Oxide) film, and an FTO (Fluorine doped Tin Oxide) film; further, the surface of the ITO can be plated with Al, Au, and Ag and then annealed to form a metal-doped ITO to enhance the current transmission capacity of the common cathode.

[0087] Furthermore, the first cathode connection structure 41 may be implemented as follows: Figure 3 As shown, the top of the insulating layer 30 is flush with the top of the N-type ohmic contact layer 14, and the first cathode connection structure 41 horizontally covers the top of the insulating layer 30 and the N-type ohmic contact layer 14. The first cathode connection structure 41 can also be implemented as follows: Figure 4 As shown, the top of the insulating layer 30 is higher than the top of the N-type ohmic contact layer 14, and the height of the portion of the first cathode connection structure 41 covering the top of the insulating layer 30 is higher than the height of the portion of the first cathode connection structure 41 covering the top of the N-type ohmic contact layer 14. The first cathode connection structure 41 can also be implemented as follows: Figure 5 As shown, the insulating layer 30 is laminated and coated on the sidewall of the pixel unit 10 , and the first cathode connection structure 41 covers the outer surface of the insulating layer 30 and the top of the N-type ohmic contact layer 14 .

[0088] Further, such as Figure 6 , Figure 7As shown, the common cathode also includes: a second cathode connection structure 42 , which is embedded in the insulating layer 30 between two adjacent pixel units 10 , and one end of the second cathode connection structure 42 away from the driving wafer 100 is connected to the first cathode connection structure 41 .

[0089] In the insulating layer 30 between two adjacent units, a second cathode connection structure 42 connected to the first cathode connection structure 41 is also prepared. Specifically, the top of the second cathode connection structure 42 is connected to the first cathode connection structure 41 and extends in a direction toward the driver wafer 100, thereby having a certain depth. The second cathode connection structure 42 can be used for common cathode current expansion enhancement. Exemplary, Figure 6 Shown in Figure 3 The schematic diagram of adding the second cathode connection structure 42 to the corresponding structure, Figure 7 Shown in Figure 4 A schematic diagram of adding a second cathode connection structure 42 to the corresponding structure. The present application does not limit the specific depth of the second cathode connection structure 42, and the depth of the second cathode connection structure 42 can be flush with the bottom of the N-type ohmic contact layer 14 of the pixel unit 10, or can be deeper than the bottom of the N-type ohmic contact layer 14 of the pixel unit 10.

[0090] In one possible implementation, Figure 8 , Fig. 9 As shown, a microlens structure 50 is disposed on a surface of the first cathode connection structure 41 on one side away from the driver wafer 100, and the projection of the metal fence 20 on the driver wafer 100 is within the projection of the microlens structure 50 on the driver wafer 100. A microlens structure 50 may be disposed on the top of the display module 200, and the microlens structure 50 is used to further enhance the brightness of the light emitted by the pixel unit 10. The material of the microlens structure 50 may be a compound semiconductor, or may be a deposited dielectric material such as silicon oxide, silicon nitride, or the like.

[0091] Exemplarily, the dimension data of the micro display device introduced in the above embodiment is illustrated as an example, the width of the insulating layer between the metal fence 20 and the side wall of the pixel unit 10 is denoted as D1, the width of the metal fence 20 is denoted as d, the height is denoted as h, the width of the pixel unit 10 is denoted as D2, the height is denoted as H, and the spacing between the outsides of two adjacent metal fences 20 is denoted as D3, which may have the following dimension data: 50nm≤D1≤D2 / 2; 110nm≤D2≤1000um; 28nm≤d≤1um; 50nm≤h≤H; 180nm≤H≤5um; 90nm≤D3≤D2 / 2.

[0092] To summarize, in the microdisplay device provided in the embodiment of the present application, the driving wafer and the display module in the microdisplay device are bonded and integrated through a bonding metal layer. Due to the physical characteristics, a metal fence is inevitably formed through the process of ion beam etching the bonding metal layer. This metal fence is fully utilized to form an optical resonant cavity for the pixel unit in the display module. There is no need to perform a fence elimination treatment process, which simplifies the overall process flow and greatly improves process stability, production efficiency and capacity. At the same time, the formation of an optical resonant cavity can also improve the brightness of the microdisplay device.

[0093] Furthermore, the side walls of the metal fence are in contact with the side walls of the bonding metal layer and the P-type ohmic contact layer in the pixel unit, and are spaced apart from the side walls of the compound semiconductor layer and the N-type ohmic contact layer. An insulating layer is filled between the metal fence and the pixel unit to avoid a short circuit between the P and N poles of each pixel unit, thereby minimizing the pixel spacing, maximizing the pixel light-emitting area, improving the pixel density, and increasing the resolution of the microdisplay device.

[0094] Next, the preparation method of the micro display device described in the above embodiment is described. Fig.10 As shown, the method may include the following steps:

[0095] S1: Prepare a driving wafer, which includes an anode contact.

[0096] Specifically, the driver wafer includes anode contacts in a vertical direction, and an insulating medium is arranged around the anode contacts.

[0097] S2: preparing a display module, wherein the display module is integrated with a driving wafer through a bonding metal layer, wherein the display module includes a pixel unit corresponding to an anode contact, and a metal fence surrounding the pixel unit, wherein the metal fence is a fence-style structure generated in the process of ion beam etching the bonding metal layer.

[0098] The metal fence forms a cylindrical optical resonant cavity for the pixel unit, and the optical resonant cavity is used to cause the light waves emitted by the pixel unit to form constructive interference, thereby confining the light energy corresponding to the light waves in the optical resonant cavity.

[0099] Wherein, S2 may specifically include the following steps S21 to S24:

[0100] S21: The compound wafer and the driver wafer are bonded and integrated via a bonding metal layer.

[0101] Specifically, since bonding metal has been deposited on the surfaces of the compound wafer and the driver wafer, the bonding metal on the surfaces of the two wafers is used to form a bonding metal layer, and the two wafers are integrated together by wafer-level thermal compression bonding to form a bonding metal layer. Fig.11 The structure shown, Fig.11In the structure shown, the bonding metal layer is continuous across the entire surface of the wafer.

[0102] In a possible implementation, step S21 specifically includes the following steps:

[0103] (1) Preparation of P-type ohmic contact layer on the P side of the compound wafer

[0104] Specifically, Fig.12 As shown, a P-type ohmic contact layer 12 is prepared on the P surface of the compound wafer 300, and its P-type contact material can be a transparent conductive material such as ITO, ZnO, etc., or a metal material such as Ni whose work function is greater than the work function of the P-type semiconductor.

[0105] In one embodiment, a Si-based blue light InGaN compound is selected as a compound wafer, and an ITO film is coated on its P surface by evaporation, sputtering, etc. The ITO film thickness is 70nm, and an ohmic contact is formed by high-temperature annealing at 550°C in an N2 environment. The thickness of the P-type ohmic contact layer on the surface of the compound wafer and the conditions for forming the contact can be adjusted according to needs.

[0106] (2) Bonding metal layers are respectively prepared on the surface of the P-type ohmic contact layer of the compound wafer and the surface of the driving wafer, and at least one of the two bonding metal layers is continuous in the pixel area and supported by an insulating medium in the non-pixel area.

[0107] Specifically, Fig.13 As shown, a bonding metal is deposited on the P-type ohmic contact layer 12 by a general semiconductor thin film growth method such as plasma vapor deposition, evaporation, sputtering, atomic layer deposition (ALD), etc. to form a bonding metal layer 11. Accordingly, as shown in FIG. Fig.14 As shown, bonding metal is also deposited on the surface of the driving wafer 100 to form another bonding metal layer 11 .

[0108] The bonding metal layer may be continuous only in the pixel region, which is the region for preparing the pixel unit, but a discontinuous film layer in the non-pixel region, which is filled with an insulating medium for support, such as Fig.15 As shown, the bonding metal layer on the surface of the compound wafer 300 is continuous only in the pixel area, and the bonding metal layer on the surface of the driving wafer 100 is continuous over the entire surface of the wafer. Fig.16 As shown, the granularity of the continuous film layer can be a single display area or multiple display areas, and each display area corresponds to a micro display chip.

[0109] (3) The compound wafer and the driver wafer are bonded and integrated via the bonding metal layers on their respective surfaces.

[0110] S22: removing the substrate of the compound wafer to expose the N-type ohmic contact layer in the compound wafer.

[0111] Specifically, the substrate of the compound wafer is removed by a substrate removal method. After the substrate is removed, Fig.17 As shown, the N-type ohmic contact layer 14 in the compound wafer 300 will be exposed on the surface of the compound wafer 300. The substrate removal method can adopt corresponding process methods according to different substrate materials, such as laser stripping to remove sapphire substrate, HNA wet etching to remove silicon substrate, etc., which is not limited in this application.

[0112] S23: using the P-type ohmic contact layer in the compound wafer as an etching cutoff layer, etching to obtain a pixel unit.

[0113] Specifically, after exposing the N-type ohmic contact layer of the compound wafer, Fig.18 As shown, through semiconductor lithography and etching processes, the compound wafer is patterned to prepare pixels with the P-type ohmic contact layer 12 as the etching stop layer, and the pixel unit 10 corresponds to the anode contact in the driving wafer 100, and the pixel unit 10 can cover the corresponding anode contact.

[0114] S24: Patterning the bonding metal layer through ion beam etching to generate a metal fence surrounding the pixel unit.

[0115] Among them, the formation of the metal fence can specifically adopt any one of the following three schemes.

[0116] Option 1:

[0117] (1) Fig.19 As shown, a photoresist mask is used to cover the top and side surfaces of the pixel unit 10 to form a first photoresist layer.

[0118] The photoresist may be of positive polarity or reverse polarity, which is not limited in the present application.

[0119] (2) Fig. 20 As shown, the bonding metal layer 11 is patterned by ion beam etching using the first photoresist layer as a mask to generate a metal fence 20 surrounding the pixel unit 10 .

[0120] (3) Fig.21 As shown, the first photoresist layer is removed.

[0121] Option 2:

[0122] (1) Fig. 22 As shown, the first insulating layer is used to fill the top and side surfaces of the pixel unit 10 and the outer surface of the P-type ohmic contact layer 12 .

[0123] The first insulating layer may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), ALD, spin coating, etc.

[0124] (2) Fig.23 As shown, a photoresist mask is used to cover the first insulating layer on the top of the pixel unit 10 to form a second photoresist layer.

[0125] The photoresist may be of positive polarity or reverse polarity, which is not limited in the present application.

[0126] (3) Fig.24 As shown, the bonding metal layer 11 is patterned by ion beam etching using the second photoresist layer as a mask to generate a metal fence 20 surrounding the pixel unit 10 .

[0127] (4) Fig.25 As shown, the second photoresist layer is removed.

[0128] Option 3:

[0129] (1) Fig.26 As shown, the second insulating layer is used to fill the top and side surfaces of the pixel unit 10 and the outer surface of the P-type ohmic contact layer 12 .

[0130] The second insulating layer may be formed by CVD, PVD, ALD, spin coating, etc.

[0131] (2) Fig. 27 As shown, on the basis of retaining the second insulating layer on the side of the pixel unit 10, the second insulating layer on the top of the pixel unit 10 is used as a mask, and the bonding metal layer 11 is patterned by ion beam etching to generate a metal fence 20 surrounding the pixel unit 10.

[0132] In a possible implementation, after the metal fence is generated in step S24, it is still necessary to perform electrical connection of the pixel unit, which can be achieved by specifically including the following steps:

[0133] S25: using a third insulating layer to fill the entire blank area of ​​the display module.

[0134] The third insulating layer may be formed by CVD, PVD, ALD, spin coating, etc.

[0135] S26: performing a planarization process or a patterning etching process on the third insulating layer to expose the N-type ohmic contact layer of the pixel unit.

[0136] S27: Depositing a transparent conductive film on the surface of the N-type ohmic contact layer and the surface of the third insulating layer to construct a first cathode connection structure.

[0137] Specifically, a transparent conductive film can be deposited by sputtering, evaporation, etc., so as to form a first cathode connection structure on the surface of the N-type ohmic contact layer and the surface of the third insulating layer. The first cathode connection structure is entirely covered on the outer surface of the display module away from the driving wafer.

[0138] In one embodiment, if Figure 3 As shown, chemical mechanical polishing (CMP) is used to flatten the surface and expose the N-type ohmic contact layer 14, and then a transparent conductive film is deposited to form the first cathode connection structure 41. In one embodiment, as Figure 4 , Figure 5 As shown, pattern etching is used to expose the N-type ohmic contact layer 14 , and then a transparent conductive film is deposited to form the first cathode connection structure 41 .

[0139] Furthermore, after step S27, the method further includes: constructing a microlens structure on a surface of the first cathode connection structure that is away from the driver wafer.

[0140] Specifically, Figure 8 , Fig. 9 As shown, the brightness can be improved by preparing a microlens structure 50 on the first cathode connection structure 41. The inorganic silicon oxide or nitride oxide prepared by PSG (phosphate glass), BPSG (borophosphosilicate glass) process or TEOS (tetraethoxysilane), TEPO (triethyl phosphate) and other deposition sources have the characteristics of fluidity, and the deposited inorganic transparent material is naturally grown into a microlens structure.

[0141] Furthermore, at the stage of exposing the N-type ohmic contact layer of the pixel unit through step S25, the following steps can also be performed: targeting the groove structure of the insulating layer portion between two adjacent pixel units, and subsequently depositing a transparent conductive film on the groove structure to construct a second cathode connection structure.

[0142] Specifically, Figure 6 , Figure 7 As shown, a transparent conductive film can be deposited on the groove structure by sputtering, evaporation, etc., so as to form a second cathode connection structure 42 embedded between two adjacent pixel units, and the second cathode connection structure 42 is connected to the first cathode connection structure 41 to enhance the electrical characteristics of the common cathode.

[0143] The trench structure may be prepared by etching the insulating layer, or may be naturally formed by the shape of the insulating layer during the filling process of the insulating layer, and the present application does not impose any limitation on this.

[0144] In summary, in the preparation method of the micro display device provided in the embodiment of the present application, the driving wafer and the display module in the micro display device are bonded and integrated through a bonding metal layer. Due to the physical characteristics, a metal fence is inevitably formed in the process of ion beam etching the bonding metal layer. This metal fence is fully utilized to form an optical resonant cavity for the pixel unit in the display module. There is no need to perform a fence elimination process, which simplifies the overall process flow and greatly improves the process stability, production efficiency and production capacity. At the same time, the formation of an optical resonant cavity can also improve the brightness of the micro display device.

[0145] Furthermore, the side walls of the metal fence are in contact with the side walls of the bonding metal layer and the P-type ohmic contact layer in the pixel unit, and are spaced apart from the side walls of the compound semiconductor layer and the N-type ohmic contact layer. An insulating layer is filled between the metal fence and the pixel unit to avoid a short circuit between the P and N poles of each pixel unit, thereby minimizing the pixel spacing, maximizing the pixel light-emitting area, improving the pixel density, and increasing the resolution of the microdisplay device.

[0146] All the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention, that is, any multiple embodiments can be combined to meet the needs of different application scenarios. They are all within the protection scope of this application and will not be described one by one here.

[0147] It should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A micro display device with a metal fence, characterized in that: The micro display device comprises: A driving wafer, wherein the driving wafer includes an anode contact; A display module integrated with the driving wafer through a bonding metal layer, wherein the display module includes a pixel unit corresponding to the anode contact and a metal fence surrounding the pixel unit, wherein the metal fence is a fence-style structure generated during ion beam etching of the bonding metal layer; The metal fence forms a cylindrical optical resonant cavity for the pixel unit, and the optical resonant cavity is used to reflect the light waves emitted by the pixel unit back and forth therein to provide optical positive feedback.

2. The micro display device according to claim 1, characterized in that: The pixel unit at least includes: the bonding metal layer, the P-type ohmic contact layer, the compound semiconductor layer and the N-type ohmic contact layer which are vertically stacked in sequence in a direction away from the driving wafer; The bottom of the metal fence is connected to a side of the driving wafer close to the display module; The sidewall of the metal fence contacts the sidewalls of the bonding metal layer and the P-type ohmic contact layer, and is spaced apart from the sidewalls of the compound semiconductor layer and the N-type ohmic contact layer.

3. The micro display device according to claim 2, characterized in that: The top height of the metal fence is not lower than the top height of the compound semiconductor layer.

4. The micro display device according to claim 2, characterized in that: The display module also includes: an insulating layer, wherein the insulating layer is filled in the blank space of the display module; A common cathode includes: a first cathode connection structure, the first cathode connection structure is covered on a side surface of the insulating layer away from the driving wafer, and is connected to the N-type ohmic contact layer.

5. The micro display device according to claim 4, characterized in that: The common cathode further includes: a second cathode connection structure, which is embedded in the insulating layer between two adjacent pixel units, and one end of the second cathode connection structure away from the driving wafer is connected to the first cathode connection structure.

6. The micro display device according to claim 4, characterized in that: The top of the insulating layer is flush with the top of the N-type ohmic contact layer, and the first cathode connection structure horizontally covers the top of the insulating layer and the N-type ohmic contact layer; or, The top of the insulating layer is higher than the top of the N-type ohmic contact layer, and the height of the portion of the first cathode connection structure covering the top of the insulating layer is higher than the height of the portion of the first cathode connection structure covering the top of the N-type ohmic contact layer; or, The insulating layer is adhered to and covered on the side wall of the pixel unit, and the first cathode connection structure covers the outer surface of the insulating layer and the top of the N-type ohmic contact layer.

7. The micro display device according to claim 4, characterized in that: The common cathode adopts a transparent conductive film.

8. The micro display device according to claim 4, characterized in that: A microlens structure is disposed on a surface of the first cathode connection structure on a side away from the driving wafer, and a projection of the metal fence on the driving wafer is within a projection of the microlens structure on the driving wafer.

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