HEMT transistor and device

Abstract

The utility model relates to an HEMT transistor and an apparatus. The HEMT transistor includes: a semiconductor channel layer; the semiconductor barrier layer is positioned on the semiconductor channel layer and is in contact with the semiconductor channel layer; the semiconductor grid electrode is arranged on a first surface, opposite to the semiconductor channel layer, of the semiconductor barrier layer and is in contact with the first surface, the grid electrode comprises an upper part and a central part, and the upper part and the central part comprise a P-type doping element; and the upper portion includes oxygen atoms that form a PN junction at an interface between the central portion and the upper portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to French Patent Application No. 2301105, filed on February 6, 2023, entitled “Transistor HEMT,” which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to the field of transistors, and more particularly to the field of high electron mobility transistors, also known as HEMTs. Background Art

[0004] HEMT transistors rely on a heterojunction with a two-dimensional electron gas (also known as 2DEG) formed on its surface.

[0005] There exists a need for improved HEMT transistors and methods of making the same. Utility Model Content

[0006] To achieve this,

[0007] An embodiment provides a HEMT transistor, comprising:

[0008] Semiconductor channel layer;

[0009] a semiconductor barrier layer located on the semiconductor channel layer and in contact with the semiconductor channel layer; and

[0010] a semiconductor gate disposed on a first surface of the semiconductor barrier layer opposite to the semiconductor channel layer and in contact with the first surface,

[0011] The gate includes an upper portion and a central portion, the upper portion and the central portion include a P-type doping element, and the upper portion includes oxygen atoms that compensate for the P-type doping to define a PN junction at an interface between the central portion and the upper portion.

[0012] According to an embodiment, the gate includes a peripheral portion including a P-type doping element and including oxygen atoms compensating for the P-type doping.

[0013] According to an embodiment, the transistor includes a passivation layer extending over a first surface of the first semiconductor layer and a side surface of the gate and a peripheral portion of a surface of the gate opposite to the first semiconductor layer.

[0014] According to an embodiment, the first passivation layer is made of aluminum oxide.

[0015] According to an embodiment, the first semiconductor layer is based on gallium nitride.

[0016] According to an embodiment, the first semiconductor layer is made of aluminum gallium nitride.

[0017] According to an embodiment, the first semiconductor layer comprises an aluminum content which decreases starting from its first surface.

[0018] According to an embodiment, the transistor includes a second semiconductor layer in contact with a second surface of the first semiconductor layer opposite to the first surface.

[0019] According to an embodiment, the second semiconductor layer is made of gallium nitride.

[0020] According to one embodiment, the semiconductor gate is made of gallium nitride.

[0021] Another embodiment also provides a device, comprising: a conductive layer; a semiconductor layer having a first surface in contact with the conductive layer and a second surface opposite to the first surface of the semiconductor layer; and a gate having a first surface coupled to the second surface of the semiconductor layer, a second surface opposite to the first surface of the gate, and a first side wall transverse to the first surface and the second surface of the gate, the gate comprising: a central portion having a first conductivity type; an outer layer having a second conductivity type opposite to the first conductivity type at the second surface of the gate; and a peripheral layer having the second conductivity type at the first side wall of the gate.

[0022] According to an embodiment, the gate has a P-type doping, and the outer layer and the peripheral layer have an N-type doping.

[0023] According to an embodiment, the device includes a PN junction at an interface between a central portion of the gate and peripheral and outer layers of the gate.

[0024] According to an embodiment, the device includes a passivation layer located on the second surface of the semiconductor layer, the peripheral layer of the gate, and the outer layer of the gate.

[0025] According to an embodiment, the device comprises a gap in the passivation layer on an outer layer of the gate and a gate contact metallization directly coupled to the gate through the gap.

[0026] According to an embodiment, the device comprises an insulating layer which completely covers the passivation layer and comprises a portion between the gate contact metallization and an outer layer of the gate.

[0027] Another embodiment provides a power conversion or matching circuit comprising at least one transistor as described. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above features and advantages as well as other features and advantages will be described in detail in the remainder of the present disclosure in the context of specific embodiments given by way of example and not limitation with reference to the accompanying drawings, in which:

[0029] Figure 1 is a partially simplified cross-sectional view of an example of a HEMT transistor;

[0030] Figure 2 is a partial simplified cross-sectional view of a HEMT transistor according to the first embodiment.

[0031] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F It is shown Figure 2 2 is a cross-sectional view of an example of a step of a method for manufacturing a HEMT transistor shown in FIG.

[0032] Figure 4 is a partial simplified cross-sectional view of a HEMT transistor according to a second embodiment; and

[0033] Figure 5 is a partial simplified cross-sectional view of a HEMT transistor according to a third embodiment. DETAILED DESCRIPTION

[0034] Similar features are denoted by similar reference numerals in the various figures. In particular, common structural and / or functional features between various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0035] For the sake of clarity, only the steps and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, the applications that the described HEMT transistors may have are not described in detail, and the embodiments are consistent with the usual applications of HEMT transistors. More specifically, the field of HEMT transistors capable of withstanding relatively high voltages in the off state (e.g., voltages of about 100 to 650 volts) is considered herein. The described transistors can be used, for example, in various power conversion or matching circuits, such as industrial equipment, display or lighting devices, telecommunication equipment, automotive devices, etc.

[0036] Unless otherwise specified, when two elements are referred to as being connected together, this means a direct connection without any intermediate elements except conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0037] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as terms "above", "below", "upper", "lower", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation of the figures.

[0038] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, and preferably within 5%.

[0039] Figure 1 is a partially simplified cross-sectional view of an example of a HEMT transistor 11 .

[0040] The HEMT transistor 11 includes a first semiconductor layer 13, referred to as a barrier layer, arranged on a second conductive layer 23, referred to as a channel layer. The semiconductor layer 13 is in contact with the upper surface of the conductive layer 23, for example, through its lower surface. As an example, a stack including the semiconductor layer 13 and the semiconductor layer 23 is located on a substrate 21. The semiconductor layer 23 is in contact with the upper surface of the substrate 21, for example, through its lower surface. The interface between the semiconductor layer 13 and the semiconductor layer 23 defines a heterojunction, at the surface of which a two-dimensional electron gas 2DEG, also referred to as an electron channel, is formed.

[0041] The semiconductor layers 13 and 23 are made of, for example, III-V type semiconductor materials (for example, III-V type semiconductor materials based on gallium nitride (GaN)). The semiconductor layer 13 is made of, for example, aluminum gallium nitride (AlGaN). The semiconductor layer 13 is made of, for example, gallium nitride (GaN).

[0042] As an example, the substrate 21 is made of a semiconductor material. The substrate 21 is made of, for example, silicon or silicon carbide. As a variant, the substrate 21 is made of aluminum nitride. The substrate 21 includes, for example, a buffer layer made of, for example, gallium nitride, which is not shown in detail in the drawings, on its upper surface side. The buffer layer is in contact with the lower surface of the semiconductor layer 23, for example, through its upper surface.

[0043] The HEMT transistor 11 includes a gate 15 located on the upper surface of the semiconductor layer 13. The gate 15 is in contact with the upper surface of the semiconductor layer 13, for example, through its lower surface.

[0044] The gate 15 is made of, for example, a semiconductor material, such as a III-V type semiconductor material, such as gallium nitride. The gate 15 includes a P-type doping element, such as a magnesium atom. As an example, the gate 15 has a thickness in the range of 20 nm to 200 nm, such as in the range of 80 nm to 120 nm, such as a thickness of about 100 nm.

[0045] As an example, the HEMT transistor 11 further comprises a source contact metallization 29 and a drain contact metallization 31. As an example, the contact metallizations 29 and 31 are based on titanium, titanium nitride and / or an alloy of aluminum and copper. The source contact metallization 29 and the drain contact metallization 31, for example, each define an ohmic contact with the semiconductor layer 13. For example, on either side of the gate 15, the contact metallizations 29 and 31 are located above and in contact with the semiconductor layer 13.

[0046] The HEMT transistor 11 further includes a passivation layer 17, which covers the side surfaces of the gate, a portion of the upper surface of the gate 15, and extends over a portion of the upper surface of the semiconductor layer 13 that is not covered by the gate 15. As an example, the passivation layer 17 is in contact with the upper surface of the semiconductor layer 13 through its lower surface. The passivation layer 17 is also in contact with the side surfaces of the gate 15, for example. Figure 1 In the embodiment of FIG. 4 , the passivation layer 17 extends laterally between the source and drain contact metallizations 29 and 31 .

[0047] The passivation layer 17 has, for example, a thickness in the range of 2 nm to 20 nm, for example, in the range of 2 nm to 10 nm, for example, a thickness of about 5 nm. The passivation layer 17 is, for example, made of a dielectric material, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum nitride (AlN) or hafnium oxide (HfO2).

[0048] For example, the gate 15 has a gate contact metallization 27 thereon.

[0049] As an example, the gate contact metallization 27 is in contact with the upper surface of the gate 15 via its lower surface. The gate contact metallization 27 then extends through the layer 17 which covers only the periphery of the upper surface of the gate 15.

[0050] As an example, the gate contact metallization 27 is based on titanium nitride and / or titanium, and / or tantalum, and / or an alloy of tungsten and tantalum, and / or an alloy of tungsten and titanium, and / or an alloy of aluminum and copper.

[0051] In this example, the metallization 27 defines a Schottky contact with the semiconductor gate 15. The semiconductor gate 15 and the metallization 27 define a Schottky diode, the anode of which corresponds to the semiconductor gate 15 and the cathode of which corresponds to the metallization 27.

[0052] The HEMT transistor 11 comprises, for example, a multi-level insulating layer, within which and, for example, on which a metallization is formed.

[0053] As an example, the HEMT transistor 11 includes an insulating layer 33 on the upper surface of the passivation layer 17 and in contact with the upper surface of the passivation layer 17. As an example, the insulating layer 33 covers the entire surface of the passivation layer 17. The insulating layer 33 is opened, for example, in front of the central portion of the gate 15 to be passed through by the gate contact metallization 27. The insulating layer 33 is made of a dielectric material, for example, an oxide (for example, silicon dioxide (SiO2)) or silicon nitride (Si3N4).

[0054] As an example, the HEMT transistor 11 comprises a metal region 37 extending over a portion of the surface of the insulating layer 33. As an example, the metal region 37 is based on titanium nitride and / or titanium, and / or tantalum, and / or an alloy of tungsten and tantalum, and / or an alloy of tungsten and titanium, and / or an alloy of aluminum and copper. The metal region 37 is, for example, made of the same material as the gate contact metallization 27.

[0055] The HEMT transistor 11 may include a second insulating layer 39 covering the entire structure except for the source contact metallization 29 and the drain contact metallization 31. The second insulating layer 39 is made of the same material as the insulating layer 33, for example.

[0056] The metal region 37 has, for example, a modified structure located on the drain side ( Figure 1 The metal region 37 has the function of lowering the peak value of the critical electric field and thus increasing the avalanche voltage. The metal region 37 is, for example, called a field plate.

[0057] As an example, the source contact metallization 29 extends further over the upper surface of the insulating layer 39 towards the drain contact metallization 31 without reaching the drain contact metallization 31 .

[0058] exist Figure 1 In a transistor of the type, the channel 2DEG is, for example, normally off, i.e., it is interrupted below the gate 15, which prevents current from flowing between the source and drain of the transistor. The transistor is said to be in a cut-off state. The channel can be restored (i.e., turned on) by biasing the gate 15. In this case, a current can be established between the source and drain of the transistor. The described embodiments can also be applied to normally on transistors.

[0059] The presence of passivation layer 17 allows protecting the upper surface of semiconductor layer 13, on which dangling bonds may exist and may produce leakage current and / or a reduction in transistor breakdown voltage. Passivation layer 17 fills these bonds to make the surface of semiconductor layer 13 electrically inert.

[0060] The passivation layer 17 also makes it possible to protect the semiconductor layer 13 from oxidation and improve its surface condition, to which the 2DEG channel is sensitive.

[0061] Although the passivation layer 17 plays an important role for the quality and lifetime of the transistor, its presence may lead to the accumulation of electrons along the sides of the gate 15 below the passivation layer 17. This phenomenon is enhanced by damage to the sides of the gate, for example, caused by etching of the gate 15. This leads to leakage currents flowing through the sides of the gate between the gate contact metallization 27 and the source and / or drain metallization 29 and / or 31.

[0062] In order to reduce this phenomenon, the doping of the upper part of the semiconductor gate 15 can be modified to obtain an N-type doping in this upper part, thereby defining a PN junction between this upper part and the lower part of the gate. The contact metallization 27 then forms an ohmic contact with the upper N-type part of the semiconductor gate 15. Figure 1 In the example of FIG. 2 , the Schottky diode formed between the semiconductor gate 15 and the metallization 27 is replaced by a PN diode formed between the lower and upper parts of the semiconductor gate 15 .

[0063] Figure 2 is a partial simplified cross-sectional view of the HEMT transistor 41 according to the first embodiment.

[0064] More specifically, Figure 2 The diagram shows Figure 1 A HEMT transistor 41 is similar to the transistor 11 shown in FIG. 1 , except that the gate 15 of the transistor 41 includes oxygen atoms in an upper portion 151 and a peripheral portion 155 of the gate, which compensates for the P-type doping to obtain an N-type doping, thereby defining a PN junction at the interface between the central portion 153 of the gate and the upper and peripheral portions 151 and 155.

[0065] As an example, the upper N-type portion 151 has a thickness in the range of 10nm to 100nm, such as in the range of 30nm to 70nm, such as a thickness of about 50nm. As an example, the peripheral N-type portion 155 has a thickness in the range of 10nm to 100nm, such as in the range of 30nm to 70nm, such as a thickness of about 50nm.

[0066] As an example, the gate 15 is made of aluminum gallium nitride. As an example, the gate 15 is made of aluminum gallium nitride, and its chemical formula corresponds to Al x Ga x-1 N, where x is a positive integer. The gate 15 includes a P-type doping element, such as magnesium atoms.

[0067] As an example, the semiconductor layer 13 comprises an inhomogeneous aluminum content over its entire thickness. The layer 13 has, for example, an aluminum content that increases starting from its lower surface, ie its aluminum content near the gate 15 is greater than its aluminum content near the semiconductor layer 23 .

[0068] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F It is a graphic manufacturing Figure 2 4 is a cross-sectional view of an example of steps of a method of making a HEMT transistor 41.

[0069] Figure 3A The initial structure is shown, which includes a substrate 21, a second semiconductor layer 23, and a first semiconductor layer 13 in order from the bottom surface of the structure. The initial structure also includes a gate layer 15, in which the gate 15 of the transistor 41 will be formed. Figure 3A In the initial structure shown in , layers 23, 13 and 15 each extend continuously over the entire upper surface of substrate 21 with a substantially uniform thickness.

[0070] By way of example, a gate layer 15 is formed on the upper surface of the layer 13 by a vapor deposition method, for example a metal organic vapor phase epitaxy method also known as a metal organic chemical vapor deposition or MOCVD method. By way of example, the deposition of the gate 15 is carried out under at least a partial vacuum. The gate layer 15 is doped, for example, during its deposition. As a variant, the gate layer 15 is doped after its deposition by a dopant implantation step. In this example, the gate layer 15 is doped, for example, of P-type with magnesium atoms.

[0071] Figure 3B The structure obtained at the end of a first step of compensation of the doping of gate layer 15 with oxygen atoms in its upper part is illustrated.

[0072] More specifically, during this step, the Figure 3A The structure shown in FIG. 1 is subjected to oxygen annealing (and, for example, under nitrogen) so that the P-type doping of the upper part of the gate layer 15 is compensated with oxygen atoms. Then, the upper part of the gate layer 15 changes the doping type, which then involves doping compensation. Here, the upper part of the gate layer 15 is changed from P-type doping to N-type doping.

[0073] In fact, the oxygen annealing makes it possible to unbind the hydrogen atoms bound to the doping elements (e.g. magnesium atoms) present in the gate layer in a first phase, for example under dinitrogen. In a second phase, the oxygen annealing allows the implantation (also for example under dinitrogen) of oxygen atoms as N-type doping elements in the structure, and more specifically in the upper part of the gate layer 15.

[0074] As an example, the oxygen annealing comprises an oxygen content in the range of 1% to 20%, such as in the range of 2% to 10%, such as about 5%. The oxygen annealing is performed at a temperature in the range of 600°C to 1000°C, such as in the range of 750°C to 900°C, such as about 820°C.

[0075] At the end of this step, the gate layer 15 comprises an upper portion 151 and a central portion 153 , the interface of which defines a PN junction.

[0076] Figure 3C The structure obtained at the end of the first step of etching the gate layer 15 is illustrated.

[0077] More specifically, during this step, in a first step, Figure 3B A mask layer 25 is formed on and, for example, in contact with the structure shown in FIG. The mask layer 25 is, for example, made of a material that resists etching described below, for example, made of an oxide, for example, made of tetraethyl orthosilicate or TEOS. As an example, the mask layer 25 is not made of a resin. The mask layer 25 has, for example, a thickness in the range of 50 nm to 200 nm, for example, a thickness of about 100 nm. As an example, the mask layer 25 is formed so that it covers the position of the future gate 15. Figure 3B The structure shown in .

[0078] During this step, in a second phase, the gate layer 15 is etched through the mask layer 25, for example by a plasma etching method, for example by a chlorine-based plasma etching method (eg by boron trichloride (BCl3) and chlorine (Cl2) plasma etching).

[0079] During this step, the gate layer 15, and more precisely the portion of the gate layer 15 that is located outside the position facing the mask layer 25, is partially etched, i.e., etched only over a portion of its thickness. As an example, during this step, the gate layer 15 is etched by 50% to 90% of its thickness, for example 80% of its thickness.

[0080] At the end of this step, the gate layer 15 remains at the locations faced by the mask layer 25 and only remains across a portion of its thickness outside of the locations faced by the mask layer 25 .

[0081] Figure 3D The structure obtained at the end of the second step of compensating the doping of gate layer 15 with oxygen atoms is illustrated.

[0082] More specifically, during this step, the Figure 3B Perform similarly to the description Figure 3C. For example, this step is performed when the mask layer 25 is still present on the surface of the structure. Thus, the side of the portion of the gate layer 15 located below the mask layer 25 and the upper portion of the remaining portion of the gate layer 15 outside the position facing the mask layer 25 are compensated with oxygen atoms.

[0083] At the end of this step, the gate layer 15 comprises an N-doped upper portion 151 and a peripheral portion 155 and a P-doped central portion 153. As an example, the thickness of the peripheral portion 155 of the gate layer 15 is in the range of 10 to 100 nm, for example in the range of 30 nm to 70 nm, for example about 50 nm.

[0084] During this step, leaving a portion of the gate layer 15 outside the position facing the mask layer 25 makes it possible to protect the semiconductor layer 13 and to compensate for the doping of the gate layer 15 without modifying the doping of the semiconductor layer 13 .

[0085] Figure 3E The structure obtained at the end of the second step of etching the gate layer 15 through the mask layer 25 to form the gate 15 is illustrated.

[0086] During this step, for example, the remaining portion of the gate layer 15 outside the position facing the mask layer 25 is etched, for example by a plasma etching method, for example by a chlorine-based plasma etching method (for example, by a plasma etching method based on chlorine (Cl2) and oxygen (O2) or by a plasma etching method based on boron trichloride (BCl3) and sulfur hexafluoride (SF6)).

[0087] As an example, the etching step is performed until the upper surface of the semiconductor layer 13 is exposed, and only the gate layer 15 remains in front of the mask layer, so as to form the gate 15 of the transistor.

[0088] This etching step is for example followed by a step of removing the mask layer 25. By way of example, the removal of the etching mask is performed by means of hydrogen fluoride (HF).

[0089] Figure 3F The diagram shows Figure 3E The structure obtained at the end of the step of forming the passivation layer 17 , the insulating layer 33 , the metallization 27 and the region 37 on the upper surface of the structure shown in .

[0090] During this step, in a first stage, a passivation layer 17 is formed in a full-wafer manner so that it covers Figure 3E The entire upper surface of the structure shown in .

[0091] The passivation layer 17 is formed, for example, to contact the upper surface of the semiconductor layer 13 and the side and upper surface of the gate 15. The passivation layer 17 is formed, for example, by a thin layer deposition method (e.g., by ALD). As an example, the deposition method of the passivation layer 17 is plasma or thermally enhanced. As an example, the passivation layer 17 has a thickness in the range of 1 nm to 10 nm, for example in the range of 3 nm to 7 nm, for example, a thickness of about 5 nm.

[0092] In the second stage, during this step, the insulating layer 33 is formed in a full-wafer manner so that it covers the entire upper surface of the passivation layer 17. The insulating layer 33 is, for example, formed in contact with the passivation layer 17. The insulating layer 33 is, for example, formed by plasma enhanced chemical vapor deposition or PECVD. At the end of this step, the insulating layer 33 has a thickness in the range of, for example, 150 nm to 400 nm, for example, in the range of 200 nm to 350 nm, for example, a thickness of about 300 nm.

[0093] As an example, the step of depositing the passivation layer 17 and the insulating layer 33 may be preceded by Figure 3E One or more steps in the preparation of the surface of the structure shown. Figure 3E Preparation of the surface of the structure shown in may comprise cleaning, for example including chemical cleaning with the aid of an acid, such as hydrogen chloride (HCl) or hydrogen fluoride (HF). Figure 3E Preparation of the surface of the structure shown in may also include cleaning including surface oxidation, for example. Thus, the passivation layer 17 will be formed in contact with the oxide film, which itself is formed in contact with the upper surface of the layer 13 .

[0094] During this step, in a third phase, the passivation layer 17 and the insulating layer 33 facing the central portion of the upper surface of the gate 15 are removed, and the gate contact metallization 27 is formed in the opening formed. As an example, this step includes removing the layer 33 and then removing the layer 17. As an example, the removal of the layer 33 is performed by, for example, a fluorine-based, for example, carbon tetrafluoride (CF4)-based plasma etching. As an example, the removal of the layer 17 is performed by, for example, a chlorine-based, for example, boron trichloride (BCl3)-based plasma etching. In this example, the layer 17 is etched to expose the upper surface of the gate 15.

[0095] After the above etching, for example, a cleaning step of the upper surface of the structure is performed to remove, for example, residues from the mask layer 25 and impurities from the etching of the gate layer 15. The cleaning of the structure includes, for example, a step of stripping by oxygen and nitrogen (N2) plasma. The cleaning of the structure may also include a step of removing organic residues by means of a solvent.

[0096] During this step, a gate contact metallization 27 is formed, for example, in an opening formed in the layers 17 and 33 facing the central portion of the gate 15. By way of example, the gate contact metallization 27 is formed over and in contact with the upper surface of the gate 15, and more precisely over and in contact with the upper portion 151 of the gate 15.

[0097] As an example, during this step a region 37 is further formed on a portion of the surface of the first insulating layer 33. The gate contact metallization 27 and the region 37 are formed, for example, by depositing one or more layers made of metallic material followed by an etching step.

[0098] As an example, the step of forming the gate contact metallization 27 and the region 37 may be preceded by a step of preparation of the surface of the structure, for example comprising chemical cleaning by means of an acid, for example hydrogen chloride (HCl).

[0099] At the end of this step, for example Figure 3F An insulating layer 39 is formed on the upper surface of the structure shown in FIG. During this step, the insulating layer 39 is formed, for example, in a full-wafer manner so that it covers Figure 3F The entire upper surface of the structure shown in FIG. 1 , i.e. the upper surface and the side surfaces of the gate contact metallization 27 and the region 37 and a portion of the layer 33. The insulating layer 39 is for example formed by contacting with the Figure 3F The insulating layer 39 is formed in the same way as described for the formation of the layer 33. At the end of this step, the insulating layer 39 has a thickness, for example, ranging from 150 nm to 400 nm, for example ranging from 200 nm to 350 nm, for example of about 300 nm.

[0100] Finally, for example, ohmic contacts are formed, and more specifically source contact metallization 29 and drain contact metallization 31, to form Figure 2 The structure shown in .

[0101] For this purpose, openings for accommodating the source and drain contact metallizations 29 and 31 are first created in the layers 17, 33 and 39. The openings are formed, for example, by a plasma etching method, for example a plasma etching method based on fluorine, for example based on carbon tetrafluoride (CF4). The above etching is, for example, selective and does not etch the gallium nitride semiconductor layer 13. Therefore, the etching of the layers 17, 33 and 39 stops when the upper surface of the layer 13 is exposed. The step of forming the openings intended to accommodate the contact metallizations 29 and 31 is followed, for example, by a step of cleaning the upper surface of the structure, for example similar to the steps described above for the gate contact metallization 27 and the region 37. As an example, a step of surface preparation of the upper surface of the layer 13 in the openings may be provided to accommodate the contact metallizations 29 and 31. This step comprises, for example, chemical cleaning with the aid of an acid, for example hydrogen chloride (HCl).

[0102] In a second phase, for example, a source contact metallization 29 and a drain contact metallization 31 are formed in the previously formed openings. The metallizations 29, 31 and the region 47 are formed, for example, by depositing one or more layers made of metallic material over the entire upper surface of the structure (here the upper surfaces of the layers 13 and 39), followed by an etching step.

[0103] Figure 4 is a partial simplified cross-sectional view of a HEMT transistor 43 according to the second embodiment.

[0104] Figure 4 The transistor 43 shown in FIG. 1 is similar to Figure 2 The HEMT transistor 41 shown in FIG. 1 is different in that the peripheral portion of the gate 15 is not N-type doped. The method for manufacturing the transistor 43 is different from the method for manufacturing the transistor 41 in that the second compensation step is omitted in the method for manufacturing the transistor 43. In addition, Figure 4 The transistor 43 shown in FIG. 1 is similar to Figure 2 The HEMT transistor 41 shown in FIG. 1 is different in that Figure 3C The etching step described is a complete etching, and the step of continuing to etch the gate layer 15 is omitted.

[0105] Thus, in the method for manufacturing transistor 43, etching of gate layer 15 is performed in a single step, i.e., during a single etching step, gate layer 15 is removed over its entire thickness except where mask layer 25 faces. The method for manufacturing transistor 43 comprises, at the end of the step of etching gate layer 15 to form gate 15, a step of forming layers 17 and 33, similar to the step already combined. Figure 3F Describe the steps.

[0106] More specifically, in this example, transistor 43 differs from transistor 41 in that gate 15 does not include an N-type doped peripheral portion 155 .

[0107] Figure 5 is a partial simplified cross-sectional view of a HEMT transistor 45 according to the third embodiment.

[0108] Figure 5 The transistor 45 shown in FIG. 4 is similar to Figure 2 , except that in the method of manufacturing transistor 45, source contact metallization 29 and drain contact metallization 31 are already formed before forming gate contact metallization 27, whereas in the method of manufacturing transistor 41, source contact metallization 29 and drain contact metallization 31 are formed after forming gate contact metallization 27.

[0109] More specifically, in this example, transistor 45 differs from transistor 41 in that gate contact metallization 27 crosses layer 39 , and in that layer 39 covers contact metallizations 29 and 31 .

[0110] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, the previously described Figure 4 and Figure 5 The second embodiment and the third embodiment described in can be combined.

[0111] Furthermore, although an example of an embodiment in which the transistor gate 15 is in contact with the upper surface of the upper semiconductor layer 13 has been described above, as a variation, the gate 15 may be separated from the semiconductor layer 13 by a gate insulating layer.

[0112] Furthermore, the embodiments are not limited to the examples of numerical values ​​nor the examples of materials mentioned in the present disclosure.

[0113] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0114] A method of forming a HEMT transistor (41) can be summarized as comprising the following sequential steps: a) providing a stack comprising a semiconductor channel layer (23), a semiconductor barrier layer (13) above and in contact with the semiconductor channel layer (23), and a semiconductor gate layer (15) arranged above and in contact with the semiconductor barrier layer (13), the semiconductor gate layer (15) comprising a P-type doping element; and b) compensating the P-type doping with oxygen atoms in an upper portion (151) of the semiconductor gate layer (15) by oxygen annealing to define a PN junction at an interface between the upper portion (151) and a central portion (153) of the semiconductor gate layer (15).

[0115] The method may include the step c) of etching the semiconductor gate layer (15).

[0116] The etching of step c) may be performed after step b).

[0117] The etching of step c) can be partial etching, retaining a portion of the thickness of the semiconductor gate layer (15) at the end of the etching step; and the etching of step c) can be followed by another step of compensating P-type doping with oxygen atoms in the peripheral portion of the etched semiconductor layer (15), and another etching step that enables removal of the remaining portion of the semiconductor gate layer (15) at the end of the etching step of step c).

[0118] The HEMT transistor (11) can be summarized as comprising: a semiconductor channel layer (23); a semiconductor barrier layer (13) located above and in contact with the semiconductor channel layer (23); and a semiconductor gate (15) arranged above and in contact with a first surface of the semiconductor barrier layer (13) opposite to the semiconductor channel layer (23), wherein the gate (15) comprises an upper portion (151) and a central portion (153), the upper portion (151) and the central portion (153) comprising a P-type doping element, and the upper portion (151) comprising oxygen atoms compensating for the P-type doping to define a PN junction at an interface between the central portion (153) and the upper portion (151).

[0119] The gate (15) may include a peripheral portion (155) including a P-type doping element and including oxygen atoms compensating for the P-type doping.

[0120] The transistor may include a passivation layer (17) extending on a first surface of the first semiconductor layer (13) and a side surface of the gate (15) and a peripheral portion of a surface of the gate (15) opposite to the first semiconductor layer (13).

[0121] The first passivation layer (17) may be made of aluminum oxide.

[0122] The first semiconductor layer (13) may be based on gallium nitride.

[0123] The first semiconductor layer (13) may be made of aluminum gallium nitride.

[0124] The first semiconductor layer may include an aluminum content that decreases from a first surface thereof.

[0125] The transistor may include a second semiconductor layer (23) in contact with a second surface of the first semiconductor layer (13) opposite to the first surface.

[0126] The second semiconductor layer (23) may be made of gallium nitride.

[0127] The semiconductor gate (15) may be made of gallium nitride.

[0128] A power conversion or matching circuit can be summarized as including at least one transistor.

[0129] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications and publications to provide further embodiments.

[0130] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalent forms granted by these claims. Therefore, the claims are not limited by the present disclosure.

Claims

1. A HEMT transistor, characterized in that: include: Semiconductor channel layer; A semiconductor barrier layer, located on the semiconductor channel layer and in contact with the semiconductor channel layer; as well as a semiconductor gate disposed on a first surface of the semiconductor barrier layer opposite to the semiconductor channel layer and in contact with the first surface, The gate includes a central portion having a first conductivity type and an upper portion having a second conductivity type opposite to the first conductivity type, the upper portion and the central portion include P-type doping elements, and the upper portion contains oxygen atoms that form a PN junction at an interface between the central portion and the upper portion.

2. The HEMT transistor according to claim 1, characterized in that The gate includes a peripheral portion, the peripheral portion includes a P-type doping element and includes oxygen atoms that compensate for the P-type doping.

3. The HEMT transistor according to claim 1, wherein: A passivation layer is included, the passivation layer extending over the first surface of the semiconductor barrier layer and the side surface of the gate and the peripheral portion of the surface of the gate opposite to the semiconductor barrier layer.

4. The HEMT transistor according to claim 1, wherein: A second semiconductor layer is included that is in contact with a second surface of the semiconductor barrier layer opposite to the first surface.

5. A device, characterized in that: include: Conductive layer; a semiconductor layer including a semiconductor barrier layer and having a first surface in contact with the conductive layer and a second surface opposite to the first surface of the semiconductor layer; as well as A gate having a first surface coupled to the second surface of the semiconductor layer, a second surface opposite to the first surface of the gate, and a first sidewall transverse to the first surface and the second surface of the gate, the gate comprising: a central portion having a first conductivity type; having an outer layer of a second conductivity type opposite to the first conductivity type at a second surface of the gate; and A peripheral layer of the second conductivity type is provided at the first side wall of the gate.

6. The device according to claim 5, characterized in that A PN junction is included at an interface between a central portion of the gate and a peripheral layer and an outer layer of the gate.

7. The device according to claim 5, characterized in that The invention comprises a passivation layer located on the second surface of the semiconductor layer, the peripheral layer of the gate and the outer layer of the gate.

8. The device according to claim 7, characterized in that A gap is included in the passivation layer on an outer layer of the gate and a gate contact metallization is directly coupled to the gate through the gap.

9. The device according to claim 8, characterized in that An insulating layer is included that completely covers the passivation layer and includes a portion between the gate contact metallization and an outer layer of the gate.

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