Storage and calculation integrated comparison operation unit based on ferroelectric transistor and comparator circuit

Abstract

The utility model discloses a storage and calculation integrated comparison operation unit based on a ferroelectric transistor and a comparator circuit, the storage and calculation integrated comparison operation unit comprises an input module, an operation module and an output module, the operation module comprises a ferroelectric transistor, the on-off state of the ferroelectric transistor is maintained or changed according to a received voltage signal, and the output module is used for outputting the voltage signal. Performing a non-volatile smaller comparison operation; the comparator circuit comprises two storage and calculation integrated comparison operation units, an interlocking unit and a low-order suppression unit, the interlocking unit is used for obtaining smaller, equal and larger comparison results, and the low-order suppression unit is used for suppressing redundant comparison; the storage and calculation integrated comparator circuit has the advantages that the storage and calculation integrated comparison operation unit facing the edge end logic operation library is developed, the comparison result can overcome the influence of power failure, logic cascade can be realized without an additional conversion circuit, the storage and calculation integrated comparator circuit realized by combining the combinational logic gate has a low-order suppression function, the power consumption overhead can be further reduced, and the power consumption is reduced. And the reliability of edge end operation is improved.

Description

Technical Field

[0001] The utility model belongs to the field of digital circuits, and relates to a storage-computation integrated circuit design technology, in particular to a storage-computation integrated comparison operation unit and a comparator circuit based on a ferroelectric transistor (FeFET, ferroelectric field effect transistor). Background Art

[0002] In IoT edge chips powered by ambient energy harvesting technology, the logic operation process is easily affected by unstable power supply. In the event of power failure, data cannot be saved in time, which will affect the continuity of calculation and data security. In order to overcome the impact of power failure, the storage and computing integrated circuit that supports on-site backup and data recovery built with emerging non-volatile memory devices is considered to be a promising solution. Among many non-volatile memory devices, ferroelectric transistors have received special attention due to their low power consumption, high switching ratio, and compatibility with existing CMOS processes. Existing IoT edge chips have used the storage capacity of ferroelectric transistors to prepare storage and computing integrated triggers that can recover from power failure. However, in terms of logical operations, there is a lack of effective development of the computing capabilities of ferroelectric transistors. Either ferroelectric transistors are used to replace the original MOS logic gates, and the operation results are difficult to recover from power failure; or the internal state of the ferroelectric transistor and the external voltage are used as the input logic variables. Although the operation results can be saved, the input logic variables are not in a uniform form, and additional conversion circuits are required to achieve logical cascading, which limits the logical cascading and increases power consumption. Therefore, the development of the IoT edge logic operation unit library is limited.

[0003] In digital systems, numerical comparators are a common and important integrated circuit component that is used to compare the size of two values ​​and output corresponding logic signals. Most existing numerical comparators use MOS logic gates to build combinational circuits to compare the size of two values, but combinational circuits do not have storage functions. Even if additional static latches are used to store the comparison results, the data cannot be effectively retained in a power-off environment. When the power is restored, the data involved in the calculation will not be the actual comparison result, affecting the accuracy of the calculation results.

[0004] How to simultaneously utilize the computing and storage capabilities of ferroelectric transistors to design a storage and computing integrated comparator suitable for IoT edge chips is an important step in expanding the IoT edge computing unit library and a key issue related to the practical development of IoT edge chips with unstable power supply. Summary of the invention

[0005] The technical problem to be solved by the utility model is to provide a storage-computation-in-one comparison operation unit and a comparator circuit based on a ferroelectric transistor for an edge chip of the Internet of Things whose logic operation process is easily affected by an unstable power supply, taking a comparator as an example. The utility model utilizes the principle of regulating the switching state of the gate and source voltage difference of the ferroelectric transistor to develop a storage-computation-in-one comparison operation unit under voltage signal input. The comparison result is stored in a non-volatile manner to overcome the influence of power failure, and logic cascading can be achieved without an additional conversion circuit. In addition, a storage-computation-in-one comparator circuit with a low-bit suppression function is realized in combination with a combinational logic gate. The low-bit suppression function further reduces the power consumption overhead and improves the reliability of edge logic operations.

[0006] The technical solution adopted by the utility model to solve the above technical problems is: a storage and calculation integrated comparison operation unit based on ferroelectric transistors, characterized by comprising:

[0007] An input module receives two voltage signals to be compared during the comparison operation and determines whether to transmit the two voltage signals to be compared to the operation module according to the unit operation control signal;

[0008] The operation module includes a ferroelectric transistor. Before the comparison operation starts, the gate and source of the ferroelectric transistor receive an initialization voltage signal respectively, so that the ferroelectric transistor is initialized to a conducting state, wherein the two initialization voltage signals are a pair of mutually inverted level signals; during the comparison operation, after the gate and source of the ferroelectric transistor receive the two voltage signals to be compared transmitted by the input module, the conducting state thereof is maintained or changed, thereby performing a less than comparison operation, and the comparison result is stored as the switch state of the ferroelectric transistor, thereby realizing a non-volatile storage-computation integrated comparison operation;

[0009] The output module establishes a voltage division path for the operation module, reads the comparison result stored in the operation module as a voltage signal and outputs it.

[0010] It is further defined that the input module has a first signal input terminal and a second signal input terminal, an operation control terminal, a first signal output terminal and a second signal output terminal, the operation module has a first signal input terminal and a second signal input terminal, a high power connection terminal, and a signal output terminal, the first signal input terminal of the operation module also serves as the first initialization terminal of the storage-computation-in-one comparison operation unit, and the second signal input terminal of the operation module also serves as the second initialization terminal of the storage-computation-in-one comparison operation unit, and the output module has a low power connection terminal, a signal transmission terminal, a signal input terminal, a signal output terminal, and a latch control terminal; the first initialization terminal and the second initialization terminal each receive an initialized voltage signal, the first signal output terminal of the input module is connected to the first signal input terminal of the operation module, and the second signal output terminal of the input module is respectively connected to the second signal input terminal of the operation module and the signal output terminal of the output module The transmission end is connected, the signal output end of the operation module is connected to the signal input end of the output module, the high power connection end of the operation module is connected to the power supply, the low power connection end of the output module is grounded, the first signal input end and the second signal input end of the input module each receive a voltage signal to be compared, the operation control end of the input module receives the unit operation control signal, the latch control end of the output module receives the latch control signal, and the signal output end of the output module outputs the comparison result in the form of a voltage signal; when the voltage signal to be compared received by the first signal input end of the input module is less than the voltage signal to be compared received by the second signal input end, the signal output end of the output module outputs a high level; when the voltage signal to be compared received by the first signal input end of the input module is greater than or equal to the voltage signal to be compared received by the second signal input end, the signal output end of the output module outputs a low level. Here, the input and output configurations of each module are defined, so that the storage and calculation integrated comparison operation unit is more modular, easy to integrate and expand; and through the specific connection relationship, the effective transmission and processing of the signal in the circuit is ensured.

[0011] Specifically, the input module includes a first NMOS transistor and a second NMOS transistor, the source of the first NMOS transistor serves as the first signal input terminal of the input module, the source of the second NMOS transistor serves as the second signal input terminal of the input module, the gate of the first NMOS transistor and the gate of the second NMOS transistor are connected and serve as the operation control terminal of the input module, the drain of the first NMOS transistor serves as the first signal output terminal of the input module, and the drain of the second NMOS transistor serves as the second signal output terminal of the input module. Here, the composition and connection relationship of the input module are specifically given, and the data transmission in the comparison operation process is optimized.

[0012] Specifically, the operation module further includes a PMOS transistor, the gate and source of the PMOS transistor are connected and serve as the high power connection terminal of the operation module, the drain of the PMOS transistor is connected to the drain of the ferroelectric transistor and serves as the signal output terminal of the operation module, the gate of the ferroelectric transistor serves as the first signal input terminal of the operation module, and the source of the ferroelectric transistor serves as the second signal input terminal of the operation module. Here, the connection mode of the PMOS transistor and the ferroelectric transistor in the operation module is defined, so that the PMOS transistor works in the resistance area, the ferroelectric transistor can form a conductive channel according to the initialized voltage signal received by its gate and source before the comparison operation starts, maintain or destroy its conductive channel according to the voltage signal to be compared received by its gate and source during the comparison operation, establish an operation relationship with an external voltage signal as input and an internal channel on and off as output, and the comparison result is not affected by whether the power supply is supplied and presents non-volatile.

[0013] Specifically, the output module includes a third NMOS transistor and a fourth NMOS transistor, the source of the third NMOS transistor serves as the low power connection terminal of the output module, the drain of the third NMOS transistor serves as the signal transmission terminal of the output module, the gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor and serves as the latch control terminal of the output module, the source of the fourth NMOS transistor serves as the signal input terminal of the output module, and the drain of the fourth NMOS transistor serves as the signal output terminal of the output module. Here, the composition and connection relationship of the output module are specifically given, so that the non-volatile comparison result can be accurately read as a voltage signal regardless of the normal power supply stage or the power-off recovery stage, creating conditions for the correct recovery of the calculation process and the direct cascading of multiple storage-computation-in-one comparison operation units.

[0014] A comparator circuit implemented using the above-mentioned storage-computation-in-one comparison operation unit, characterized by comprising:

[0015] The first storage-computation integrated comparison operation unit and the second storage-computation integrated comparison operation unit are configured such that the two ferroelectric transistors are uniformly initialized to a conducting state before the comparison operation starts; during the comparison operation, the two ferroelectric transistors respectively maintain or change their respective conducting states, thereby respectively performing a less-than comparison operation, and the two comparison results are respectively transmitted to the interlocking unit by the signal output terminals of the corresponding output modules in the form of voltage signals;

[0016] An interlocking unit receives the voltage signals transmitted by the two output modules, and uses logic gates to implement static latching of the two voltage signals, and constructs a less than comparison path, an equal to comparison path, and a greater than comparison path, and obtains a less than comparison result, an equal to comparison result, and a greater than comparison result, respectively;

[0017] A low-order suppression unit receives the equal comparison result fed back by the interlocking unit, performs a logical operation with the original operation control signal, outputs a unit operation control signal and transmits it to the first storage-computation-in-one comparison operation unit and the second storage-computation-in-one comparison operation unit, so as to suppress the transmission process of the low-order voltage signal to the first storage-computation-in-one comparison operation unit and the second storage-computation-in-one comparison operation unit when the comparison result of the high-order voltage signal is unequal in size, thereby eliminating redundant comparison.

[0018] It is further defined that the first storage-computing integrated comparison operation unit and the second storage-computing integrated comparison operation unit are connected in parallel, the interlocking unit has a first signal input terminal and a second signal input terminal, a signal output terminal of the less than comparison path, a signal output terminal of the equal to comparison path, and a signal output terminal of the greater than comparison path, and the low-level suppression unit has a first signal input terminal and a second signal input terminal, and a signal output terminal; the first signal input terminal of the input module in the first storage-computing integrated comparison operation unit receives a first voltage signal, and the second signal input terminal receives a second voltage signal, the first signal input terminal of the input module in the second storage-computing integrated comparison operation unit receives a second voltage signal, and the second signal input terminal receives a first voltage signal, and the signal output terminal of the output module in the first storage-computing integrated comparison operation unit is connected to the The first signal input terminal of the interlocking unit is connected, the signal output terminal of the output module in the second storage-computation-in-one comparison operation unit is connected to the second signal input terminal of the interlocking unit, the signal output terminal of the less than comparison path outputs a less than comparison result, the signal output terminal of the equal to comparison path outputs an equal to comparison result, the signal output terminal of the greater than comparison path outputs a greater than comparison result, the signal output terminal of the equal to comparison path is connected to the first signal input terminal of the low-level suppression unit, the second signal input terminal of the low-level suppression unit receives the original operation control signal, the signal output terminal of the low-level suppression unit outputs the unit operation control signal, and the signal output terminal of the low-level suppression unit is respectively connected to the operation control terminals of the input modules in the first storage-computation-in-one comparison operation unit and the second storage-computation-in-one comparison operation unit.

[0019] Specifically, the interlock unit includes a first interlock structure formed by connecting a first inverter and a second inverter end to end, a third inverter, a second interlock structure formed by connecting a fourth inverter and a fifth inverter end to end, a sixth inverter, and a first AND gate, wherein the first interlock structure is used to temporarily lock the voltage signal output from the first storage-computing integrated comparison operation unit, and the second interlock structure is used to temporarily lock the voltage signal output from the second storage-computing integrated comparison operation unit. The first interlock structure and the third inverter constitute the less than comparison path, the second interlock structure and the sixth inverter constitute the greater than comparison path, the first interlock structure, the second interlock structure, and the first AND gate constitute the equal comparison path, and the input end of the first inverter is connected to the second inverter. The output end of the first inverter is connected to the input end of the second inverter and is connected to the input end of the third inverter and the first input end of the first AND gate respectively, the output end of the third inverter is used as the signal output end of the less than comparison path, the input end of the fourth inverter is connected to the output end of the fifth inverter and is used as the second signal input end of the interlocking unit, the output end of the fourth inverter is connected to the input end of the fifth inverter and is connected to the input end of the sixth inverter and the second input end of the first AND gate respectively, the output end of the sixth inverter is used as the signal output end of the greater than comparison path, and the output end of the first AND gate is used as the signal output end of the equal comparison path. Here, the composition and connection relationship of the interlocking unit are specifically given, so as to realize the static storage of the voltage signal representing the non-volatile comparison result and maintain the stable voltage signal output.

[0020] Specifically, the low-bit suppression unit includes a second AND gate, the first input end of the second AND gate serves as the first signal input end of the low-bit suppression unit, the second input end of the second AND gate serves as the second signal input end of the low-bit suppression unit, and the output end of the second AND gate serves as the signal output end of the low-bit suppression unit. Here, the second AND gate can adjust the control of the operation control signal received at its second input end on the storage-computation integrated comparison operation unit according to the voltage signal of whether the data received at its first input end is equal, thereby suppressing the redundant low-bit voltage signal comparison process in the comparison of multi-bit serial voltage data and improving the operation energy consumption.

[0021] Compared with the prior art, the advantages of the utility model are:

[0022] The storage-computation integrated comparison operation unit gets rid of the extra power consumption caused by the conversion circuit, and at the same time utilizes the operation and storage capabilities of the ferroelectric transistor to realize the less-than comparison of the gate and source voltage signals of the ferroelectric transistor, and the comparison result is stored in the ferroelectric transistor in situ. By establishing the voltage division path of the operation module, the comparison result can be correctly output in the form of voltage regardless of normal power supply or even power failure recovery stage. In the storage-computation integrated comparator circuit based on the comparison operation unit, the accurate equal comparison result, greater than comparison result, and less than comparison result are completely non-volatile: in the normal power supply stage, the interlocking unit does not need to repeatedly read out the comparison result to maintain a stable voltage signal output; in the power failure and recovery stage, the comparison result output by the storage-computation integrated comparison operation unit is re-transmitted to the interlocking unit, updated and stored, and re-stable output. In addition, the non-volatile equal comparison result can control the comparison operation process through feedback, realizing the suppression of redundant comparison of low-bit voltage signals in multi-bit serial voltage data comparison. The completely non-volatile comparison results ensure the correctness of the operation, and the suppression function of redundant comparisons further reduces the power consumption of the operation. Therefore, the proposed storage-computation integrated comparison operation unit and comparator circuit are suitable for the IoT environment with unstable power supply, and appropriately expand the IoT edge chip operation unit library. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of an N-type ferroelectric transistor;

[0024] Figure 2 is a schematic diagram of an NMOS transistor;

[0025] Figure 3 is a schematic diagram of a PMOS transistor;

[0026] Figure 4 is a schematic diagram of an inverter;

[0027] Figure 5 is a schematic diagram of a logic AND gate;

[0028] Figure 6 A schematic diagram of a storage-computation-in-one comparison operation unit based on ferroelectric transistors;

[0029] Figure 7 For use Figure 6 A schematic diagram of a storage-computation-in-one comparator circuit implemented by a storage-computation-in-one comparison operation unit shown;

[0030] Figure 8 for Figure 7 The timing simulation results of the storage and calculation integrated comparator circuit are shown. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present utility model clearer, the technical solution in the embodiments of the present utility model will be clearly and completely described below in conjunction with the accompanying drawings in the examples of the present utility model.

[0032] The utility model proposes a storage-computation integrated comparison operation unit based on ferroelectric transistors, which uses N-type ferroelectric transistors, NMOS transistors, and PMOS transistors to realize non-volatile numerical comparison operations. The comparator circuit is realized by the storage-computation integrated comparison operation unit based on ferroelectric transistors and logic gates.

[0033] Figure 1 A schematic diagram of an N-type ferroelectric transistor is given, where the g terminal is the gate of the ferroelectric transistor, the s terminal is the source of the ferroelectric transistor, and the d terminal is the drain of the ferroelectric transistor. When a forward bias voltage is applied between the g terminal and the s terminal of the N-type ferroelectric transistor, and the forward bias voltage is greater than the threshold V TH When the voltage difference between the g terminal and the s terminal is less than the threshold value V TH Even after the voltage between the g and s terminals is removed, it still remains; when a reverse bias voltage is applied between the g and s terminals of the N-type ferroelectric transistor, and the reverse bias voltage is greater than the threshold V TL When the conductive channel between the source and drain of the N-type ferroelectric transistor disappears, the N-type ferroelectric transistor is in the "off" state, and the voltage difference between the g-terminal and the s-terminal in this state is less than the threshold value V TL It remains even after the voltage on the g and s terminals is removed.

[0034] Figure 2 A schematic diagram of an NMOS transistor is given, where g N The terminal is the gate of the NMOS transistor, s N The end is the source of the NMOS transistor, d N The terminal is the drain of the NMOS transistor. The on-off state of the NMOS transistor depends on g N The voltage applied to the terminal. N The voltage applied to the terminal is greater than its threshold voltage V thn When N end and d N A conductive channel is formed between the two terminals, and the NMOS transistor is in the "on" state; when g N The voltage applied to the terminal is less than its threshold voltage V thn When N end and d N The conductive channel between the terminals disappears and the NMOS transistor is in the "off" state.

[0035] Figure 3A schematic diagram of a PMOS transistor is given, where g P The end is the gate of the PMOS transistor, s P The end is the source of the PMOS transistor, d P The end is the drain of the PMOS transistor. The on-off state of the PMOS transistor depends on g P The voltage applied to the terminal. P The voltage applied to the terminal is less than its threshold voltage V thp When P end and d P A conductive channel is formed between the two ends, and the PMOS transistor is in the "on" state; when g P The voltage applied to the terminal is greater than its threshold voltage V thp When P end and d P The conductive channel between the two ends disappears and the PMOS transistor is in the "off" state.

[0036] Figure 4 A schematic diagram of an inverter is given, in which the in terminal is the input terminal and the ot terminal is the output terminal. When a high-level voltage is input to the input terminal of the inverter, the output terminal of the inverter outputs a low-level voltage; conversely, when a low-level voltage is input to the input terminal of the inverter, the output terminal of the inverter outputs a high-level voltage.

[0037] Figure 5 The schematic diagram of the logic AND gate is given, where in1 is the first input terminal of the logic AND gate, in2 is the second input terminal of the logic AND gate, and out is the output terminal of the logic AND gate. When a low-level voltage is input to any input terminal, the output terminal out of the logic AND gate outputs a low-level voltage; conversely, when high-level voltages are input to both input terminals, the output terminal out of the logic AND gate outputs a high-level voltage.

[0038] Implementation case 1:

[0039] This embodiment proposes a storage and calculation integrated comparison operation unit based on ferroelectric transistors, such as Figure 6As shown, it includes: an input module 11, which receives two voltage signals to be compared during the comparison operation, and determines whether to pass the two voltage signals to be compared to the operation module 12 according to the unit operation control signal; the operation module 12 includes a ferroelectric transistor Fe1, before the comparison operation starts, the gate and source of the ferroelectric transistor Fe1 respectively receive an initialized voltage signal, so that the ferroelectric transistor Fe1 is initialized to a conductive state, wherein the two initialized voltage signals are a pair of mutually inverted level signals; during the comparison operation, after the gate and source of the ferroelectric transistor Fe1 receive the two voltage signals to be compared transmitted by the input module 11, the conductive state thereof is maintained or changed, thereby executing a less than comparison operation, and the comparison result is stored as the switch state of the ferroelectric transistor Fe1, realizing a non-volatile storage-computation integrated comparison operation; an output module 13, which establishes a voltage division path for the operation module 12, reads the comparison result stored in the operation module 12 as a voltage signal and outputs it.

[0040] It is further defined that the input module 11 has a first signal input terminal IN1 and a second signal input terminal IN2, an operation control terminal CL*, a first signal output terminal and a second signal output terminal, the operation module 12 has a first signal input terminal and a second signal input terminal, a high power connection terminal, and a signal output terminal. The first signal input terminal of the operation module 12 also serves as the first initialization terminal Set of the storage-computation integrated comparison operation unit, and the second signal input terminal of the operation module 12 also serves as the second initialization terminal !Set of the storage-computation integrated comparison operation unit. The output module 13 has a low power connection terminal, a signal transmission terminal, a signal input terminal, a signal output terminal OUT, and a latch control terminal RE; the first initialization terminal Set and the second initialization terminal !Set each receive an initialized voltage signal, the first signal output terminal of the input module 11 is connected to the first signal input terminal of the operation module 12, the second signal output terminal of the input module 11 is respectively connected to the second signal input terminal of the operation module 12 and the signal transmission terminal of the output module 13, the signal output terminal of the operation module 12 is connected to the signal input terminal of the output module 13, and the high power connection terminal of the operation module 12 is connected to the power supply V dd, the low power connection end of the output module 13 is grounded, the first signal input end IN1 and the second signal input end IN2 of the input module 11 each receive a voltage signal to be compared, the operation control end CL* of the input module 11 receives the unit operation control signal, the latch control end RE of the output module 13 receives the latch control signal, and the signal output end OUT of the output module 13 outputs the comparison result in the form of a voltage signal; when the voltage signal to be compared received by the first signal input end IN1 of the input module 11 is less than the voltage signal to be compared received by the second signal input end IN2, the signal output end OUT of the output module 13 outputs a high level; when the voltage signal to be compared received by the first signal input end IN1 of the input module 11 is greater than or equal to the voltage signal to be compared received by the second signal input end IN2, the signal output end OUT of the output module 13 outputs a low level. Here, the input and output configurations of each module are defined, so that the storage and calculation integrated comparison operation unit is more modular, easy to integrate and expand; and through the specific connection relationship, the effective transmission and processing of the signal in the circuit is ensured.

[0041] Specifically, the input module 11 includes a first NMOS transistor N1 and a second NMOS transistor N2, the source of the first NMOS transistor N1 serves as the first signal input terminal IN1 of the input module 11, the source of the second NMOS transistor N2 serves as the second signal input terminal IN2 of the input module 11, the gate of the first NMOS transistor N1 is connected to the gate of the second NMOS transistor N2 and serves as the operation control terminal CL* of the input module 11, the drain of the first NMOS transistor N1 serves as the first signal output terminal of the input module 11, and the drain of the second NMOS transistor N2 serves as the second signal output terminal of the input module 11. Here, the composition and connection relationship of the input module 11 are specifically given, and the data transmission in the comparison operation process is optimized.

[0042] Specifically, the operation module 12 further includes a PMOS transistor P1, the gate and source of the PMOS transistor P1 are connected and serve as the high power connection terminal of the operation module 12, the drain of the PMOS transistor P1 is connected to the drain of the ferroelectric transistor Fe1 and serves as the signal output terminal of the operation module 12, the gate of the ferroelectric transistor Fe1 serves as the first signal input terminal of the operation module 12, and the source of the ferroelectric transistor Fe1 serves as the second signal input terminal of the operation module 12. Here, the connection mode of the PMOS transistor P1 and the ferroelectric transistor Fe1 in the operation module 12 is defined, so that the PMOS transistor P1 works in the resistance region, the ferroelectric transistor Fe1 can form a conductive channel according to the initialized voltage signal received by its gate and source before the comparison operation starts, and maintain or destroy its conductive channel according to the voltage signal to be compared received by its gate and source during the comparison operation, establish an operation relationship with an external voltage signal as input and an internal channel on-off as output, and the comparison result is not affected by whether the power supply is supplied and presents non-volatile.

[0043] Specifically, the output module 13 includes a third NMOS transistor N3 and a fourth NMOS transistor N4, the source of the third NMOS transistor N3 serves as a low power connection terminal of the output module 13, the drain of the third NMOS transistor N3 serves as a signal transmission terminal of the output module 13, the gate of the third NMOS transistor N3 is connected to the gate of the fourth NMOS transistor N4 and serves as a latch control terminal RE of the output module 13, the source of the fourth NMOS transistor N4 serves as a signal input terminal of the output module 13, and the drain of the fourth NMOS transistor N4 serves as a signal output terminal OUT of the output module 13. Here, the composition and connection relationship of the output module 13 are specifically given, so that the non-volatile comparison result can be accurately read as a voltage signal regardless of the normal power supply stage or the power-off recovery stage, creating conditions for the correct recovery of the calculation process and the direct cascading of multiple storage-computation-in-one comparison operation units.

[0044] Preferably, the ferroelectric transistor Fe1 is an N-type ferroelectric transistor.

[0045] exist Figure 6In the figure, before the comparison operation starts, the first initialization terminal Set and the second initialization terminal !Set are connected to the high level and the low level respectively, and the ferroelectric transistor Fe1 is initialized to the on state, which creates reasonable conditions for realizing the less than comparison operation. The initialized ferroelectric transistor Fe1 can regard the gate and the source as the logic input terminal, and destroy the conductive channel of the ferroelectric transistor Fe1 when the first signal input terminal IN1 of the input module 11 is connected to the low level and the second signal input terminal IN2 is connected to the high level. Under other voltage conditions at both ends, the switch state of the ferroelectric transistor Fe1 is maintained, which equivalently demonstrates the comparison operation capability that the voltage signal connected to the first signal input terminal IN1 of the input module 11 is less than the voltage signal connected to the second signal input terminal IN2. The switch state of the ferroelectric transistor Fe1 is regarded as the result of the comparison operation, and the real-time storage of the comparison result is realized.

[0046] Implementation case 2:

[0047] This embodiment proposes a comparator circuit implemented by using the storage-computation-in-one comparison operation unit of the first embodiment, which is obtained by cascading the above two storage-computation-in-one comparison operation units and logic gates, such as Figure 7 As shown, it includes: a first storage-calculation integrated comparison operation unit 21 and a second storage-calculation integrated comparison operation unit 22, and the two ferroelectric transistors are uniformly initialized to the on state before the comparison operation starts; during the comparison operation, the two ferroelectric transistors respectively realize the maintenance or change of their respective on states, so as to respectively perform the less than comparison operation, and the two comparison results are respectively transmitted to the interlocking unit 23 in the form of voltage signals by the signal output terminal OUT of the corresponding output module 13; the interlocking unit 23 receives the voltage signals transmitted by the two output modules 13, and uses logic gates to realize the static latching of the two voltage signals, and at the same time constructs a less than comparison path, an equal comparison path, and a greater than comparison path, and obtains the less than comparison result, the equal comparison result, and the greater than comparison result respectively; the low-bit suppression unit 24 receives the equal comparison result fed back by the interlocking unit 23, and through the original operation control signal ( Figure 7 The output unit performs a logic operation on the signal input from the CL terminal shown in the figure, and transmits the control signal to the first storage-computation integrated comparison operation unit 21 and the second storage-computation integrated comparison operation unit 22, so as to suppress the transmission process of the low voltage signal to the first storage-computation integrated comparison operation unit 21 and the second storage-computation integrated comparison operation unit 22 when the comparison result of the high voltage signal is unequal, thereby eliminating redundant comparison. Figure 7 The upper storage-computation-in-one comparison operation unit is defined as the first storage-computation-in-one comparison operation unit 21 , and the lower storage-computation-in-one comparison operation unit is defined as the second storage-computation-in-one comparison operation unit 22 .

[0048] It is further defined that the first storage-computation integrated comparison operation unit 21 and the second storage-computation integrated comparison operation unit 22 are connected in parallel, the interlocking unit 23 has a first signal input terminal and a second signal input terminal, a signal output terminal O1 less than the comparison path, a signal output terminal O2 equal to the comparison path, and a signal output terminal O3 greater than the comparison path, and the low-level suppression unit 24 has a first signal input terminal and a second signal input terminal CL, and a signal output terminal; the first signal input terminal IN1 of the input module 11 in the first storage-computation integrated comparison operation unit 21 receives a first voltage signal, and the second signal input terminal IN2 receives a second voltage signal, the first signal input terminal IN1 of the input module 11 in the second storage-computation integrated comparison operation unit 22 receives a second voltage signal, and the second signal input terminal IN2 receives the first voltage signal, and the signal output terminal O3 of the output module 13 in the first storage-computation integrated comparison operation unit 21 receives a second voltage signal, and the second signal input terminal IN2 receives a first voltage signal. UT is connected to the first signal input terminal of the interlocking unit 23, the signal output terminal OUT of the output module 13 in the second storage-computation integrated comparison operation unit 22 is connected to the second signal input terminal of the interlocking unit 23, the signal output terminal O1 of the less-than comparison path outputs a less-than comparison result, the signal output terminal O2 of the equal comparison path outputs an equal comparison result, the signal output terminal O3 of the greater-than comparison path outputs a greater-than comparison result, the signal output terminal O2 of the equal comparison path is connected to the first signal input terminal of the low-level suppression unit 24, the second signal input terminal CL of the low-level suppression unit 24 receives the original operation control signal, the signal output terminal of the low-level suppression unit 24 outputs the unit operation control signal, and the signal output terminal of the low-level suppression unit 24 is respectively connected to the operation control terminal CL* of the input module 11 in the first storage-computation integrated comparison operation unit 21 and the second storage-computation integrated comparison operation unit 22.

[0049] Specifically, the interlock unit 23 includes a first interlock structure formed by connecting the first inverter INV1 and the second inverter INV2 end to end, a third inverter INV3, a second interlock structure formed by connecting the fourth inverter INV4 and the fifth inverter INV5 end to end, a sixth inverter INV6, and a first AND gate AND1. The first interlock structure is used to temporarily lock the voltage signal output from the first storage-computation integrated comparison operation unit 21, and the second interlock structure is used to temporarily lock the voltage signal output from the second storage-computation integrated comparison operation unit 22. The first interlock structure and the third inverter INV3 constitute a less than comparison path, the second interlock structure and the sixth inverter INV6 constitute a greater than comparison path, the first interlock structure and the second interlock structure and the first AND gate AND1 constitute an equal comparison path, and the input end of the first inverter INV1 is connected to the input end of the second inverter INV2. The output end is connected and serves as the first signal input end of the interlock unit 23, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and is respectively connected to the input end of the third inverter INV3 and the first input end of the first AND gate AND1, the output end of the third inverter INV3 serves as the signal output end O1 less than the comparison path, the input end of the fourth inverter INV4 is connected to the output end of the fifth inverter INV5 and serves as the second signal input end of the interlock unit 23, the output end of the fourth inverter INV4 is connected to the input end of the fifth inverter INV5 and is respectively connected to the input end of the sixth inverter INV6 and the second input end of the first AND gate AND1, the output end of the sixth inverter INV6 serves as the signal output end O3 greater than the comparison path, and the output end of the first AND gate AND1 serves as the signal output end O2 equal to the comparison path. Here, the composition and connection relationship of the interlock unit 23 are specifically given, so as to realize the static storage of the voltage signal representing the non-volatile comparison result and maintain the stable voltage signal output.

[0050] Specifically, the low-bit suppression unit 24 includes a second AND gate AND2, a first input end of the second AND gate AND2 serves as a first signal input end of the low-bit suppression unit 24, a second input end of the second AND gate AND2 serves as a second signal input end CL of the low-bit suppression unit 24, and an output end of the second AND gate AND2 serves as a signal output end of the low-bit suppression unit 24. Here, the second AND gate AND2 can adjust the control of the storage-computation integrated comparison operation unit by the operation control signal received at its second input end according to the voltage signal of whether the data received at its first input end is equal, thereby suppressing the redundant low-bit voltage signal comparison process in the comparison of multi-bit serial voltage data and improving the operation energy consumption.

[0051] exist Figure 7In the process, if the operation control terminal CL* of the input module 11 receives a high level, the first storage-computation integrated comparison operation unit 21 and the second storage-computation integrated comparison operation unit 22 are in the operation stage, and the switching states of the two ferroelectric transistors are maintained or switched according to the sizes of the first voltage signal and the second voltage signal to be compared, and a comparison result of whether the voltage signal received by the first signal input terminal IN1 of the input module 11 is smaller than the voltage signal received by the second signal input terminal IN2 is obtained, and the comparison results are stored as the switching states of the corresponding ferroelectric transistors. If the operation control terminal CL* of the input module 11 receives a low level, and the latch control terminal RE of the output module 13 receives a high level, the two comparison results are transmitted from the corresponding signal output terminal of the output module 13 to the first signal input terminal or the second signal input terminal of the interlocking unit 23 in the form of a voltage signal: when the first voltage signal is less than the second voltage signal, the first storage and calculation integrated comparison operation unit 21 outputs a high level voltage signal to the first signal input terminal of the interlocking unit 23, and the second storage and calculation integrated comparison operation unit 22 outputs a low level voltage signal to the second signal input terminal of the interlocking unit 23; when the first voltage signal is greater than the second voltage signal, the first storage and calculation integrated comparison operation unit 21 outputs a low level voltage signal to the first signal input terminal of the interlocking unit 23, and the second storage and calculation integrated comparison operation unit 22 outputs a high level voltage signal to the second signal input terminal of the interlocking unit 23; when the first voltage signal is equal to the second voltage signal, the first storage and calculation integrated comparison operation unit 21 and the second storage and calculation integrated comparison operation unit 22 both output low level voltage signals. In the interlocking unit 23, when the first signal input terminal and the second signal input terminal of the interlocking unit 23 both receive low levels, it means that the first voltage signal and the second voltage signal are equal, and at this time, the signal output terminal O1 that is smaller than the comparison path and the signal output terminal O3 that is larger than the comparison path output a low level, and the signal output terminal O2 that is equal to the comparison path outputs a high level; when the first signal input terminal of the interlocking unit 23 receives a low level and the second signal input terminal receives a high level, it means that the first voltage signal is greater than the second voltage signal, and at this time, the signal output terminal O1 that is smaller than the comparison path and the signal output terminal O2 that is equal to the comparison path output a low level, and the signal output terminal O3 that is greater than the comparison path outputs a high level; when the first signal input terminal of the interlocking unit 23 receives a high level and the second signal input terminal receives a low level, it means that the first voltage signal is less than the second voltage signal, and at this time, the signal output terminal O2 that is equal to the comparison path and the signal output terminal O3 that is larger than the comparison path output a low level, and the signal output terminal O1 that is less than the comparison path outputs a high level.

[0052] To further illustrate the feasibility of the storage-computation-in-one comparison operation unit and the comparator circuit of the present invention, Figure 7 The comparator circuit shown is used for simulation experiments.

[0053] In the simulation experiment, "0" is used to represent a low-level voltage signal, and "1" is used to represent a high-level voltage signal. Figure 8 Yes Figure 7 The simulation result of the comparator circuit shown in FIG. 1 is shown in FIG. 1 , wherein Set is the first initialization terminal for receiving the initialization voltage signal; A represents the first 4-bit serial voltage data, A= a 3 a 2 a 1 a 0, the serial input from the high voltage signal to the low voltage signal is {0, 0, 1, 1}, each voltage signal in A is used as the first voltage signal, and B represents the second 4-bit serial voltage data, B= b 3 b 2 b 1 b 0, the serial input from the high-order voltage signal to the low-order voltage signal is {0, 1, 0, 1}, and each voltage signal in B is used as the second voltage signal; CL is the second signal input terminal of the low-order suppression unit 24, which is used to receive the original operation control signal; CL* is the operation control terminal of the input module 11, which is used to receive the unit operation control signal; RE is the latch control terminal of the output module 13, which is used to receive the latch control signal; O1 is the signal output terminal of the less than comparison path, which is used to output the less than comparison result; O2 is the signal output terminal of the equal to comparison path, which is used to output the equal to comparison result; O3 is the signal output terminal of the greater than comparison path, which is used to output the greater than comparison result.

[0054] Figure 8In the process, before the comparison operation starts, the ferroelectric transistors in the first storage-computation integrated comparison operation unit 21 and the second storage-computation integrated comparison operation unit 22 are initialized. At this time, the first initialization terminal Set is connected to a high level, and the second initialization terminal !Set is connected to a low level, so that the two ferroelectric transistors are set to the on state. Then the comparison operation process is started. At the moment T1 of the first cycle L1, the second signal input terminal CL of the low-bit suppression unit 24 is connected to a high level, the latch control terminal RE is connected to a low level, and the unit operation control signal transmitted to the operation control terminal CL* of the input module 11 in the first storage-computation integrated comparison operation unit 21 and the second storage-computation integrated comparison operation unit 22 is a high level. After that, the first storage-computation integrated comparison operation unit 21 and the second storage-computation integrated comparison operation unit 22 each start the comparison operation. The highest voltage signal {0} of A is transmitted to the first signal input terminal IN1 of the input module 11 in the first storage-computation integrated comparison operation unit 21 and the second signal input terminal IN2 of the input module 11 in the second storage-computation integrated comparison operation unit 22, and the highest voltage signal {0} of B is transmitted to the second signal input terminal IN2 of the input module 11 in the first storage-computation integrated comparison operation unit 21 and the first signal input terminal IN1 of the input module 11 in the second storage-computation integrated comparison operation unit 22. Because the two voltage signals are consistent, the ferroelectric transistors in the first storage-computation integrated comparison operation unit 21 and the second storage-computation integrated comparison operation unit 22 remain in the on state. At the moment T2 of the first cycle L1, the second signal input terminal CL of the low-level suppression unit 24 is connected to a low level, the latch control terminal RE is connected to a high level, and the conduction state of the ferroelectric transistors in the first storage-computation integrated comparison operation unit 21 and the second storage-computation integrated comparison operation unit 22 is read as a low level, and transmitted to the first signal input terminal and the second signal input terminal of the interlocking unit 23 respectively. Therefore, the less-than comparison result output by the signal output terminal O1 of the less-than comparison path and the greater-than comparison result output by the signal output terminal O3 of the greater-than comparison path are both low levels, and the equal comparison result output by the first AND gate AND1 is a high level. At the moment T3 of the first cycle L1, because the comparison results output by the two output modules 13 have been temporarily stored in the interlocking unit 23, the less-than comparison result, the greater-than comparison result, and the equal comparison result remain unchanged.

[0055] At the moment T1 of the second cycle L2, the second signal input terminal CL of the low-level suppression unit 24 is connected to a high level, and the latch control terminal RE is connected to a low level. Because the comparison result is equal to the high level, the unit operation control signal obtained after passing through the low-level suppression unit 24 is a high level. After that, the first storage-computation integrated comparison operation unit 21 and the second storage-computation integrated comparison operation unit 22 each start the comparison operation. The second highest voltage signal {0} is transmitted to the first signal input terminal IN1 of the input module 11 in the first storage-computation integrated comparison operation unit 21 and the second signal input terminal IN2 of the input module 11 in the second storage-computation integrated comparison operation unit 22. The second highest voltage signal {1} ​​of B is transmitted to the second signal input terminal IN2 of the input module 11 in the first storage-computation integrated comparison operation unit 21 and the first signal input terminal IN1 of the input module 11 in the second storage-computation integrated comparison operation unit 22. Because the first voltage signal is less than the second voltage signal, the ferroelectric transistor in the first storage-computation integrated comparison operation unit 21 is changed to the off state, while the ferroelectric transistor in the second storage-computation integrated comparison operation unit 22 remains on. At the moment T2 of the second cycle L2, the second signal input terminal CL of the low-order suppression unit 24 is connected to a low level, the latch control terminal RE is connected to a high level, the off state of the ferroelectric transistor in the first storage-computation integrated comparison operation unit 21 is read as a high level, and the on state of the ferroelectric transistor in the second storage-computation integrated comparison operation unit 22 is read as a low level, which are respectively transmitted to the first signal input terminal and the second signal input terminal of the interlocking unit 23. Therefore, the less-than comparison result output by the signal output terminal O1 of the less-than comparison path in the interlocking unit 23 is a high level, and the greater-than comparison result output by the signal output terminal O3 of the greater-than comparison path is a low level, and the equal comparison result output by the first AND gate AND1 is also a low level. At the moment T3 of the second cycle L2, because the comparison results output by the two output modules 13 have been temporarily stored in the interlocking unit 23, the less-than comparison result, the greater-than comparison result, and the equal comparison result remain unchanged.

[0056] At the moment T1 of the third cycle L2, the second signal input terminal CL of the low-level suppression unit 24 is connected to a high level, and the latch control terminal RE is connected to a low level. Because the equal comparison result is a low level, the unit operation control signal obtained after passing through the low-level suppression unit 24 is a low level, which suppresses the third round of less than comparison operation of the first storage-calculation integrated comparison operation unit 21 and the second storage-calculation integrated comparison operation unit 22. The state of the ferroelectric transistor is no longer affected by the change of the gate and source voltages, and therefore remains unchanged. At the moment T2 of the third cycle L2, the second signal input terminal CL of the low-level suppression unit 24 is connected to a low level, and the latch control terminal RE is connected to a high level. The ferroelectric transistor in the first storage-calculation integrated comparison operation unit 21 is still in the off state and is read as a high level, and the ferroelectric transistor in the second storage-calculation integrated comparison operation unit 22 is still in the on state and is read as a low level, which are respectively transmitted to the first signal input terminal and the second signal input terminal of the interlocking unit 23. At the moment T3 of the third cycle L2, the less than comparison result, the greater than comparison result, and the equal to comparison result are maintained.

Claims

1. A storage and calculation integrated comparison operation unit based on ferroelectric transistors, characterized in that include: An input module receives two voltage signals to be compared during the comparison operation and determines whether to pass the two voltage signals to be compared to the operation module according to the unit operation control signal; The operation module includes a ferroelectric transistor. Before the comparison operation starts, the gate and source of the ferroelectric transistor receive an initialization voltage signal respectively, so that the ferroelectric transistor is initialized to a conducting state, wherein the two initialization voltage signals are a pair of mutually inverted level signals; during the comparison operation, after the gate and source of the ferroelectric transistor receive the two voltage signals to be compared transmitted by the input module, the conducting state thereof is maintained or changed, thereby performing a less than comparison operation, and the comparison result is stored as the switch state of the ferroelectric transistor, thereby realizing a non-volatile storage-computation integrated comparison operation; The output module establishes a voltage division path for the operation module, reads the comparison result stored in the operation module as a voltage signal and outputs it.

2. The ferroelectric transistor-based storage and calculation integrated comparison operation unit according to claim 1, characterized in that The input module has a first signal input terminal and a second signal input terminal, an operation control terminal, a first signal output terminal and a second signal output terminal. The operation module has a first signal input terminal and a second signal input terminal, a high power connection terminal, and a signal output terminal. The first signal input terminal of the operation module also serves as the first initialization terminal of the storage-computation-in-one comparison operation unit, and the second signal input terminal of the operation module also serves as the second initialization terminal of the storage-computation-in-one comparison operation unit. The output module has a low power connection terminal, a signal transmission terminal, a signal input terminal, a signal output terminal, and a latch control terminal; the first initialization terminal and the second initialization terminal each receive an initialized voltage signal, the first signal output terminal of the input module is connected to the first signal input terminal of the operation module, and the second signal output terminal of the input module is respectively connected to the second signal input terminal of the operation module and the signal transmission terminal of the output module. The signal output terminal of the operation module is connected to the signal input terminal of the output module, the high power connection terminal of the operation module is connected to the power supply, the low power connection terminal of the output module is grounded, the first signal input terminal and the second signal input terminal of the input module each receive a voltage signal to be compared, the operation control terminal of the input module receives a unit operation control signal, the latch control terminal of the output module receives a latch control signal, and the signal output terminal of the output module outputs a comparison result in the form of a voltage signal; when the voltage signal to be compared received by the first signal input terminal of the input module is less than the voltage signal to be compared received by the second signal input terminal, the signal output terminal of the output module outputs a high level; when the voltage signal to be compared received by the first signal input terminal of the input module is greater than or equal to the voltage signal to be compared received by the second signal input terminal, the signal output terminal of the output module outputs a low level.

3. The ferroelectric transistor-based storage and calculation integrated comparison operation unit according to claim 2, characterized in that The input module includes a first NMOS transistor and a second NMOS transistor, the source of the first NMOS transistor serves as a first signal input terminal of the input module, the source of the second NMOS transistor serves as a second signal input terminal of the input module, the gate of the first NMOS transistor and the gate of the second NMOS transistor are connected and serve as an operation control terminal of the input module, the drain of the first NMOS transistor serves as a first signal output terminal of the input module, and the drain of the second NMOS transistor serves as a second signal output terminal of the input module.

4. The ferroelectric transistor-based storage and calculation integrated comparison operation unit according to claim 2 or 3, characterized in that The operation module also includes a PMOS transistor, the gate and source of the PMOS transistor are connected and serve as the high power connection terminal of the operation module, the drain of the PMOS transistor is connected to the drain of the ferroelectric transistor and serves as the signal output terminal of the operation module, the gate of the ferroelectric transistor serves as the first signal input terminal of the operation module, and the source of the ferroelectric transistor serves as the second signal input terminal of the operation module.

5. The ferroelectric transistor-based storage and calculation integrated comparison operation unit according to claim 4, characterized in that The output module includes a third NMOS transistor and a fourth NMOS transistor, the source of the third NMOS transistor serves as a low power connection terminal of the output module, the drain of the third NMOS transistor serves as a signal transmission terminal of the output module, the gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor and serves as a latch control terminal of the output module, the source of the fourth NMOS transistor serves as a signal input terminal of the output module, and the drain of the fourth NMOS transistor serves as a signal output terminal of the output module.

6. A comparator circuit implemented using the storage-computation integrated comparison operation unit according to claim 5, characterized in that include: The first storage-computation integrated comparison operation unit and the second storage-computation integrated comparison operation unit are configured such that the two ferroelectric transistors are uniformly initialized to a conducting state before the comparison operation starts; during the comparison operation, the two ferroelectric transistors respectively maintain or change their respective conducting states, thereby respectively performing a less-than comparison operation, and the two comparison results are respectively transmitted to the interlocking unit by the signal output terminals of the corresponding output modules in the form of voltage signals; An interlocking unit receives the voltage signals transmitted by the two output modules, and uses logic gates to implement static latching of the two voltage signals, and constructs a less than comparison path, an equal to comparison path, and a greater than comparison path, and obtains a less than comparison result, an equal to comparison result, and a greater than comparison result, respectively; A low-order suppression unit receives the equal comparison result fed back by the interlocking unit, performs a logical operation with the original operation control signal, outputs a unit operation control signal and transmits it to the first storage-computation-in-one comparison operation unit and the second storage-computation-in-one comparison operation unit, so as to suppress the transmission process of the low-order voltage signal to the first storage-computation-in-one comparison operation unit and the second storage-computation-in-one comparison operation unit when the comparison result of the high-order voltage signal is unequal in size, thereby eliminating redundant comparison.

7. The comparator circuit according to claim 6, characterized in that The first storage-computing integrated comparison operation unit and the second storage-computing integrated comparison operation unit are connected in parallel, the interlocking unit has a first signal input terminal and a second signal input terminal, a signal output terminal of the less than comparison path, a signal output terminal of the equal to comparison path, and a signal output terminal of the greater than comparison path, and the low-level suppression unit has a first signal input terminal and a second signal input terminal, and a signal output terminal; the first signal input terminal of the input module in the first storage-computing integrated comparison operation unit receives a first voltage signal, and the second signal input terminal receives a second voltage signal, the first signal input terminal of the input module in the second storage-computing integrated comparison operation unit receives a second voltage signal, and the second signal input terminal receives a first voltage signal, and the signal output terminal of the output module in the first storage-computing integrated comparison operation unit is connected to the interlocking unit. The first signal input terminal of the unit is connected, the signal output terminal of the output module in the second storage-computation-in-one comparison operation unit is connected to the second signal input terminal of the interlocking unit, the signal output terminal of the less than comparison path outputs a less than comparison result, the signal output terminal of the equal to comparison path outputs an equal to comparison result, the signal output terminal of the greater than comparison path outputs a greater than comparison result, the signal output terminal of the equal to comparison path is connected to the first signal input terminal of the low-level inhibition unit, the second signal input terminal of the low-level inhibition unit receives the original operation control signal, the signal output terminal of the low-level inhibition unit outputs the unit operation control signal, and the signal output terminal of the low-level inhibition unit is respectively connected to the operation control terminals of the input modules in the first storage-computation-in-one comparison operation unit and the second storage-computation-in-one comparison operation unit.

8. The comparator circuit according to claim 7, characterized in that The interlock unit includes a first interlock structure formed by connecting a first inverter and a second inverter end to end, a third inverter, a second interlock structure formed by connecting a fourth inverter and a fifth inverter end to end, a sixth inverter, and a first AND gate. The first interlock structure is used to temporarily lock the voltage signal output from the first storage-computation integrated comparison operation unit. The second interlock structure is used to temporarily lock the voltage signal output from the second storage-computation integrated comparison operation unit. The first interlock structure and the third inverter constitute the less than comparison path. The second interlock structure and the sixth inverter constitute the greater than comparison path. The first interlock structure, the second interlock structure, and the first AND gate constitute the equal comparison path. The input end of the first inverter is connected to the second inverter. The output end of the first inverter is connected to the input end of the second inverter and serves as the first signal input end of the interlock unit, the output end of the first inverter is connected to the input end of the second inverter and is respectively connected to the input end of the third inverter and the first input end of the first AND gate, the output end of the third inverter serves as the signal output end of the less than comparison path, the input end of the fourth inverter is connected to the output end of the fifth inverter and serves as the second signal input end of the interlock unit, the output end of the fourth inverter is connected to the input end of the fifth inverter and is respectively connected to the input end of the sixth inverter and the second input end of the first AND gate, the output end of the sixth inverter serves as the signal output end of the greater than comparison path, and the output end of the first AND gate serves as the signal output end of the equal to comparison path.

9. The comparator circuit according to claim 7 or 8, characterized in that The low-level suppression unit includes a second AND gate, wherein the first input end of the second AND gate serves as the first signal input end of the low-level suppression unit, the second input end of the second AND gate serves as the second signal input end of the low-level suppression unit, and the output end of the second AND gate serves as the signal output end of the low-level suppression unit.

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