Display substrate and display device

Abstract

The utility model provides a display substrate, belongs to the technical field of display, and can solve the problems of poor dark spots and the like caused by short circuit between an anode and a cathode due to the fact that an anode film layer at a T position of a tip structure is easy to fall off or adsorb foreign matters and the like, and a light-emitting layer is easy to pierce. The display substrate comprises a substrate body, an interlayer dielectric layer and a pixel unit, wherein the interlayer dielectric layer and the pixel unit are arranged on the substrate body. The pixel unit comprises a plurality of concave microstructures formed on the interlayer dielectric layer and a light-emitting device located on the side, away from the substrate body, of the interlayer dielectric layer. The array substrate is characterized in that for each pixel unit, a first area is defined by the multiple concave microstructures which are arranged adjacently, and the orthographic projection of the first electrode of the light-emitting device and the orthographic projection of the first area on the substrate do not overlap.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate. Background Art

[0002] As AMOLED (Active-matrix organic light emitting diode) display products gradually develop in the direction of high resolution and high brightness, higher light extraction efficiency is required. However, since the light emitted by the light-emitting components in OLED display products needs to pass through many film layers to enter the external environment, there are differences in refractive index between these film layers, which causes some light to be reflected in these film layers and cause light loss. In order to improve the luminous brightness of OLED products, the current mainstream technology is to introduce MLA (Microlens Array) technology in the substrate preparation process, and improve the light extraction effect by preparing the reflective surface into a concave mirror. However, how to form a regular concave shape faces many technical challenges. A common technical means is to etch the interlayer dielectric layer to form many regular and densely packed pits, and then deposit the anode after patterning to also have a concave shape. The subsequent light-emitting layer and cathode, etc., are all concave, so they will have a good divergence effect on the light emitted by the light-emitting layer, thereby significantly improving the light extraction effect, and then significantly improving the display quality of the display product. Utility Model Content

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and to provide a display substrate that can significantly improve the light extraction effect while avoiding problems such as dark spots.

[0004] In a first aspect, the present disclosure provides a display substrate, which includes a base substrate, an interlayer dielectric layer and a pixel unit arranged on the base substrate, wherein the pixel unit includes a plurality of concave microstructures formed on the interlayer dielectric layer, and a light-emitting device located on a side of the interlayer dielectric layer away from the base substrate; characterized in that:

[0005] For at least one of the pixel units, the plurality of adjacently arranged concave microstructures define a first region, and the first electrode of the light-emitting device has no overlap with the orthographic projection of the first region on the substrate.

[0006] Preferably, each of the concave microstructures and the two concave microstructures closest thereto define the first region.

[0007] Preferably, the width of the first region between adjacent concave microstructures is greater than or equal to 1 micrometer.

[0008] Preferably, the pixel unit further comprises a pixel driving circuit electrically connected to the first electrode of the light emitting device, the pixel driving circuit comprises a thin film transistor, and the thin film transistor is a top-gate thin film transistor.

[0009] Preferably, the pixel unit further includes a shading layer, which is arranged on a side of the active layer of the thin film transistor close to the base substrate, and the orthographic projection of the shading layer on the base substrate covers the orthographic projection of the active layer of the thin film transistor on the base substrate.

[0010] Preferably, the thin film transistor in the pixel unit includes a driving transistor, and a source of the driving transistor is electrically connected to the first electrode of the light emitting device and the light shielding layer.

[0011] Preferably, the display substrate further comprises a color resist layer disposed on a side of the interlayer dielectric layer close to the base substrate, and the orthographic projection of the color resist layer on the base substrate at least partially overlaps with the orthographic projection of the concave microstructure on the base substrate.

[0012] In a second aspect, the present disclosure further provides a display device, which includes the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a top view of an existing microlens array;

[0014] Figure 2 It is a structural schematic diagram of a microlens array substrate in the prior art;

[0015] Figure 3 A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0016] Figure 4 for Figure 3 A top view of a first electrode of a display substrate is disclosed;

[0017] Figure 5 A schematic diagram of a pixel driving circuit structure of a display substrate provided in an embodiment of the present disclosure;

[0018] Figure 6 A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure;

[0019] Figure 7a A schematic diagram of an intermediate product of step S1 of a method for preparing a display substrate provided in an embodiment of the present disclosure;

[0020] Figure 7b A schematic diagram of an intermediate product of step S2 of a method for preparing a display substrate provided in an embodiment of the present disclosure;

[0021] Figure 7c A schematic diagram of an intermediate product of step S3 of a method for preparing a display substrate provided in an embodiment of the present disclosure;

[0022] Figure 7d A schematic diagram of an intermediate product of step S4 of a method for preparing a display substrate provided in an embodiment of the present disclosure;

[0023] Figure 7e A schematic diagram of an intermediate product of step S5 of a method for preparing a display substrate provided in an embodiment of the present disclosure;

[0024] Figure 7f A schematic diagram of an intermediate product of step S7 of a method for preparing a display substrate provided in an embodiment of the present disclosure;

[0025] Figure 7g A schematic diagram of an intermediate product of step S7 of a method for preparing a display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0027] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0028] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0029] As AMOLED display products gradually develop in the direction of high resolution and high brightness, a higher light extraction rate is required. However, since the light emitted by the light-emitting components in OLED display products needs to pass through many film layers before entering the external environment, there are differences in the refractive index between these film layers, causing part of the light to be reflected in these film layers and causing light loss. In the prior art, in order to improve the luminous brightness of OLED products, MLA (Microlens Array) technology is mainly used in the substrate preparation process, and the light extraction effect is improved by preparing the reflective surface into a concave mirror. Figure 1 and Figure 2 As shown, the commonly used concave mirrors are regularly distributed on hemispherical surfaces, and the hemispheres are closely packed with each other so that they present a regular hexagonal distribution when viewed from above. A relatively high tip structure T is formed at the intersection of the three hemispheres. Subsequently, the anode film layer at the tip structure T is easy to fall off or absorb foreign matter, etc., which can easily lead to piercing the light-emitting layer and causing a short circuit between the anode and the cathode, thereby causing problems such as dark spots.

[0030] In the first aspect, the embodiment of the present disclosure provides a display substrate, which includes a base substrate 1, an interlayer dielectric layer 17 disposed on the base substrate 1, and a pixel unit, wherein the pixel unit includes a plurality of concave microstructures 18 formed on the interlayer dielectric layer 17, and a light-emitting device located on the side of the interlayer dielectric layer 17 away from the base substrate 1. It is characterized in that for each pixel unit, when the width of the first region 19 between the adjacent concave microstructures 18 is less than 1 micron, the adjacent multiple concave microstructures 18 define a first region 19, and it is characterized in that the first region 19 includes a tip structure T formed by extrusion of the multiple adjacent concave microstructures 18. The first electrode 20 of the light-emitting device and the tip structure T of the first region 19 have no overlap in their orthographic projection on the base substrate 1. The above-mentioned patterning method can well avoid the problem that the first electrode 20 at the first region 19 is easy to fall off or adsorb foreign matter, which causes the piercing of the light-emitting layer 21, resulting in a short circuit between the first electrode 20 and the second electrode 22, thereby causing problems such as dark spots. In addition, the interlayer dielectric layer 17 is etched to form many regularly and closely packed concave microstructures 18. Since the concave microstructure 18 has a concave shape, the first electrode 20 after deposition and patterning also has a concave shape. The light-emitting layer 21 and the second electrode 22 formed in sequence subsequently have a concave shape. Therefore, they have a good divergent effect on the light emitted by the light-emitting layer, thereby significantly improving the light extraction effect, and further significantly improving the display quality of the display product.

[0031] It should be noted that the interlayer dielectric layer 17 is a planarization layer, and the concave microstructure 18 is obtained by etching the side of the planarization layer away from the substrate base plate 1 .

[0032] In order to make the embodiments of the present disclosure more clear, the following describes them in conjunction with specific examples.

[0033] The present disclosure provides a display substrate, such as Figure 3As shown, it includes a base substrate 1, an interlayer dielectric layer 17 arranged on the base substrate 1, a color group layer 16 arranged on the side of the interlayer dielectric layer 17 close to the base substrate 1, and a pixel unit. It is characterized in that the pixel unit includes a light shielding layer 2, a pixel driving circuit, a concave microstructure 18 and a light-emitting device. It is characterized in that the light-emitting device includes a first electrode 20, a light-emitting layer 21 and a second electrode 22 arranged in sequence. For each pixel unit, a plurality of adjacently arranged concave microstructures 18 define a first area 19, and the first electrode 20 of the light-emitting device and the orthographic projection of the first area 19 on the base substrate 1 do not overlap. The above-mentioned patterning method can well avoid the problem that the first electrode 20 at the first area 19 is easy to fall off or adsorb foreign matter, which causes the light-emitting layer 21 to pierce, resulting in a short circuit between the first electrode 20 and the second electrode 22, thereby causing problems such as dark spots. The interlayer dielectric layer 17 is etched to form many regularly and closely packed concave microstructures 18. Since the concave microstructures 18 have a concave shape, the first electrode 20 after deposition and patterning also has a concave shape. The light-emitting layer 21 and the second electrode 22 formed in sequence subsequently have a concave shape, so they have a good divergent effect on the light emitted by the light-emitting layer, thereby significantly improving the light extraction effect, and further significantly improving the display quality of the display product.

[0034] It should be noted that the pixel driving circuit of the display substrate in the embodiment of the present disclosure adopts the following Figure 5 The pixel driving circuit of the 3T1C structure shown includes: a first transistor T1, a second transistor T2, a third transistor T3, a capacitor Cst and a light-emitting device OLED, and the light-emitting device OLED can be an organic light-emitting diode. It is characterized in that the source of the first transistor T1 is connected to the gate line DATA, the gate is connected to the first gate line G1, and the data line is connected to the gate of the third transistor T3; the source of the second transistor T2 is connected to the source of the third transistor T3, the gate is connected to the second gate line G2, and the drain is connected to the detection interface Sense; the source of the third transistor T3 is connected to the light-emitting device OLED, the gate is connected to the first transistor T1, and the drain is connected to the first power supply voltage VDD; the first plate of the capacitor Cst is connected to the drain of the first transistor T1, and the second plate is connected to the source of the second transistor T2; the first electrode of the light-emitting device OLED is connected to the ground electrode VSS, and the second electrode is connected to the source of the third transistor T3. The third transistor T3 is a driving transistor. The embodiment of the present application adopts a pixel driving circuit of the 3T1C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, uses fewer components, has a simple and stable structure, and saves costs.

[0035] In some examples, such as Figure 6As shown, the width of the gap between adjacent concave microstructures 18 is greater than or equal to 1 micron. Since there is no overlap between the concave microstructures 18, multiple flat structures F are formed in the gaps between multiple adjacent concave microstructures 18, thereby avoiding the adjacent concave microstructures 18 from being squeezed in the first area 19 to form a pointed structure T, fundamentally preventing the first electrode 20 in the first area 19 from easily falling off or absorbing foreign matter, which may cause the light-emitting layer 21 to be pierced, resulting in a short circuit between the first electrode 20 and the second electrode 22, thereby causing dark spots and other problems.

[0036] In some examples, the pixel driving circuit includes a thin film transistor, which is a top-gate thin film transistor. The top-gate thin film transistor has the characteristics of a short channel, so its on-state current can be effectively improved, thereby significantly improving the display effect and effectively reducing power consumption. In addition, the gate 6 of the top-gate thin film transistor has a small overlapping area with the source and drain, so the parasitic capacitance generated is small, so the possibility of dark spot defects is also reduced.

[0037] In some examples, the light shielding layer 2 is disposed on a side of the active layer 4 of the thin film transistor close to the base substrate 1, and the orthographic projection of the light shielding layer 2 on the base substrate 1 covers the orthographic projection of the active layer of the thin film transistor on the base substrate 1. In addition, the part where the orthographic projection of the active layer 4 on the base substrate 1 does not overlap with the orthographic projection of the gate insulating layer 5 on the base substrate 1 is processed by conductorization to form a conductor layer 7, and the lateral diffusion phenomenon when the active layer 4 is conductorized is used to increase the contact yield of the source electrode 10 and the drain electrode 9 with the conductor layer 7, that is, the contact yield with the edge of the active layer 4 is increased, thereby greatly improving the conduction characteristics of the thin film transistor device.

[0038] In some examples, the material of the active layer 4 of the thin film transistor includes indium gallium zinc oxide (IGZO), which has the advantages of high carrier mobility, large-area preparation, good uniformity, stable device performance, etc., and is compatible with the current amorphous silicon thin film transistor process, and is an ideal material in the display field.

[0039] In some examples, the color group layer 16 may include color filters of multiple colors, including: red filters, green filters and blue filters. The color filters can use filtering to produce the three primary colors of red (R), green (G), and blue (B), and then mix the three primary colors in different proportions to produce various colors, so that the display substrate appears colorful.

[0040] In some examples, the source electrode 10 of the driving transistor is electrically connected to the first electrode 20 of the light emitting device and the light shielding layer 2. In the embodiments of the present disclosure, the driving transistor can be used to regulate current and further control light emission.

[0041] In some examples, the first electrode 20 and the second electrode 22 materials include carbon nanotubes. Carbon nanotubes have a one-dimensional hollow tubular structure, the tube wall is surrounded by a single layer or multiple layers of graphene sheets, the tube diameter is nanometer-level, the tube length is micrometer-level, and the aspect ratio is huge. Its properties will change due to the different curling methods of the graphene sheets, reflecting metallic or semiconductor properties, and have good electrical conductivity. Secondly, carbon nanotubes have good thermal conductivity, and the axial thermal conductivity is 2000-3000W / mK, which is about 10 times that of copper and 3 times that of diamond. Thirdly, carbon nanotubes have a large specific surface area and strong adsorption performance; at the same time, they have good electromagnetic wave absorption and other properties.

[0042] In a second aspect, the present disclosure also provides a method for preparing a display substrate, such as Figure 6 As shown, including:

[0043] S1, such as Figure 7a As shown, a substrate 1 is provided.

[0044] S2, such as Figure 7b As shown, a patterned light shielding layer 2 is formed on a base substrate 1 .

[0045] In some examples, step S2 may specifically include:

[0046] S21 , forming a light shielding layer 2 on the base substrate 1 .

[0047] S22 , patterning the light shielding layer 2 through a composition process to form a patterned light shielding layer 2 .

[0048] Optionally, step S21 may specifically include:

[0049] A light shielding layer 2 is formed on the base substrate 1 by a physical vapor deposition process (PVD) or a chemical vapor deposition process (CVD) or a sputtering process, and the light shielding layer 2 is processed by a chemical mechanical polishing process, leaving only the required portion of the light shielding layer 2 to form a patterned light shielding layer 2.

[0050] S3, such as Figure 7c As shown, a buffer layer 3 covering the light shielding layer 2 is formed on the side of the light shielding layer 2 facing away from the substrate 1 .

[0051] Optionally, step S3 may specifically include:

[0052] A buffer layer 3 covering the light shielding layer 2 is formed on the substrate 1 at a side of the light shielding layer 2 facing away from the substrate 1 by a physical vapor deposition process (PVD) or a chemical vapor deposition process (CVD) or a sputtering process.

[0053] S4, such as Figure 7dAs shown, a thin film transistor including a driving transistor and an interlayer insulating layer 8 are formed on the side of the buffer layer 3 facing away from the substrate 1 .

[0054] In some examples, step S4 may specifically include:

[0055] S41 , forming a patterned active layer 4 on a side of the buffer layer 3 facing away from the substrate 1 .

[0056] In some examples, step S41 may specifically include:

[0057] S411 , forming an active layer 4 on a side of the buffer layer 3 facing away from the substrate 1 .

[0058] S412 , patterning the active layer 4 through a composition process, and the orthographic projection of the light shielding layer 2 on the base substrate 1 covers the orthographic projection of the active layer 4 on the base substrate 1 .

[0059] Optionally, step S411 may specifically include:

[0060] An active layer 4 is formed on the side of the buffer layer 3 facing away from the substrate 1 by a physical vapor deposition process (PVD) or a chemical vapor deposition process (CVD) or a sputtering process, and the active layer 4 is processed by a chemical mechanical polishing process, leaving only the required portion of the active layer 4, thereby forming a patterned active layer 4.

[0061] S42 , forming a gate insulating layer 5 on a side of the active layer 4 facing away from the substrate 1 .

[0062] Optionally, step S42 may specifically include:

[0063] The gate insulating layer 5 is formed on the side of the active layer 4 facing away from the substrate 1 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) or sputtering.

[0064] S43 , forming a gate 6 on the side of the gate insulating layer 5 facing away from the base substrate 1 .

[0065] Optionally, step S42 may specifically include:

[0066] The gate 6 is formed on the side of the gate insulating layer 5 facing away from the substrate 1 by a physical vapor deposition process (PVD) or a chemical vapor deposition process (CVD) or a sputtering process.

[0067] S44 , the portion where the orthographic projection of the active layer 4 on the base substrate 1 does not overlap with the orthographic projection of the gate insulating layer 5 on the base substrate 1 is conductively processed to form a conductive layer 7 .

[0068] Optionally, step S44 may specifically include:

[0069] The active layer 4 is subjected to plasma treatment in the area in contact with the source electrode 10 and the drain electrode 9 by using gases such as ar (argon) and helium (helium) to realize the process of making the active layer 4 conductive, thereby forming the conductive layer 7.

[0070] By utilizing the lateral diffusion phenomenon when the active layer 4 is conductive, the contact yield between the source electrode 10 and the drain electrode 9 and the edge of the active layer 4 is increased, thereby greatly improving the conduction characteristics of the thin film transistor device.

[0071] S45 , forming an interlayer insulating layer 8 on the side of the conductor layer 7 and the gate 6 facing away from the base substrate 1 , patterning the interlayer insulating layer 8 to form vias, and forming a drain electrode 9 and a source electrode 10 electrically connected to the conductor layer 7 .

[0072] In some examples, step S45 may specifically include:

[0073] S451 , forming an interlayer insulating layer 8 on the side of the conductor layer 7 and the gate 6 facing away from the base substrate 1 .

[0074] S452 , patterning the interlayer insulating layer 8 through a composition process to form a first via hole 11 and a second via hole 12 electrically connected to the conductor layer 7 , and a third via hole 13 connected to the light shielding layer 2 .

[0075] S453. A drain electrode 9 and a source electrode 10 are formed on the side of the interlayer insulating layer 8 facing away from the base substrate 1. The drain electrode 9 is electrically connected to the conductor layer 7 through the first via hole 11. The source electrode 10 is electrically connected to the conductor layer 7 through the second via hole 12. The source electrode 10 is also electrically connected to the light shielding layer 2 through the third via hole 13.

[0076] Optionally, step S451 may specifically include:

[0077] An interlayer insulating layer 8 is formed on the side of the conductor layer 7 and the gate 6 facing away from the substrate 1 by a physical vapor deposition process (PVD) or a chemical vapor deposition process (CVD) or a sputtering process.

[0078] Optionally, step S452 may specifically include:

[0079] The interlayer insulating layer 8 is patterned on a side facing away from the substrate 1 by an etching process to form a first via hole 11 and a second via hole 12 electrically connected to the conductor layer 7 , and a third via hole 13 connected to the light shielding layer 2 .

[0080] S5, such as Figure 7e As shown, a passivation layer 15 is formed on the side of the interlayer insulating layer 8 facing away from the substrate 1 .

[0081] Optionally, step S5 may specifically include:

[0082] The passivation layer 15 is formed on the side of the interlayer insulating layer 8 facing away from the substrate 1 by a physical vapor deposition process (PVD) or a chemical vapor deposition process (CVD) or a sputtering process.

[0083] S6, such as Figure 7f As shown, a color combination layer 16 is formed on the side of the passivation layer 15 facing away from the base substrate 1 , and the orthographic projection of the color combination layer 16 on the base substrate 1 does not overlap with the orthographic projection of the light shielding layer 2 on the base substrate 1 .

[0084] In some examples, step S6 may specifically include:

[0085] S61 , forming a red filter, a green filter and a blue filter on the side of the passivation layer 15 facing away from the base substrate 1 .

[0086] Optionally, step S6 may specifically include:

[0087] The color component layer 16 is formed on the side of the passivation layer 15 facing away from the substrate 1 by a physical vapor deposition process (PVD) or a chemical vapor deposition process (CVD) or a sputtering process.

[0088] S7, such as Figure 7g As shown, an interlayer dielectric layer 17 is formed on the side of the passivation layer 15 and the color group layer 16 facing away from the base substrate 1, and the interlayer dielectric layer 17 on the side facing away from the color group layer 16 is patterned to form a concave microstructure 18, and the orthographic projection of the concave microstructure 18 on the base substrate 1 does not overlap with the orthographic projection of the light shielding layer 2 on the base substrate 1.

[0089] In some examples, step S7 may specifically include:

[0090] S71 , forming an interlayer dielectric layer 17 on the side of the passivation layer 15 and the color group layer 16 facing away from the base substrate 1 .

[0091] S72, patterning the interlayer dielectric layer 17 and the passivation layer 15 by a patterning process to form a fourth via hole 14 connected to the source electrode 10. Patterning the interlayer dielectric layer 17 on the side away from the color group layer 16 to form a concave microstructure 18.

[0092] Optionally, step S71 may specifically include:

[0093] An interlayer dielectric layer 17 is formed on the side of the passivation layer 15 and the color group layer 16 facing away from the substrate 1 by a physical vapor deposition process (PVD) or a chemical vapor deposition process (CVD) or a sputtering process.

[0094] Since the interlayer dielectric layer is etched to form many regularly and closely packed concave microstructures 18 having a concave shape, the first electrode 20 after deposition and patterning also has a concave shape. The light-emitting layer 21 and the second electrode 22 formed subsequently have a concave shape, so they have a good divergent effect on the light emitted by the light-emitting layer 21, thereby significantly improving the light extraction effect, and further significantly improving the display quality of the display product.

[0095] Optionally, step S72 may specifically include:

[0096] The interlayer dielectric layer 17 is patterned by an etching process to form a fourth via hole 14 connected to the source electrode 10. The passivation layer 15 is patterned by an etching process to form a concave microstructure 18.

[0097] S8, such as Figure 3 As shown, a light emitting device is formed on the side of the interlayer dielectric layer 17 facing away from the substrate 1 .

[0098] In some examples, step S8 may specifically include:

[0099] S81 , forming a first electrode 20 on a side of the interlayer dielectric layer 17 facing away from the base substrate 1 , and a plurality of adjacently arranged concave microstructures 18 define a first region 19 , and the orthographic projections of the first electrode 20 and the first region 19 on the base substrate 1 do not overlap.

[0100] In some examples, step S81 may specifically include:

[0101] S811 , forming a first electrode 20 on a side of the interlayer dielectric layer 17 facing away from the base substrate 1 .

[0102] S812. Through a patterning process, remove the first electrode 20 located on the first region 19 and the first electrode 20 whose orthographic projection on the base substrate 1 overlaps with the orthographic projection of the light shielding layer 2 on the base substrate 1, so as to form a first electrode 20 located inside the fourth via hole 14 and on the side of the concave microstructure 18 facing away from the base substrate 1.

[0103] Optionally, step S811 may specifically include:

[0104] The first electrode 20 is formed on the side of the interlayer dielectric layer 17 away from the substrate 1 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) or sputtering.

[0105] Optionally, step S812 may specifically include:

[0106] The first electrode 20 is patterned by an etching process to form the first electrode 20 located inside the fourth via hole 14 and on the side of the concave microstructure 18 facing away from the substrate 1 .

[0107] For each pixel unit, when the width of the first region 19 between adjacent concave microstructures 18 is less than 1 micron, the adjacent multiple concave microstructures 18 define the first region 19, characterized in that the first region 19 includes a tip structure T formed by extrusion of the adjacent multiple concave microstructures 18. The above-mentioned patterning method can well avoid the problem of the first electrode 20 at the first region 19 easily falling off or adsorbing foreign matter, which causes the piercing of the light-emitting layer 21, resulting in a short circuit between the first electrode 20 and the second electrode 22, thereby causing problems such as dark spots.

[0108] S82 , forming a light-emitting layer 21 on a side of the first electrode 20 facing away from the base substrate 1 .

[0109] S83 , forming a second electrode 22 on the side of the light emitting layer 21 facing away from the base substrate 1 .

[0110] Optionally, step S82 may specifically include:

[0111] The light emitting layer 21 is formed on the side of the first electrode 20 away from the substrate 1 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) or sputtering.

[0112] Optionally, step S83 may specifically include:

[0113] The second electrode 22 is formed on the side of the light emitting layer 21 away from the substrate 1 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) or sputtering.

[0114] It should be noted that the pixel driving circuit of the display substrate in the embodiment of the present disclosure adopts the following Figure 5The pixel driving circuit of the 3T1C structure shown includes: a first transistor T1, a second transistor T2, a third transistor T3, a capacitor Cst and a light-emitting device OLED, and the light-emitting device OLED can be an organic light-emitting diode. It is characterized in that the source of the first transistor T1 is connected to the gate line DATA, the gate is connected to the first gate line G1, and the data line is connected to the gate of the third transistor T3; the source of the second transistor T2 is connected to the source of the third transistor T3, the gate is connected to the second gate line G2, and the drain is connected to the detection interface Sense; the source of the third transistor T3 is connected to the light-emitting device OLED, the gate is connected to the first transistor T1, and the drain is connected to the first power supply voltage VDD; the first plate of the capacitor Cst is connected to the drain of the first transistor T1, and the second plate is connected to the source of the second transistor T2; the first electrode of the light-emitting device OLED is connected to the ground electrode VSS, and the second electrode is connected to the source of the third transistor T3. The third transistor T3 is a driving transistor. The embodiment of the present application adopts a pixel driving circuit of the 3T1C structure to effectively compensate the threshold voltage of the driving transistor in each pixel, uses fewer components, has a simple and stable structure, and saves costs.

[0115] In some examples, such as Figure 6 As shown, the width of the gap between adjacent concave microstructures 18 is greater than or equal to 1 micron. Since there is no overlap between the concave microstructures 18, multiple flat structures F are formed in the gaps between multiple adjacent concave microstructures 18, thereby avoiding the adjacent concave microstructures 18 from being squeezed in the first area 19 to form a pointed structure T, fundamentally preventing the first electrode 20 in the first area 19 from easily falling off or absorbing foreign matter, which may cause the light-emitting layer 21 to be pierced, resulting in a short circuit between the first electrode 20 and the second electrode 22, thereby causing dark spots and other problems.

[0116] In some examples, the pixel driving circuit includes a thin film transistor, which is a top-gate thin film transistor. The top-gate thin film transistor has the characteristics of a short channel, so its on-state current can be effectively improved, thereby significantly improving the display effect and effectively reducing power consumption. In addition, the gate 6 of the top-gate thin film transistor has a small overlapping area with the source and drain, so the parasitic capacitance generated is small, so the possibility of dark spot defects is also reduced.

[0117] In some examples, the light shielding layer 2 is disposed on a side of the active layer 4 of the thin film transistor close to the base substrate 1, and the orthographic projection of the light shielding layer 2 on the base substrate 1 covers the orthographic projection of the active layer of the thin film transistor on the base substrate 1. In addition, the part where the orthographic projection of the active layer 4 on the base substrate 1 does not overlap with the orthographic projection of the gate insulating layer 5 on the base substrate 1 is processed by conductorization to form a conductor layer 7, and the lateral diffusion phenomenon when the active layer 4 is conductorized is used to increase the contact yield of the source electrode 10 and the drain electrode 9 with the conductor layer 7, that is, the contact yield with the edge of the active layer 4 is increased, thereby greatly improving the conduction characteristics of the thin film transistor device.

[0118] In some examples, the material of the active layer 4 of the thin film transistor includes indium gallium zinc oxide (IGZO), which has the advantages of high carrier mobility, large-area preparation, good uniformity, stable device performance, etc., and is compatible with the current amorphous silicon thin film transistor process, and is an ideal material in the display field.

[0119] In some examples, the color group layer 16 may include color filters of multiple colors. The color filters may generate the three primary colors of red (R), green (G), and blue (B) by filtering light, and then mix the three primary colors in different proportions to generate various colors, so that the display substrate appears colorful.

[0120] In some examples, the source electrode 10 of the driving transistor is electrically connected to the first electrode 20 of the light emitting device and the light shielding layer 2. In the embodiments of the present disclosure, the driving transistor can be used to regulate current and further control light emission.

[0121] In some examples, the first electrode 20 and the second electrode 22 materials include carbon nanotubes. Carbon nanotubes have a one-dimensional hollow tubular structure, the tube wall is surrounded by a single layer or multiple layers of graphene sheets, the tube diameter is nanometer-level, the tube length is micrometer-level, and the aspect ratio is huge. Its properties will change due to the different curling methods of the graphene sheets, reflecting metallic or semiconductor properties, and have good electrical conductivity. Secondly, carbon nanotubes have good thermal conductivity, and the axial thermal conductivity is 2000-3000W / mK, which is about 10 times that of copper and 3 times that of diamond. Thirdly, carbon nanotubes have a large specific surface area and strong adsorption performance; at the same time, they have good electromagnetic wave absorption and other properties.

[0122] The present disclosure also provides a display device, which includes the display substrate of any one of the above embodiments. The display device can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, or any other product with a display function. Other essential components of the display device should be understood by a person of ordinary skill in the art, and will not be described in detail here, nor should they be used as a limitation to the present disclosure.

[0123] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a base substrate, an interlayer dielectric layer and a pixel unit arranged on the base substrate, wherein the pixel unit comprises a plurality of concave microstructures formed on the interlayer dielectric layer, and a light-emitting device located on a side of the interlayer dielectric layer away from the base substrate; characterized in that: For at least one of the pixel units, the plurality of adjacently arranged concave microstructures define a first region, and the first electrode of the light-emitting device has no overlap with the orthographic projection of the first region on the substrate.

2. The display substrate according to claim 1, characterized in that: Each of the concave microstructures and the two concave microstructures closest thereto define the first region.

3. The display substrate according to claim 1, characterized in that: The width of the first region between the adjacent concave microstructures is greater than or equal to 1 micrometer.

4. The display substrate according to claim 1, characterized in that: The pixel unit further includes a pixel driving circuit electrically connected to the first electrode of the light emitting device. The pixel driving circuit includes a thin film transistor, and the thin film transistor is a top-gate thin film transistor.

5. The display substrate according to claim 4, characterized in that: The pixel unit further includes a light shielding layer, which is arranged on a side of the active layer of the thin film transistor close to the base substrate, and the orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the active layer of the thin film transistor on the base substrate.

6. The display substrate according to claim 5, characterized in that: The thin film transistor in the pixel unit includes a driving transistor, and a source of the driving transistor is electrically connected to the first electrode of the light emitting device and the light shielding layer.

7. The display substrate according to claim 1, characterized in that: It also includes a color resist layer disposed on a side of the interlayer dielectric layer close to the base substrate, wherein the orthographic projection of the color resist layer on the base substrate at least partially overlaps with the orthographic projection of the concave microstructure on the base substrate.

8. A display device, characterized in that: Comprising the display substrate according to any one of claims 1 to 7.

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