Control circuit of motor controller and motor controller
By designing a motor controller control circuit including fault input processing circuit, latch output circuit, controller and output processing circuit, the problem of low response speed of existing motor controllers is solved, and the motor failure is quickly responded to, and the system response speed and safety is improved.
Patent Information
- Application Number
- CN202420944309.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-30
- Publication Date
- 2025-03-11
- Estimated Expiration
- 2034-04-30
AI Technical Summary
The existing motor controller has low response speed and is difficult to deal with motor failures quickly.
A motor controller control circuit including a fault input processing circuit, a latch output circuit, a controller and an output processing circuit are designed. The control circuit quickly processes multiple status signals through the hardware circuit structure and outputs processing signals to the power device to ensure that the system responds quickly in the event of a failure.
It improves the response speed of the motor controller system, ensures that the power device can be quickly shut down when a fault occurs, and improves the safety and stability of the system.
Smart Images
Figure CN222602293U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of motor controllers, and in particular to a control circuit of a motor controller and a motor controller. Background Art
[0002] At present, the motor controller of new energy vehicles generally controls the motor torque and speed through the SVPWM (Space Vector Pulse Width Modulation) control strategy. In traditional technology, the operation of the motor controller system is monitored by sensors or detection circuits, and the detected fault information is sent to the main control chip, which stops the output of the PWM (Pulse Width Modulation) waveform to achieve the shutdown of the power device. However, this traditional technical solution has a low response speed. Utility Model Content
[0003] Based on this, it is necessary to provide a control circuit and a motor controller with a fast response speed.
[0004] In a first aspect, a control circuit of a motor controller is provided, the control circuit comprising:
[0005] A fault input processing circuit, wherein the multiple input terminals of the fault input processing circuit are respectively used to correspond to the multiple state signals connected to the motor controller, and the fault input processing circuit is used to output a first signal when the multiple state signals match the multiple state signals output by the motor controller when the motor controller works normally;
[0006] A latch output circuit, wherein an input end of the latch output circuit is connected to an output end of the fault input processing circuit; the latch output circuit is used to shut down when receiving a first signal;
[0007] A controller, the controller is used to output a plurality of pulse width modulation signals;
[0008] An output processing circuit, wherein multiple first input terminals of the output processing circuit are connected to multiple first output terminals of the controller, multiple second input terminals of the output processing circuit are connected to the output terminals of the latch output circuit, and multiple first output terminals of the output processing circuit are used to connect to power devices. The output processing circuit is used to output multiple processed signals to the power devices according to each pulse width modulation signal when the latch output circuit is in the off state.
[0009] In one embodiment, the control circuit of the motor controller further includes:
[0010] A reset circuit, wherein an input end of the reset circuit is connected to a second output end of the controller;
[0011] A latch circuit, wherein a first input end of the latch circuit is connected to a fault input processing circuit, a second input end of the latch circuit is connected to an output end of a reset circuit, and an output end of the latch circuit is connected to a latch output circuit, so as to drive the latch output circuit to shut down when the reset circuit receives a reset signal output by a controller and the fault input processing circuit outputs a first signal.
[0012] In one embodiment, the latch output circuit comprises:
[0013] A first transistor, wherein the first end of the first transistor is connected to the output end of the latch circuit, the second end of the first transistor is used to connect to an external power supply, and the three ends of the first transistor are grounded; the first transistor is turned off when the reset circuit receives a reset signal output by the controller and the fault input processing circuit outputs a first signal.
[0014] In one embodiment, the reset circuit comprises:
[0015] The second transistor, the first end of the second transistor is connected to the second output end of the controller, the second end of the second transistor is used to connect to the external power supply, and the third end of the second transistor is grounded; the second transistor is used to be turned on when receiving a reset signal.
[0016] In one embodiment, the fault input processing circuit is used to output a second signal when the multiple status signals do not match the multiple status signals output when the motor controller works normally; wherein the second signal has a high and low level state opposite to that of the first signal.
[0017] In one embodiment, when the control circuit of the motor controller includes a latch circuit, the latch circuit is used to drive the latch output circuit to conduct when the fault input processing circuit outputs the second signal.
[0018] In one embodiment, the first input terminal of the controller is connected to the output terminal of the latch output circuit, and the controller is further configured to output a reset signal when the latch output circuit is turned on.
[0019] In one embodiment, the second input terminal of the controller is used to receive multiple status signals; the controller is also used to generate and send alarm information when the multiple status signals do not match the multiple status signals output by the motor controller when it works normally.
[0020] In one embodiment, the output processing circuit includes:
[0021] A plurality of AND gates, a first input end of each AND gate is connected to a first output end of the controller, a second input end of each AND gate is connected to an output end of a latch output circuit, and an output end of each AND gate is used to connect to a power device.
[0022] In a second aspect, a motor controller is provided, comprising the control circuit of the motor controller mentioned above.
[0023] The control circuit of the motor controller and the motor controller include a fault input processing circuit, a latch output circuit, a controller and an output processing circuit. When the fault input processing circuit outputs a first signal to the latch output circuit, the latch output circuit is turned off, and the output processing circuit outputs multiple processing signals to the power device according to the multiple pulse width modulation signals output by the controller to maintain the normal operation of the system equipped with the control circuit of the motor controller. The control circuit of the motor controller is a hardware circuit structure, which can improve the response speed of the system equipped with the control circuit of the motor controller compared to the software implementation scheme in the traditional way. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0025] Figure 1 One of the control circuit module structures of a motor controller of an embodiment;
[0026] Figure 2 This is a second control circuit module structure of a motor controller in one embodiment. DETAILED DESCRIPTION
[0027] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0029] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first transistor may be referred to as a second transistor, and similarly, a second transistor may be referred to as a first transistor. Both the first transistor and the second transistor are transistors, but they are not the same transistor.
[0030] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.
[0031] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least part of an element” means part or all of an element.
[0032] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.
[0033] In one embodiment, Figure 1 As shown, a control circuit of a motor controller is provided. The control circuit 100 includes: a fault input processing circuit 102 , a latch output circuit 104 , a controller 106 and an output processing circuit 108 .
[0034] Among them, multiple input terminals of the fault input processing circuit 102 are used to respectively correspond to multiple status signals connected to the motor controller, and the fault input processing circuit 102 is used to output a first signal when the multiple status signals match the multiple status signals output by the motor controller when working normally.
[0035] An input end of the latch output circuit 104 is connected to an output end of the fault input processing circuit 102 ; the latch output circuit 104 is used to shut down when receiving the first signal.
[0036] The controller 106 is configured to output a plurality of pulse width modulation signals.
[0037] Multiple first input terminals of the output processing circuit 108 are connected to multiple first output terminals of the controller 106, multiple second input terminals of the output processing circuit 108 are connected to the output terminal of the latch output circuit 104, and multiple first output terminals of the output processing circuit 108 are used to connect to the power device 200. The output processing circuit 108 is used to output multiple processed signals to the power device according to each pulse width modulation signal when the latch output circuit 104 is in the off state.
[0038] like Figure 1 As shown, the multiple status signals of the motor controller include I_Flt (hardware overcurrent fault signal, CurrentFault), V_Flt (bus overvoltage fault signal, Voltage Fault), Fault_H (IGBT (insulated gate bipolar transistor, Insulated Gate Bipolar Transistor) drive upper bridge fault signal, Fault High), Fault_L (IGBT drive lower bridge fault signal, Fault Low), Re_Flt (rotating transformer fault signal, Resistance Fault), Tep_Flt (IGBT overtemperature fault signal, Temperature Fault). These status signals are compared one by one with the multiple status signals output by the motor controller when it is working normally in real time, so as to determine whether the motor controller is in a normal working state. Multiple different status signals can quickly determine the type of fault that occurs in the motor controller when the motor controller is in an abnormal working state.
[0039] When the fault input processing circuit 102 outputs the first signal when the multiple state signals match the multiple state signals output by the motor controller when the motor controller is working normally, it can be a level signal. Specifically, the first signal can be a high level signal. Of course, the first signal can also be other types of preset signals, which are not limited here.
[0040] The output processing circuit 108 generates one-to-one corresponding processing signals according to the multiple pulse width modulation signals output by the controller 106. The multiple processing signals are signals for driving the upper bridge and / or the lower bridge in the motor to enter the on or off state. In one embodiment, a new energy vehicle equipped with the control circuit 100 of the motor controller is taken as an example for explanation. When multiple processing signals drive the upper bridge and the lower bridge of the motor of the new energy vehicle to enter the on state, the new energy vehicle enters the driving state; when multiple processing signals drive the upper bridge and / or the lower bridge of the motor of the new energy vehicle to enter the off state, the new energy vehicle exits the driving state; specifically, each processing signal includes PWM_UH (pulse width modulation upper high signal, Pulse Width Modulation Upper High), PWM_UL (pulse width modulation upper low signal, Pulse Width ModulationUpper Low), PWM_VH (pulse width modulation voltage upper high signal, Pulse Width ModulationVoltageHigh), PWM_VL (pulse width modulation voltage upper low signal, Pulse Width ModulationVoltage Low), PWM_WH (pulse width modulation waveform upper high signal, Pulse Width Modulation Waveform High) and PWM_WL (pulse width modulation waveform upper low signal, Pulse Width ModulationWaveform Low).
[0041] In the case where the fault input processing circuit 102 outputs the first signal to the latch output circuit 104, the latch output circuit 104 is turned off so as not to affect the output processing circuit 108 outputting multiple processed signals to the power device according to the multiple pulse width modulation signals output by the controller 106, so as to maintain the normal operation of the system equipped with the control circuit 100 of the motor controller. The control circuit 100 of the motor controller is a hardware circuit structure, which can improve the response speed of the system equipped with the control circuit 100 of the motor controller.
[0042] In one embodiment, Figure 2 As shown, the control circuit 100 of the motor controller further includes: a reset circuit 110 and a latch circuit 112 .
[0043] The input end of the reset circuit 110 is connected to the second output end of the controller 106 .
[0044] A first input end of the latch circuit 112 is connected to the fault input processing circuit 102, a second input end of the latch circuit 112 is connected to the output end of the reset circuit 110, and an output end of the latch circuit 112 is connected to the latch output circuit 104, so as to drive the latch output circuit 104 to turn off when the reset circuit 110 receives a reset signal output by the controller 106 and the fault input processing circuit 102 outputs a first signal.
[0045] The control circuit 100 of the motor controller may be as follows Figure 2 The fault input processing circuit 102 outputs a first signal to the latch circuit 112 when receiving multiple state signals that match the multiple state signals output by the motor controller when the motor controller is working normally; in this case, the latch circuit 112 also receives a reset signal ( Figure 2 When the reset circuit 110 outputs a signal (MCU_Rst signal in the reset circuit 110), the latch circuit 112 drives the latch output circuit 104 to turn off. The signal output by the reset circuit 110 may be a level signal, specifically, the signal may be a low level.
[0046] In one embodiment, the reset signal may be a high-level pulse of 50 ms, or a signal of other configurations, which may be set according to actual needs.
[0047] In one embodiment, Figure 2 As shown, the latch output circuit 104 includes a first transistor 1042 .
[0048] The first end of the first transistor 1042 is connected to the output end of the latch circuit 112, the second end of the first transistor 1042 is used to connect to an external power supply, and the three ends of the first transistor 1042 are grounded; the first transistor 1042 is turned off when the reset circuit 110 receives the reset signal output by the controller 106 and the fault input processing circuit 102 outputs the first signal.
[0049] In one embodiment, the latch circuit 112 includes: Figure 2 The NAND gate latch shown, the truth table of the NAND gate latch can be seen in the table below.
[0050]
[0051] Specifically, Figure 2 The latch circuit 112 of the NAND latch shown in FIG. 1 is used as an example to illustrate that if the first signal is a high level, the reset circuit 110 outputs a low level according to the reset signal. When the fault input processing circuit 102 outputs a high level, Figure 2 The potential at point A is pulled up, showing a high level; when the reset circuit 110 outputs a low level according to the reset signal, Figure 2 The potential at point B is low level; the latch circuit 112 of the NAND gate structure in the figure outputs a low level in this case, that is, at this time, Figure 2 The potential at point C is pulled down, showing a low level; at this time, the first transistor 1042 of the latch output circuit 104 is turned off. Figure 2 The potential at point D is pulled up by the external power supply and is shown as a high level. Of course, the latch circuit 112 can also be a circuit with other structures having the same operation logic, which will not be described in detail here.
[0052] In one embodiment, Figure 2 As shown, the reset circuit 110 includes a second transistor 11021102.
[0053] A first end of the second transistor 1102 is connected to a second output end of the controller 106 , a second end of the second transistor 1102 is used to connect to an external power supply, and a third end of the second transistor 1102 is grounded; the second transistor 1102 is used to be turned on when receiving a reset signal.
[0054] The second transistor 1102 is turned on when receiving a reset signal. Figure 2 Point B is grounded, and its potential is pulled down, showing a low level; the second transistor 1102 is turned off without receiving a reset signal. At this time, Figure 2 When point B is connected to an external power supply, its potential is pulled up, showing a high level.
[0055] In one embodiment, the fault input processing circuit 102 is used to output a second signal when the multiple status signals do not match the multiple status signals output by the motor controller when the motor controller works normally; wherein the high and low level states of the second signal are opposite to those of the first signal.
[0056] When the first signal is at a high level, the second signal is at a low level. When at least one state signal input to the fault input processing circuit 102 does not match the state signal output by the motor controller when it is working normally, the fault input processing circuit 102 outputs a low level, i.e. Figure 2 The potential at point A is low.
[0057] In one embodiment, when the control circuit 100 of the motor controller includes the latch circuit 112 , the latch circuit 112 is used to drive the latch output circuit 104 to turn on when the fault input processing circuit 102 outputs the second signal.
[0058] When the fault input processing circuit 102 outputs the second signal of low level, it can be seen from the truth table of the NAND latch that the latch circuit 112 outputs high level. At this time, the latch output circuit 104 is turned on. Figure 2The potential at the point D is grounded, which is a low level. At this time, the latch output circuit 104 no longer outputs a plurality of processed signals to the power device according to each pulse width modulation signal.
[0059] As shown in the truth table of the NAND latch described above, only when the latch circuit 112 receives the high-level first signal and the low-level output of the reset circuit 110, will the latch output circuit 104 be driven to output multiple processing signals to the power device according to each pulse width modulation signal. Therefore, the latch circuit 112 can ensure that when any fault occurs, the output of the processing signal can be stopped in time, thereby turning off the power device to ensure that the power device will not work in a fault environment, thereby improving the safety of the power device. At the same time, the hardware circuit can make the above control process faster, so as to turn off the power device in the shortest time.
[0060] In one embodiment, the first input terminal of the controller 106 is connected to the output terminal of the latch output circuit 104 , and the controller 106 is further configured to output a reset signal when the latch output circuit 104 is turned on.
[0061] When the latch output circuit 104 is turned off, multiple status signals of the input fault input processing circuit 102 match multiple status signals output by the motor controller when it is working normally. At this time, the motor controller has no fault and is in a normal working state; when the latch output circuit 104 is turned on, at least one status signal in the input fault input processing circuit 102 does not match the status signal output by the motor controller when it is working normally. At this time, the motor controller fails and is in an abnormal working state; therefore, the controller 106 can determine whether the motor controller has resumed normal working state by detecting the signal state at the output end of the latch output circuit 104.
[0062] As shown in the truth table of the NAND latch described above, the signal at the output end of the latch output circuit 104 is EM_Stop. Specifically, when EM_Stop is at a high level, the latch output circuit 104 is in an off state, and it can be determined that the motor controller has no fault and is in a normal working state. Specifically, when EM_Stop is at a low level, the latch output circuit 104 is in an on state, and it can be determined that the motor controller has a fault and is in an abnormal working state; in order to restore the normal operation of the motor controller, at this time, the controller 106 can output a reset signal to the reset circuit 110 when the latch output circuit 104 is turned on, so that the motor controller can output a first signal to drive the latch output circuit 104 to turn off after the fault is eliminated and the normal working state is restored, and then the output processing circuit 108 outputs multiple processing signals to the power device according to the multiple pulse width modulation signals output by the controller 106.
[0063] Through the above-mentioned settings, when a fault occurs in the motor controller, the output of multiple processing signals to the power device can be stopped in time through the hardware circuit; and the output signal of the fault input processing circuit 102 and the output signal of the reset circuit 110 are latched in the latch circuit 112, which can avoid repeated prohibition of outputting multiple processing signals due to repeated occurrence of the fault, and ensure that the output of multiple processing signals is restored only when the fault disappears completely and the controller 106 outputs a reset signal.
[0064] In one embodiment, the second input terminal of the controller 106 is used to receive multiple status signals; the controller 106 is also used to generate and send an alarm message when the multiple status signals do not match the multiple status signals output by the motor controller when the motor controller works normally.
[0065] In the event of a motor controller failure, an alarm message is generated and sent in a timely manner to prompt the staff to handle the failure as soon as possible, so as to improve the safety of the system of the control circuit 100 equipped with the motor controller.
[0066] In one embodiment, Figure 2 As shown, the output processing circuit 108 includes a plurality of AND gates (U6-U11).
[0067] The first input terminal of each AND gate is connected to the first output terminal of the controller 106 , the second input terminal of each AND gate is connected to the output terminal of the latch output circuit 104 , and the output terminal of each AND gate is used to connect to a power device.
[0068] Taking the AND gate U6 as an example, when the latch output circuit 104 is in the off state, Figure 2 The point D in the middle is at a high level. At this time, the AND gate U6 outputs a processing signal according to the high level output by the latch output circuit 104 and the pulse width modulation signal output by the controller 106; when the latch output circuit 104 is in the on state, Figure 2 The point D in the middle is at a low level, and the AND gate U6 does not output at this time, that is, the output processing signal is prohibited at this time.
[0069] The working logic of other AND gates in the output processing circuit 108 is consistent with that of the AND gate U6 and will not be described in detail here.
[0070] In one embodiment, a motor controller is provided, including the motor controller control circuit 100 as described above. The motor controller control circuit 100 can control the motor controller to stop running when the motor controller fails, and the motor controller control circuit 100 with a hardware circuit structure can make the response speed faster.
[0071] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.
[0072] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0073] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A control circuit of a motor controller, characterized in that: include: A fault input processing circuit, wherein a plurality of input terminals of the fault input processing circuit are respectively used to correspond to a plurality of status signals connected to the motor controller, and the fault input processing circuit is used to output a first signal when the plurality of status signals match a plurality of status signals output by the motor controller when the motor controller is working normally; a latch output circuit, wherein an input end of the latch output circuit is connected to an output end of the fault input processing circuit; the latch output circuit is configured to be turned off upon receiving the first signal; A controller, the controller being used to output a plurality of pulse width modulation signals; An output processing circuit, wherein a plurality of first input terminals of the output processing circuit are connected to a plurality of first output terminals of the controller, a plurality of second input terminals of the output processing circuit are connected to an output terminal of the latch output circuit, a plurality of first output terminals of the output processing circuit are used to connect to a power device, and the output processing circuit is used to output a plurality of processing signals to the power device according to each of the pulse width modulation signals when the latch output circuit is in the off state.
2. The control circuit of the motor controller according to claim 1, characterized in that: The control circuit of the motor controller also includes: A reset circuit, wherein an input end of the reset circuit is connected to a second output end of the controller; A latch circuit, wherein a first input end of the latch circuit is connected to the fault input processing circuit, a second input end of the latch circuit is connected to the output end of the reset circuit, and the output end of the latch circuit is connected to the latch output circuit, so as to drive the latch output circuit to turn off when the reset circuit receives a reset signal output by the controller and the fault input processing circuit outputs a first signal.
3. The control circuit of the motor controller according to claim 2, characterized in that: The latch output circuit comprises: A first transistor, wherein a first end of the first transistor is connected to an output end of the latch circuit, a second end of the first transistor is used to connect to an external power supply, and three ends of the first transistor are grounded; the first transistor is turned off when the reset circuit receives a reset signal output by the controller and the fault input processing circuit outputs a first signal.
4. The control circuit of the motor controller according to claim 2, characterized in that: The reset circuit comprises: A second transistor, wherein the first end of the second transistor is connected to the second output end of the controller, the second end of the second transistor is used to connect to an external power supply, and the third end of the second transistor is grounded; the second transistor is used to be turned on when receiving the reset signal.
5. The control circuit of the motor controller according to any one of claims 1 to 4, characterized in that: The fault input processing circuit is used to output a second signal when the multiple status signals do not match the multiple status signals output when the motor controller works normally; wherein the second signal has a high and low level state opposite to that of the first signal.
6. The control circuit of the motor controller according to claim 5, characterized in that: In the case where the control circuit of the motor controller includes a latch circuit, the latch circuit is used to drive the latch output circuit to conduct when the fault input processing circuit outputs the second signal.
7. The control circuit of the motor controller according to claim 2, characterized in that: The first input terminal of the controller is connected to the output terminal of the latch output circuit, and the controller is further used to output the reset signal when the latch output circuit is turned on.
8. The control circuit of the motor controller according to claim 2, characterized in that: The second input terminal of the controller is used to receive a plurality of status signals; the controller is also used to generate and send an alarm message when the plurality of status signals do not match the plurality of status signals outputted when the motor controller is working normally.
9. The control circuit of the motor controller according to claim 1, characterized in that: The output processing circuit comprises: A plurality of AND gates, wherein the first input end of each AND gate is connected to the first output end of the controller, the second input end of each AND gate is connected to the output end of the latch output circuit, and the output end of each AND gate is used to connect to the power device.
10. A motor controller, characterized in that: A control circuit comprising the motor controller according to any one of claims 1-9.