Multi-mode verification UART circuit and integrated circuit chip
By introducing a mode selection controller and a verification selection module in the UART circuit, multi-mode communication and multiple verification types are realized, solving the problem of insufficient applicability and compatibility of traditional UARTs, and improving the flexibility and security of data transmission.
Patent Information
- Application Number
- CN202421285699.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-06
- Publication Date
- 2025-03-11
- Estimated Expiration
- 2034-06-06
AI Technical Summary
The communication method of traditional UART is single and lacks multi-mode verification function, resulting in insufficient applicability and communication compatibility in different application scenarios.
A UART circuit for multi-mode verification is designed, including a mode selection controller and a calibration selection module. It can operate in full-duplex communication, single-line sending or single-line receiving modes, and supports multiple verification types such as no-calcification, parity, accumulation and verification and CRC verification.
It realizes the flexibility and applicability of UART circuits in different scenarios, providing a higher level of data transmission security.
Smart Images
Figure CN222602403U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the UART field, in particular to a multi-mode verification UART circuit and an integrated circuit chip. Background Art
[0002] UART (Universal Asynchronous Receiver / Transmitter) is a universal serial data bus used for asynchronous communication. The bus has bidirectional communication and can achieve full-duplex transmission and reception. In embedded design, UART is used to communicate with the PC, including monitoring debuggers and other devices such as EEPROM.
[0003] The traditional UART communication mode is relatively simple, which is not conducive to different application scenarios. Secondly, the traditional UART usually does not have a verification function, or only has one verification function. In some specific scenarios, it is impossible to select verification types with different security levels, and the communication compatibility needs to be improved. Summary of the invention
[0004] In order to solve the problems existing in the background technology, the utility model proposes a UART circuit and an integrated circuit chip with multi-mode verification.
[0005] A multi-mode verification UART circuit, comprising:
[0006] The sending module is configured to connect the communication bus interface and the sending port, and is used to receive the data sent by the communication bus and perform parallel-to-serial processing and then send it to the receiving device through the sending port;
[0007] The receiving module is configured to connect the communication bus interface and the receiving port, and is used to receive data sent from the outside, perform serial conversion, process, and then send to the communication bus;
[0008] A control register configured to be connected to the communication bus interface, the mode selection controller and the check selection module respectively, and used to control the mode selection controller and the check selection module according to a control instruction sent by the communication bus;
[0009] A mode selection controller, configured to control the connection between the sending module and the receiving module respectively, and used to control the working mode of the sending module and the receiving module;
[0010] The check selection module is configured to be connected to the sending module and the receiving module respectively, and is used to select the check type, and to add a check bit to the sending data of the sending module and to check the receiving data of the receiving module.
[0011] Based on the above, the sending module is connected to the communication bus interface via a sending data register, and the sending data register is used to store the received data.
[0012] Based on the above, the sending module includes a sending control logic module, a sending FIFO and a sending serial shift register. The sending control logic module controls the connection between the sending FIFO and the sending serial shift register respectively, and the sending control logic module is used to control the working mode of the sending FIFO and the sending serial shift register; the sending FIFO receives and temporarily stores the data sent by the communication bus, and the sending serial shift register is used to perform parallel-to-serial processing on the data transmitted by the sending FIFO and send it to the sending port.
[0013] Based on the above, the receiving module is connected to the communication bus interface via a receiving data register, and the receiving data register is used to store data to be sent to the communication bus.
[0014] Based on the above, the receiving module includes a receiving control logic module, a receiving FIFO and a receiving serial shift register. The receiving control logic module controls the connection between the receiving FIFO and the receiving serial shift register respectively, and the receiving control logic module is used to control the working mode of the receiving FIFO and the receiving serial shift register; the receiving FIFO receives and temporarily stores data sent from the outside, and the receiving serial shift register is used to serially convert the data transmitted by the receiving FIFO and send it to the communication bus after processing.
[0015] Based on the above, a baud rate generator is included, which is configured to be connected to a control register, a clock source, a sending module and a receiving module respectively, for receiving clock information and providing a clock signal to the sending module and the receiving module according to a control instruction of the control register.
[0016] Based on the above, the check types of the check selection module at least include no check, parity check, cumulative check and CRC check.
[0017] Based on the above, the mode selection controller controls the working mode of the sending module to include a sending mode and a shutdown mode, and the mode selection controller controls the working mode of the receiving module to include a receiving mode and a shutdown mode.
[0018] Based on the above, the mode selection controller controls the working mode of the receiving module to include a receiving mode and a shutdown mode.
[0019] An integrated circuit chip includes a UART circuit. The integrated circuit chip uses any of the above-mentioned multi-mode check UART circuits.
[0020] The present invention has substantial features and progress over the prior art. Specifically, the present invention controls the working states of the sending module and the receiving module by setting a mode selection controller, thereby realizing three modes, namely, full-duplex communication, single-line sending only, or single-line receiving only. Different modes can be selected according to different scenarios, and the invention has stronger applicability. Furthermore, a verification selection module can be set to select the verification type as needed, thereby providing higher compatibility and optional data security level for data transmission. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 It is a schematic structural diagram of the utility model. DETAILED DESCRIPTION
[0022] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0023] like Figure 1 As shown, a UART circuit with multi-mode verification includes: a sending module, configured to connect a communication bus interface and a sending port, for receiving data sent by the communication bus and performing parallel-to-serial processing and then sending the data to a receiving device through the sending port; a receiving module, configured to connect the communication bus interface and the receiving port, for receiving data sent by the outside world and performing serial-to-serial processing and then sending the data to the communication bus; a control register, configured to connect the communication bus interface, a mode selection controller and a verification selection module respectively, for controlling the mode selection controller and the verification selection module according to a control instruction sent by the communication bus; a mode selection controller, configured to control the connection between the sending module and the receiving module respectively, for controlling the working modes of the sending module and the receiving module; a verification selection module, configured to connect the sending module and the receiving module respectively, for selecting a verification type, and adding a verification bit to the data sent by the sending module and verifying the received data of the receiving module.
[0024] When in use, after the control register receives the external control instruction from the communication bus interface, the mode selection controller selects the working mode of the sending module and the receiving module, the working mode of the sending module includes the sending mode and the off mode, and the working mode of the receiving module includes the receiving mode and the off mode, so as to realize the full-duplex communication mode, the single-line sending mode or the single-line receiving mode. The check selection module enables or disables a specific check function according to the setting instruction received from the communication bus, and selects the corresponding check type. In this embodiment, the check type at least includes no check, parity check, cumulative check and CRC check, etc. In reality, the sending module and the receiving module contain a check module (this part is the prior art, not shown in the figure), according to the selected check function and check type, the check module is responsible for generating a check bit according to the selected check type, and when sending data, the generated check bit will be attached to the data packet to be sent. When receiving data, the check module is responsible for detecting the check bit in the received data and comparing it with the calculated check result.
[0025] In this embodiment, the sending module includes a sending control logic module, a sending FIFO (FIFO is a first-in-first-out register) and a sending serial shift register. The sending control logic module controls the connection of the sending FIFO and the sending serial shift register respectively. The sending control logic module is used to control the working mode of the sending FIFO and the sending serial shift register; the sending FIFO receives and temporarily stores the data sent by the communication bus, and the sending serial shift register is used to perform parallel-to-serial processing on the data transmitted by the sending FIFO and then send it to the sending port. The sending FIFO of the sending module is connected to the communication bus interface through a sending data register, and the sending data register is used to store the received data. When data needs to be sent, the mode control selection controller enables the sending control logic module, and according to the external instruction, the data is loaded onto the sending FIFO. After the sending FIFO sends the data to be sent to the verification module for data verification calculation, the character data after the verification calculation is transferred to the sending serial shift register for parallel-to-serial processing. The sending control logic module outputs the serial data stream and adds the start bit, parity bit, and stop bit at the same time.
[0026] The receiving module includes a receiving control logic module, a receiving FIFO and a receiving serial shift register. The receiving control logic module controls the connection of the receiving FIFO and the receiving serial shift register respectively. The receiving control logic module is used to control the working mode of the receiving FIFO and the receiving serial shift register; the receiving FIFO receives and temporarily stores data sent from the outside world, and the receiving serial shift register is used to serially convert and process the data transmitted by the receiving FIFO and send it to the communication bus. The receiving FIFO of the receiving module is connected to the communication bus interface through the receiving data register, and the receiving data register is used to store the data to be sent to the communication bus. When it is necessary to receive data, the mode selection controller enables the receiving control logic module, and the received data is converted into parallel data after passing through the receiving serial shift register, sent to the verification module for verification, loaded into the receiving FIFO, and then transmitted to the receiving data register for storage, waiting to be sent to the communication bus.
[0027] In practice, the UART circuit includes a baud rate generator, which is respectively connected to a control register, a clock source, a sending module and a receiving module, and is used to receive clock information and provide clock signals to the sending module and the receiving module according to control instructions of the control register.
[0028] An integrated circuit chip includes a UART circuit. The integrated circuit chip uses any of the above-mentioned multi-mode check UART circuits.
[0029] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.
Claims
1. A UART circuit with multi-mode verification, characterized in that: include: The sending module is configured to connect the communication bus interface and the sending port, and is used to receive the data sent by the communication bus and perform parallel-to-serial processing and then send it to the receiving device through the sending port; The receiving module is configured to connect the communication bus interface and the receiving port, and is used to receive data sent from the outside, perform serial conversion, process, and then send to the communication bus; A control register configured to be connected to the communication bus interface, the mode selection controller and the check selection module respectively, and used to control the mode selection controller and the check selection module according to a control instruction sent by the communication bus; A mode selection controller, configured to control the connection between the sending module and the receiving module respectively, and used to control the working mode of the sending module and the receiving module; The check selection module is configured to be connected to the sending module and the receiving module respectively, and is used to select the check type, and to add a check bit to the sending data of the sending module and to check the receiving data of the receiving module.
2. The UART circuit of multi-mode verification according to claim 1, characterized in that: The sending module is connected to the communication bus interface via a sending data register, and the sending data register is used to store received data.
3. The UART circuit of multi-mode verification according to claim 1, characterized in that: The sending module includes a sending control logic module, a sending FIFO and a sending serial shift register. The sending control logic module controls the connection between the sending FIFO and the sending serial shift register respectively, and the sending control logic module is used to control the working modes of the sending FIFO and the sending serial shift register; the sending FIFO receives and temporarily stores data sent by the communication bus, and the sending serial shift register is used to perform parallel-to-serial processing on the data transmitted by the sending FIFO and send it to the sending port.
4. The UART circuit of claim 1, wherein: The receiving module is connected to the communication bus interface via a receiving data register, and the receiving data register is used to store data to be sent to the communication bus.
5. The multi-mode verification UART circuit according to claim 1, characterized in that: The receiving module includes a receiving control logic module, a receiving FIFO and a receiving serial shift register. The receiving control logic module controls the connection between the receiving FIFO and the receiving serial shift register respectively, and the receiving control logic module is used to control the working modes of the receiving FIFO and the receiving serial shift register; the receiving FIFO receives and temporarily stores data sent from the outside, and the receiving serial shift register is used to serially convert the data transmitted by the receiving FIFO and send it to the communication bus after processing.
6. The multi-mode verification UART circuit according to claim 1, characterized in that: It includes a baud rate generator, which is configured to be connected to a control register, a clock source, a sending module and a receiving module respectively, and is used to receive clock information and provide clock signals for the sending module and the receiving module according to a control instruction of the control register.
7. The multi-mode verification UART circuit according to claim 1, characterized in that: The check types of the check selection module include at least no check, parity check, cumulative check and CRC check.
8. The multi-mode verification UART circuit according to claim 1, characterized in that: The mode selection controller controls the working mode of the sending module to include a sending mode and a shutdown mode.
9. The multi-mode verification UART circuit according to claim 1, characterized in that: The mode selection controller controls the working mode of the receiving module to include a receiving mode and a shutdown mode.
10. An integrated circuit chip, comprising a UART circuit, characterized in that: The integrated circuit chip uses the multi-mode check UART circuit described in any one of claims 1-9.