Terminal structure of semiconductor device, semiconductor device, electronic equipment and vehicle

Abstract

The utility model discloses a terminal structure of a semiconductor device, the semiconductor device, electronic equipment and a vehicle. The terminal structure of the semiconductor device comprises a substrate, a field limiting ring structure and a protection layer, the field limiting ring structure is located on the substrate in the first direction perpendicular to the substrate, and a step part is constructed on the side face of the outer edge of the field limiting ring structure; the protection layer covers the upper surface of the field limiting ring structure and extends along the side face of the outer edge of the field limiting ring structure in the second direction perpendicular to the substrate, and the protection layer covers the step part. According to the terminal structure provided by the embodiment of the utility model, the isolation capability of the terminal structure for water / oxygen, metal ions, metal contamination and the like is fundamentally improved, the tolerance environment of the terminal structure of the semiconductor device is optimized, the electric leakage risk of the semiconductor device is reduced, and the reliability of the whole semiconductor device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a terminal structure of a semiconductor device, a semiconductor device, an electronic device and a vehicle. Background Art

[0002] With the continuous development of integrated circuit technology, the demand for semiconductor devices is also increasing. By integrating different semiconductor devices in the module, different circuit functions can be realized. During the manufacturing process of semiconductor devices, sensitive electronic components are packaged to protect these sensitive electronic components from being easily affected by external environmental interference. Among them, with the development of various packaging technologies, many different types of packaging forms have been derived.

[0003] In the prior art, the terminal structure protection of traditional high-voltage Si / SiC semiconductor devices is generally only designed to improve the device's voltage resistance. However, in actual working conditions, the environment has a greater impact on the device, and simply eliminating device failure through packaging is not the root cause. Utility Model Content

[0004] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, the first purpose of the utility model is to propose a terminal structure of a semiconductor device, which fundamentally improves the isolation ability of the terminal structure of the semiconductor device to water / oxygen, metal ions, metal contamination, etc., optimizes the tolerance environment of the terminal structure, reduces the leakage risk of the semiconductor device, and improves the reliability of the entire semiconductor device.

[0005] The second objective of the present invention is to provide a semiconductor device.

[0006] The third objective of the present invention is to provide an electronic device.

[0007] A fourth objective of the present invention is to provide a vehicle.

[0008] In order to achieve the above-mentioned purpose, the terminal structure of the semiconductor device proposed in the embodiment of the first aspect of the utility model includes: a substrate; a field limiting ring structure, wherein the field limiting ring structure is located on the substrate in a first direction perpendicular to the substrate, and the side surface of the outer edge of the field limiting ring structure is configured with a step portion; a protective layer, wherein the protective layer covers the upper surface of the field limiting ring structure and extends along the side surface of the outer edge of the field limiting ring structure in a second direction perpendicular to the substrate, and the protective layer covers the step portion.

[0009] According to the terminal structure proposed in the embodiment of the utility model, by changing the length of the field limiting ring structure at the edge of the terminal structure, the effect of a protective layer covering the upper surface of the field limiting ring structure and the step formed by the field limiting ring structure and the epitaxial layer is created. By setting the protective layer, the terminal structure of the semiconductor device can be protected, and the isolation ability of the terminal structure to water / oxygen is fundamentally improved. By improving the tolerance environment of the terminal structure, it can effectively prevent the occurrence of electrochemical corrosion of the internal structure of the semiconductor device tube core caused by water / oxygen, metal ions, metal contamination, etc. invading the internal structure of the semiconductor device tube core through the terminal structure, thereby reducing the leakage risk of the semiconductor device, and further improving the voltage resistance of the terminal structure, improving the reliability of the terminal structure, and then improving the reliability of the entire semiconductor device, and extending the service life of the semiconductor device.

[0010] In some embodiments of the present invention, the base includes: a substrate; an epitaxial layer, wherein the epitaxial layer is located on the substrate in the first direction; and the field limiting ring structure is located on the epitaxial layer in the first direction.

[0011] In some embodiments of the present invention, the epitaxial layer includes: a first epitaxial portion and a second epitaxial portion, the first epitaxial portion is connected to the second epitaxial portion, and the second epitaxial portion protrudes from the first epitaxial portion in the first direction toward a side of the epitaxial layer away from the substrate.

[0012] In some embodiments of the present invention, the field limiting ring structure includes: a heavily doped region, the heavily doped region is located on the first epitaxial layer in the first direction, and the outer edge of the heavily doped region extends along the second direction to the edge of the first epitaxial portion; an interlayer dielectric layer, the interlayer dielectric layer covers part of the heavily doped region and the interlayer dielectric layer is located above the second epitaxial portion in the first direction, the outer edge of the interlayer dielectric layer and the outer edge of the heavily doped region have a first preset distance in the second direction, so that the side of the outer edge of the interlayer dielectric layer and the upper surface of the epitaxial layer are constructed as a first step portion.

[0013] In some embodiments of the present invention, an outer edge of the heavily doped region is flush with an edge of the first epitaxial portion.

[0014] In some embodiments of the present invention, a side surface of the heavily doped region away from an edge of the first epitaxial portion is connected to the second epitaxial portion.

[0015] In some embodiments of the present invention, an upper surface of the heavily doped region is flush with an upper surface of the second epitaxial portion.

[0016] In some embodiments of the present invention, the field limiting ring structure further includes: a metal layer, the metal layer is located on the interlayer dielectric layer in the first direction, and the metal layer is connected to the heavily doped region via a through hole penetrating the interlayer dielectric layer.

[0017] In some embodiments of the present invention, the outer edge of the metal layer and the outer edge of the interlayer dielectric layer have a second preset distance in the second direction, so that the side surface of the outer edge of the metal layer and the upper surface of the interlayer dielectric layer are configured as a second step portion.

[0018] In some embodiments of the present invention, the field limiting ring structure further includes: a field oxide layer, the field oxide layer is located between the interlayer dielectric layer and the second epitaxial portion in the first direction, and the field oxide layer covers a portion of the heavily doped region away from an edge of the first epitaxial portion.

[0019] In some embodiments of the present invention, the protective layer includes: a passivation layer, and the passivation layer covers the upper surface of the metal layer, the first step portion, and the second step portion.

[0020] In some embodiments of the present invention, the passivation layer is a silicon nitride layer or a silicon nitride oxide layer.

[0021] In some embodiments of the present invention, the protective layer further includes: an organic layer, and the organic layer is located on the passivation layer.

[0022] In some embodiments of the present invention, the organic layer completely covers the passivation layer.

[0023] In some embodiments of the present invention, the organic layer includes a polyimide layer.

[0024] In order to achieve the above-mentioned purpose, the second aspect embodiment of the utility model further proposes a semiconductor device, comprising an active area and a terminal structure of the semiconductor device described in any one of the above items, wherein the terminal structure of the semiconductor device is arranged around the active area, and the protective layer of the terminal structure of the semiconductor device covers the upper surface of the active area.

[0025] According to the semiconductor device proposed in the embodiment of the utility model, by adopting the terminal structure of the semiconductor device of the first embodiment above to surround the active area, by improving the waterproof / oxygen, metal ion, metal contamination, etc. effect of the terminal structure of the semiconductor device, it can effectively prevent water / oxygen, metal ions, metal contamination, etc. from invading the active area from the terminal structure, and setting a protective layer of the terminal structure of the semiconductor device to cover the upper surface of the active area, it can improve the waterproof / oxygen, metal ion, metal contamination, etc. ability of the active area, even when the package fails, it can avoid the occurrence of water / oxygen, metal ions, metal contamination, etc. invading the internal structure of the semiconductor device, causing it to be irreversibly damaged, increase leakage current, and withstand voltage failure, etc., thereby improving the waterproof / oxygen, metal ion, metal contamination, etc. effect of the semiconductor device, and improving the ability of the semiconductor device to withstand voltage and high humidity.

[0026] In order to achieve the above-mentioned purpose, the third aspect of the present invention further provides an electronic device, comprising at least one semiconductor device as described in the third aspect of the present invention.

[0027] According to the semiconductor device proposed in the embodiment of the utility model, the semiconductor device of the above embodiment is adopted, and the stability of electronic equipment can be effectively improved and the service life of electronic equipment can be extended by improving the waterproof / oxygen, metal ion, metal contamination and other effects of the semiconductor device and the ability to withstand pressure and high humidity.

[0028] In order to achieve the above-mentioned purpose, a fourth aspect of the present utility model further provides a vehicle, comprising the electronic device described in the above embodiment.

[0029] The vehicle proposed in the embodiment of the utility model can effectively improve the safety and stability of vehicle operation and enhance the overall waterproof / oxygen, metal ion, metal contamination and other performance of the vehicle by adopting electronic equipment that applies the semiconductor devices of the above embodiments.

[0030] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0032] Figure 1 A schematic diagram of a terminal structure of a semiconductor device according to an embodiment of the utility model;

[0033] Figure 2 is a schematic diagram of a terminal structure of a semiconductor device according to another embodiment of the utility model;

[0034] Figure 3 A schematic diagram of a preparation process of a terminal structure of a semiconductor device according to an embodiment of the utility model;

[0035] Figure 4 A schematic diagram of a preparation process of a terminal structure of a semiconductor device according to another embodiment of the utility model;

[0036] Figure 5 A schematic diagram of a preparation process of a terminal structure of a semiconductor device according to another embodiment of the utility model;

[0037] Figure 6 A schematic diagram of a preparation process of a terminal structure of a semiconductor device according to another embodiment of the utility model;

[0038] Figure 7 The figure is a schematic diagram of a preparation process of a terminal structure of a semiconductor device according to another embodiment of the present invention.

[0039] Figure 8 is a schematic diagram of a semiconductor device according to an embodiment of the utility model;

[0040] Fig. 9 is a block diagram of an electronic device according to an embodiment of the utility model;

[0041] Fig.10 The block diagram of a vehicle according to an embodiment of the present utility model.

[0042] Reference numerals:

[0043] Vehicles 1000;

[0044] Electronic device 100;

[0045] Semiconductor device 10;

[0046] A terminal structure 1 and an active region 2 of a semiconductor device;

[0047] Substrate 11, field limiting ring structure 12, protective layer 13;

[0048] The substrate 111 , the epitaxial layer 112 , the heavily doped region 121 , the interlayer dielectric layer 122 , the metal layer 123 , the field oxide layer 124 , the passivation layer 131 , the organic layer 132 , the first epitaxial portion 1121 , and the second epitaxial portion 1122 . DETAILED DESCRIPTION

[0049] The embodiments of the present utility model are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present utility model are described in detail below.

[0050] In the prior art, the terminal structure protection of traditional high-voltage Si / SiC semiconductor devices is generally only designed to improve the voltage resistance, while the device reliability application and packaging stability are poor, and generally not much improvement is made in the device design. Environmental factors such as water / oxygen, metal ions, metal contamination, water and oxygen have a great impact on the device, so under actual working conditions, the probability of device failure due to packaging failure is very high.

[0051] In order to solve the above problems, the embodiment of the utility model proposes a terminal structure of a semiconductor device. Under the premise of failure of packaging technology, the terminal structure of the semiconductor device can prevent the occurrence of electrochemical corrosion caused by water / oxygen, metal ions, metal contamination, etc. invading the internal structure of the semiconductor device, thereby reducing the risk of leakage of the semiconductor device. In view of the problem of semiconductor devices being isolated from water / oxygen, metal ions, metal contamination, etc., the terminal structure of the semiconductor device of the embodiment of the utility model can avoid the occurrence of undesirable phenomena such as irreversible damage to the semiconductor device, increased leakage, and even withstand voltage failure.

[0052] Reference below Figure 1-Figure 7 A terminal structure of a semiconductor device according to an embodiment of the present invention is described.

[0053] In some embodiments of the present invention, Figure 1 , which is a schematic diagram of a terminal structure of a semiconductor device according to an embodiment of the present utility model, wherein the terminal structure 1 of the semiconductor device includes a substrate 11 , a field limiting ring structure 12 and a protective layer 13 .

[0054] For example, Si / SiC of N-type conductivity may be selected as the substrate 11. In some embodiments, the substrate 11 includes a substrate 111 and an epitaxial layer 112, and the epitaxial layer 112 is located on the substrate 111 in the first direction. The difference between the epitaxial layer 112 and the substrate 111 is that the concentrations are different, the substrate 111 is better doped, and the prices and growth rates of the epitaxial layer 112 and the substrate 111 are also different. It can be understood that the substrate 111 serves as the substrate of the entire power device, and in the following drawings and descriptions, only the epitaxial layer is used as the bottom layer of the terminal structure 10 of the semiconductor device for illustration and explanation.

[0055] Furthermore, the field limiting ring structure 12 is located on the epitaxial layer 112 in the first direction, and a step portion is configured on the side of the edge of the field limiting ring structure 12. Figure 1 Only a cross section of the terminal structure 1 of the semiconductor device is shown. In fact, the field limiting ring structure 12 is a closed surrounding structure arranged around the periphery of the chip.

[0056] It is understandable that when the field limiting ring structure 12 is prepared on the epitaxial layer 112, the extension length of the outer edge of the field limiting ring structure 12 can be set to be shorter than the length of the edge of the epitaxial layer 112, so as to form a step portion in combination with the epitaxial layer 112. The protective layer 13 covers the upper surface of the field limiting ring structure 12 and extends along the side of the edge of the field limiting ring structure 13 in the second direction perpendicular to the substrate 11. The protective layer 13 covers the step portion and extends at least to the upper surface of the substrate 11. That is to say, the protective layer 13 can completely cover the step formed by the field limiting ring structure 12. By improving the length of the field limiting ring structure 12, a step effect covered by the protective layer 13 is formed, so that water / oxygen, metal ions, metal contamination, etc. can be effectively isolated from entering the interior of the semiconductor device from the field limiting ring structure 12 in the terminal structure 1 of the semiconductor device. Even if the packaging technology fails, the protective layer 13 can effectively prevent the semiconductor device from being irreversibly damaged, increased leakage, and withstand voltage failure caused by water / oxygen, metal ions, metal contamination, etc. invading the terminal structure 1 of the semiconductor device and then entering the internal structure of the semiconductor device, thereby improving the device's waterproof / oxygen, metal ion, metal contamination, etc. effect. Among them, the first direction and the second direction are already in Figure 1 And marked in the following drawings.

[0057] According to the terminal structure 1 of the semiconductor device proposed in the embodiment of the utility model, by changing the length of the field limiting ring structure 12 at the edge of the terminal structure 1 of the semiconductor device, the protective layer 13 is created to cover the upper surface of the field limiting ring structure 12 and the step formed by the field limiting ring structure 12 and the substrate 11. By setting the protective layer 13, the terminal structure 1 of the semiconductor device can be protected, and the isolation ability of the terminal structure 1 of the semiconductor device to water / oxygen, metal ions, metal contamination, etc. is fundamentally improved. By improving the tolerance environment of the terminal structure 1 of the semiconductor device, it can effectively prevent the electrochemical corrosion of the internal structure of the device caused by water / oxygen, metal ions, metal contamination, etc. invading the internal structure of the device through the terminal structure 1 of the semiconductor device, thereby reducing the leakage risk of the semiconductor device, and further improving the voltage resistance of the terminal structure 1 of the semiconductor device, improving the reliability of the terminal structure 1 of the semiconductor device, thereby improving the reliability of the entire semiconductor device and extending the service life of the semiconductor device.

[0058] In some embodiments, the Figure 2 Understanding the terminal structure 1 of the semiconductor device of the embodiment of the utility model, Figure 2 It is a schematic diagram of a terminal structure of a semiconductor device according to another embodiment of the utility model.

[0059] Among them, combined Figure 1 and Figure 2It can be seen that the epitaxial layer 112 includes a first epitaxial portion 1121 and a second epitaxial portion 1122 , the first epitaxial portion 1121 is connected to the second epitaxial portion 1122 , and the second epitaxial portion 1122 protrudes from the first epitaxial portion 1121 in the first direction toward a side of the epitaxial layer 112 away from the substrate. Figure 2 The epitaxial layer 112 is not shown in the figure, and the first epitaxial portion 1121 and the second epitaxial portion 1122 are separated by a dotted line. The first epitaxial portion 1121 and the second epitaxial portion 1122 in the following figures are distinguished in this way.

[0060] like Figure 2 As shown, the field limiting ring structure 12 includes a heavily doped region 121, an interlayer dielectric layer 122 and a metal layer 123. The heavily doped region 121 is located on the first extension portion 1121 in the first direction, and the outer edge of the heavily doped region 121 extends to the edge of the first extension portion 1121 along the second direction.

[0061] In other embodiments, the outer edge of the heavily doped region 121 is flush with the edge of the first epitaxial portion 1121. Also, the side of the heavily doped region 121 away from the edge of the first epitaxial portion 1121 is connected to the side of the second epitaxial portion 1122, and the upper surface of the heavily doped region 121 is flush with the upper surface of the second epitaxial portion 1122. Specifically, in order to form a PN junction, when preparing the heavily doped region 121, a layer of ions can be implanted on the first epitaxial portion 1121 to form the heavily doped region 121, and the conductivity type of the heavily doped region 121 can also be N-type. When the device is working, the electric fields P and N inside it will form a depletion region, and the heavily doped region 121 can be provided to offset the lateral electric field generated in the device to prevent the semiconductor device from being broken down.

[0062] The interlayer dielectric layer 122 covers part of the heavily doped region 121 and is located above the second epitaxial portion 1122 in the first direction. The outer edge of the interlayer dielectric layer 122 and the outer edge of the heavily doped region 121 have a first preset distance in the second direction, so that the side surface of the outer edge of the interlayer dielectric layer 122 and the upper surface of the heavily doped region 121 form a first step portion. The interlayer dielectric layer 122 has the function of providing ions and insulation, and the interlayer dielectric layer 122 is prepared by doping boron B or phosphorus P in silicon dioxide. In addition, the first preset distance can be set as needed, aiming to stagger the length and height of the edge of the heavily doped region 121 to form a step shape, and the value of the first preset distance is not specifically limited here. Specifically, when preparing the interlayer dielectric layer 122, an interlayer dielectric layer 122 can be first prepared on the upper surface of the second epitaxial portion 1122 and the upper surface of the heavily doped region 121, and then the interlayer dielectric layer 122 is etched so as to form a perforation in the interlayer dielectric layer 122, and the edge of the interlayer dielectric layer 122 is etched to etch a first preset distance in the second direction at the edge of the interlayer dielectric layer 122, so that the edge of the interlayer dielectric layer 122 forms a step shape compared to the heavily doped region 121.

[0063] The metal layer 123 is located on the interlayer dielectric layer 122 in the first direction, and the metal layer 123 is connected to the heavily doped region 121 through the through-holes penetrating the interlayer dielectric layer 122. The metal layer 123 is a cathode metal. When the metal layer 123 is prepared on the interlayer dielectric layer 122, the metal forming the metal layer 123 will flow into the through-holes of the interlayer dielectric layer 122 and connect with the heavily doped region 121. Since the metal layer 123 is conductive, water / oxygen, metal ions, metal contamination, etc., invading the terminal structure 1 of the semiconductor device can easily cause the metal layer 123 to fail or leak electricity. Therefore, by providing the protective layer 13 to completely cover the interlayer dielectric layer 122 and the metal layer 123, water / oxygen, metal ions, metal contamination, etc. can be effectively isolated. By improving the ability of the terminal structure 1 of the semiconductor device to isolate water / oxygen, metal ions, metal contamination, etc., the ability of the device to withstand high humidity environments is improved, and the ability of the semiconductor device to withstand high voltage and high humidity is improved.

[0064] In other embodiments, Figure 2As shown, the outer edge of the metal layer 123 and one end of the outer edge of the interlayer dielectric layer 122 have a second preset distance in the second direction, so that the side of the outer edge of the metal layer 123 and the upper surface of the interlayer dielectric layer 122 are configured as a second step portion. That is to say, for the terminal structure 1 of the semiconductor device of the embodiment of the utility model, on the basis of the first step portion being configured at its edge, a second step portion can be further configured, and the second step portion can be formed by setting the extension length of the outer edge of the metal layer 123 to be shorter than the extension length of the outer edge of the interlayer dielectric layer 122. It can be understood that the second preset distance can be set as needed, and is intended to be staggered with the length and height of the edge of the interlayer dielectric layer 122 to form a step shape, and the value of the second preset distance is not specifically limited here. That is to say, the edges of the interlayer dielectric layer 122 and the metal layer 123 of the embodiment of the utility model can be set to a step shape. At this time, when preparing the protective layer 13, the protective layer 13 covers the exposed portion of the upper surface of the interlayer dielectric layer 122 and the upper surface of the metal layer 123 and extends along the side of the metal layer 123 and the side of the interlayer dielectric layer 122 close to the edge of the heavily doped layer 121 in the second direction perpendicular to the epitaxial layer 112. The protective layer 13 covers the first step portion and the second step portion and extends at least to the upper surface of the heavily doped layer 121. At this time, the protective layer 13 can better completely cover and wrap the sides at the edges of the interlayer dielectric layer 122 and the metal layer 123, and can effectively prevent water / oxygen, metal ions, metal contamination, etc. from invading the interior of the semiconductor device from the interlayer dielectric layer 122 and / or the metal layer 123. The terminal structure 1 of the semiconductor device adopts this design, which can effectively prevent the semiconductor device from being irreversibly damaged due to the invasion of water / oxygen, metal ions, metal contamination, etc. into the internal structure of the semiconductor device, and effectively avoid the occurrence of adverse phenomena such as increased leakage and withstand voltage failure.

[0065] In some embodiments of the present invention, Figure 2 As shown, the field limiting ring structure 12 also includes a field oxygen layer 124, wherein the field oxygen layer 124 is located between the interlayer dielectric layer 122 and the second epitaxial portion 1122 in the first direction. Specifically, the field oxygen layer 124 is a thick silicon dioxide layer, which can be used to achieve isolation and prevent the occurrence of parasitic tubes. During the preparation process, the interlayer dielectric layer 122 can completely cover the upper surface and side surfaces of the field oxygen layer 124. Since the field oxygen layer 124 covers a portion of the heavily doped region 121 away from the edge of the second epitaxial portion 1122, the possibility of water / oxygen, metal ions, metal contamination, etc. entering the field oxygen layer 124 can be further eliminated by preparing a protective layer 13 to cover the interlayer dielectric layer 122 and the metal layer 123.

[0066] In some embodiments of the present invention, Figure 2As shown, the protective layer 13 includes a passivation layer 131, wherein the passivation layer 131 is a silicon nitride layer or a silicon nitride oxide layer, and the passivation layer 131 covers the upper surface, the first step portion and the second step portion of the metal layer 123, so as to completely cover the upper surface and the side of the metal layer 123 and the interlayer dielectric layer 122, thereby being able to effectively isolate water / oxygen, metal ions, metal contamination, etc. from entering the device from the metal layer 123 and / or the interlayer dielectric layer 122 in the terminal structure 1 of the semiconductor device. Even if the packaging technology fails, the terminal structure 1 of the semiconductor device of the device can effectively prevent the occurrence of undesirable phenomena such as irreversible damage to the semiconductor device, increased leakage and withstand voltage failure caused by the invasion of water / oxygen, metal ions, metal contamination, etc. into the internal structure of the semiconductor device, thereby improving the device's waterproof / oxygen, metal ion, metal contamination, etc. effects.

[0067] In other embodiments, Figure 2 As shown, the protective layer 13 also includes an organic layer 132, wherein the organic layer 132 is located on the passivation layer 131, wherein the organic layer 132 includes a polyimide layer. It can be understood that polyimide is a high molecular organic substance with excellent properties such as high temperature resistance, low temperature resistance, corrosion resistance, self-lubrication, low wear, excellent mechanical properties, good dimensional stability, small thermal expansion coefficient, high insulation, low thermal conductivity, non-melting, and non-rusting. Further, the organic layer 132 can be set to fully cover the passivation layer 131 to increase the waterproof / oxygen, metal ion, metal contamination, etc. effects of the protective layer 13.

[0068] Compared with the method of only preparing a passivation layer 131 for waterproofing / oxygen, metal ions, metal contamination, etc., the protective layer 13 of the embodiment of the utility model can further enhance the waterproofing / oxygen, metal ion, metal contamination, etc. effect of the terminal structure 1 of the semiconductor device by preparing another organic layer 132 on the passivation layer 131. In addition, during the preparation process, the polyimide layer can be prepared by spin coating. Since polyimide is an organic substance, the preparation cost is considerable and it is easy to package.

[0069] In some embodiments of the present invention, it can be combined with Figure 2-Figure 7 Understand the preparation process of the terminal structure of the semiconductor device of the embodiment of the utility model. Figure 3 A schematic diagram of a preparation process of a terminal structure of a semiconductor device according to an embodiment of the utility model; Figure 4 A schematic diagram of a preparation process of a terminal structure of a semiconductor device according to another embodiment of the utility model; Figure 5 A schematic diagram of a preparation process of a terminal structure of a semiconductor device according to another embodiment of the utility model; Figure 6A schematic diagram of a preparation process of a terminal structure of a semiconductor device according to another embodiment of the utility model; Figure 7 FIG. 1 is a schematic diagram of a process for preparing a terminal structure of a semiconductor device according to another embodiment of the present invention. Figure 2-Figure 7 In the figures, the substrate 11 is shown, and only the epitaxial layer 112 is described as a schematic diagram, and the first direction and the second direction are shown in Figure 2-Figure 7 Mark in.

[0070] like Figure 3 As shown, N-type Si / SiC is provided as the epitaxial layer 112, the epitaxial layer 112 includes a first epitaxial portion 1121 and a second epitaxial portion 1122, and a layer of ions is implanted on the first epitaxial portion 1121 to form the heavily doped region 121. Figure 4 As shown, a field oxide layer 124 is formed on a portion of the upper surface of the second epitaxial portion 1122 and the heavily doped region 121; and Figure 5 As shown, an interlayer dielectric layer 122 is prepared in a part of the upper surface of the heavily doped region 121 and the field oxide layer 124, and the interior of the interlayer dielectric layer 122 is etched to form a through hole in the interlayer dielectric layer 122, and the edge of the interlayer dielectric layer 122 is etched to stagger the length and height of the edge of the interlayer dielectric layer 122 and the heavily doped region 121 to form a step-shaped, i.e., a first step portion; as shown in FIG. Figure 6 As shown, a metal layer 123 is prepared on the interlayer dielectric layer 122. When the metal layer 123 is prepared on the interlayer dielectric layer 122, the metal forming the metal layer 123 flows into the through-holes of the interlayer dielectric layer 122 and connects with the heavily doped region 121. The edge of the metal layer 123 is etched to stagger the length and height of the edge of the metal layer 123 and the interlayer dielectric layer 122 to form a step-shaped, i.e., a second step portion; as shown in FIG. Figure 7 As shown, a passivation layer 131 is prepared on the metal layer 123, and the passivation layer 131 covers the upper surface, the first step portion and the second step portion of the metal layer 123, so as to completely cover the upper surface and the side of the metal layer 123 and the interlayer dielectric layer 122; finally, an organic layer 132 is prepared on the upper surface of the passivation layer 131, wherein a polyimide layer can be prepared by spin coating as the organic layer 132, and finally a structure as shown in FIG. Figure 2 The terminal structure 1 of the semiconductor device shown. Further, in addition to Figure 2 The structural design of the organic layer 132 and the passivation layer 131 shown in the figure can also be set so that the organic layer 132 fully covers the passivation layer 131 to further enhance the waterproof / oxygen, metal ion, metal contamination and other effects of the protective layer 13.

[0071] Based on the above, the terminal structure 1 of the semiconductor device proposed in the embodiment of the utility model includes, from bottom to top, an epitaxial layer 112, a heavily doped region 121, a field oxide layer 124, an interlayer dielectric layer 122, a metal layer 123, a passivation layer 131 and an organic layer 132. When preparing the interlayer dielectric layer 122 and the metal layer 123, the lengths of the edges of the metal layer 123 and the edges of the interlayer dielectric layer 122 are changed to form the first step portion and the second step portion respectively, and the passivation layer 131 is provided to cover the upper surface of the metal layer 123, the first step portion and the second step portion, and further an organic layer 132 is prepared on the passivation layer 131, so as to form a step effect covered by polyimide. By providing the polyimide layer and the passivation layer 131 to protect the terminal structure 1 of the semiconductor device, the isolation capability of the terminal structure 1 of the semiconductor device for water / oxygen, metal ions, metal contamination, etc. is fundamentally improved, the tolerance environment of the semiconductor device is improved, the reliability of the semiconductor device is improved, and the service life of the semiconductor device is extended.

[0072] In some embodiments of the present invention, Figure 8 FIG. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device 10 includes an active region 2 and a terminal structure 1 of the semiconductor device of any of the above embodiments. The terminal structure 1 of the semiconductor device is arranged around the active region 2, and the protective layer 13 of the terminal structure 1 of the semiconductor device covers the upper surface of the active region 2. Figure 8 The structures of the various parts are only for illustration, and the specific arrangement of the terminal structure 1 and the active area 2 of the semiconductor device is not limited here. The dotted box part in the figure is the active area 2 covered by the protective layer 13, and the protective layer 13 is not shown in the figure.

[0073] According to the semiconductor device 10 proposed in the embodiment of the utility model, by adopting the terminal structure 1 of the semiconductor device of the first aspect embodiment above to surround the active area 2, by improving the waterproof / oxygen, metal ion, metal contamination, etc. effect of the terminal structure 1 of the semiconductor device, it can effectively prevent water / oxygen, metal ions, metal contamination, etc. from invading the active area 2 from the terminal structure 1 of the semiconductor device, and setting the protective layer 13 of the terminal structure 1 of the semiconductor device to cover the upper surface of the active area 2, it can improve the waterproof / oxygen, metal ion, metal contamination, etc. ability of the active area 2, even when the package fails, it can avoid the occurrence of water / oxygen, metal ions, metal contamination, etc. invading the internal structure of the semiconductor device 10, causing it to be irreversibly damaged, increase leakage current, and withstand voltage failure, etc., thereby improving the waterproof / oxygen, metal ion, metal contamination, etc. effect of the semiconductor device 10, and improving the ability of the semiconductor device 10 to withstand voltage and high humidity.

[0074] In some embodiments of the present invention, an electronic device is also provided, such as Fig. 9, which is a block diagram of an electronic device according to an embodiment of the present utility model, wherein the electronic device 100 includes at least one semiconductor device 10 as described in the above second aspect embodiment.

[0075] According to the electronic device 100 proposed in the embodiment of the utility model, the semiconductor device 10 of the above embodiment is adopted, and the stability of the electronic device 100 can be effectively improved and the service life of the electronic device 100 can be extended by improving the waterproof / oxygen, metal ion, metal contamination and other effects of the semiconductor device 10 and the ability to withstand pressure and high humidity.

[0076] In some embodiments of the present invention, a vehicle is also provided, such as Fig.10 As shown, it is a block diagram of a vehicle according to an embodiment of the present utility model, wherein the vehicle 1000 includes the electronic device 100 as described in the third aspect embodiment above.

[0077] According to the vehicle 1000 proposed in the embodiment of the utility model, by adopting the electronic device 100 applying the semiconductor device 10 of the above embodiment, the safety and stability of the operation of the vehicle 1000 can be effectively improved, and the overall waterproof / oxygen, metal ion, metal contamination and other performances of the vehicle 1000 can be enhanced.

[0078] Other structures and operations of the vehicle 1000 , the electronic device 100 and the semiconductor device 10 according to the embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

[0079] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0080] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A terminal structure of a semiconductor device, characterized in that: include: substrate; A field limiting ring structure, wherein the field limiting ring structure is located on the substrate in a first direction perpendicular to the substrate, and a side surface of an outer edge of the field limiting ring structure is configured with a step portion; A protective layer covers the upper surface of the field limiting ring structure and extends along the side of the outer edge of the field limiting ring structure in a second direction perpendicular to the substrate, and the protective layer covers the step portion.

2. The terminal structure of the semiconductor device according to claim 1, characterized in that: The substrate comprises: substrate; an epitaxial layer, the epitaxial layer being located on the substrate in the first direction; The field limiting ring structure is located on the epitaxial layer in the first direction.

3. The terminal structure of the semiconductor device according to claim 2, characterized in that: The epitaxial layer comprises: A first epitaxial portion and a second epitaxial portion, the first epitaxial portion is connected to the second epitaxial portion, and the second epitaxial portion protrudes from the first epitaxial portion toward a side of the epitaxial layer away from the substrate in the first direction.

4. The terminal structure of the semiconductor device according to claim 3, characterized in that: The field limiting ring structure (12) comprises: a heavily doped region, the heavily doped region being located on the first epitaxial portion in the first direction, and the heavily doped region extending to an edge of the first epitaxial portion along the second direction; An interlayer dielectric layer, wherein the interlayer dielectric layer covers a portion of the heavily doped region and is located above the second epitaxial portion in the first direction, and an outer edge of the interlayer dielectric layer and an outer edge of the heavily doped region have a first preset distance in the second direction, so that a side surface of the outer edge of the interlayer dielectric layer and an upper surface of the heavily doped region are constructed as a first step portion.

5. The terminal structure of the semiconductor device according to claim 4, characterized in that: An outer edge of the heavily doped region is flush with an edge of the first epitaxial portion.

6. The terminal structure of the semiconductor device according to claim 4, characterized in that: A side surface of the heavily doped region away from an edge of the first epitaxial portion is connected to the second epitaxial portion.

7. The terminal structure of the semiconductor device according to claim 4, characterized in that: An upper surface of the heavily doped region is flush with an upper surface of the second epitaxial portion.

8. The terminal structure of a semiconductor device according to any one of claims 4 to 7, characterized in that: The field limiting ring structure further includes: A metal layer, wherein the metal layer is located on the interlayer dielectric layer in the first direction, and the metal layer is connected to the heavily doped region via a through hole penetrating the interlayer dielectric layer.

9. The terminal structure of the semiconductor device according to claim 8, characterized in that: An outer edge of the metal layer and an outer edge of the interlayer dielectric layer have a second preset distance in the second direction, so that a side surface of the outer edge of the metal layer and an upper surface of the interlayer dielectric layer form a second step portion.

10. The terminal structure of the semiconductor device according to claim 9, characterized in that: The field limiting ring structure further includes: A field oxide layer is located between the interlayer dielectric layer (122) and the second epitaxial portion in the first direction, and the field oxide layer covers a portion of the heavily doped region away from an edge of the first epitaxial portion.

11. The terminal structure of the semiconductor device according to claim 9, characterized in that: The protective layer comprises: A passivation layer covers the upper surface of the metal layer, the first step portion, and the second step portion.

12. The terminal structure of the semiconductor device according to claim 11, characterized in that: The passivation layer is a silicon nitride layer or a silicon nitride oxide layer.

13. The terminal structure of the semiconductor device according to claim 11, characterized in that: The protective layer also includes: An organic layer is located on the passivation layer.

14. The terminal structure of the semiconductor device according to claim 13, characterized in that: The organic layer completely covers the passivation layer.

15. The terminal structure of the semiconductor device according to claim 14, characterized in that: The organic layer includes a polyimide layer.

16. A semiconductor device, characterized in that: The invention comprises an active area and a terminal structure of a semiconductor device according to any one of claims 1 to 15, wherein the terminal structure of the semiconductor device is arranged around the active area, and a protective layer of the terminal structure of the semiconductor device covers the upper surface of the active area.

17. An electronic device, characterized in that: Comprising at least one semiconductor device as claimed in claim 16.

18. A vehicle, characterized in that: An electronic device comprising the electronic device described in claim 17.

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