Detection circuit and temperature sensor realized by same

Abstract

The utility model provides a detection circuit which can be applied to a temperature sensor and is in direct proportion to absolute temperature, the detection circuit is provided with a first detection output end (23) and a second detection output end (24), and the detection circuit comprises a plurality of detection elements (35) which are used for detecting an object to be detected to obtain a detection result; a switch assembly (34) through which each detection element (35) is connected to a first detection output end (23) or a second detection output end (24), the first detection output end (23) and the second detection output end (24) being used for outputting a detection result; wherein the switch assembly (34) is configured to connect at least one detection element (35) to the first detection output (23) and the remaining detection elements (35) to the second detection output (24) during any time period. By dynamically compensating the detection results of the detection elements (35), the problem of mismatch caused by the fact that each detection element (35) is fixedly connected to one output end is avoided, and the detection error is reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of electronic information, and in particular to a detection circuit and a temperature sensor implemented therein. Background Art

[0002] Detection circuits play an important role in various fields such as chip manufacturing and sensor production. For example, in the production process of temperature sensors, a PTAT circuit that can generate a current or voltage proportional to the absolute temperature is required. This circuit can output a current or voltage that is proportional to the absolute temperature and is independent of the process and power supply voltage.

[0003] However, the conventional bias current will cause the PTAT circuit to produce large errors during the chip processing. For example, the chip processing will produce an offset voltage on the PNP tube, which will cause a large error on the PTAT circuit. It can be seen that the above circuit will inevitably cause mismatch problems during the chip manufacturing process, and then produce an offset voltage at the output end, thereby affecting the accuracy of the final temperature sensor. Utility Model Content

[0004] In view of the above problems, the present disclosure is proposed to provide a detection circuit and a temperature sensor implemented therein that overcome the above problems or at least partially solve the above problems.

[0005] According to one aspect of the present disclosure, a detection circuit is provided.

[0006] Having a first detection output terminal and a second detection output terminal, the detection circuit comprises:

[0007] A plurality of detection elements are used to detect the object to be detected to obtain the detection result;

[0008] a switch component, each of the detection elements is connected to the first detection output end or the second detection output end through the switch component, and the first detection output end and the second detection output end are used to output the detection result;

[0009] The switch component is configured to: in any time period, connect at least one of the detection elements to the first detection output terminal, and connect the remaining detection elements to the second detection output terminal.

[0010] According to yet another aspect of the present disclosure, a temperature sensor is provided, comprising: the detection circuit as described above.

[0011] In the detection circuit and temperature sensor provided by the present disclosure, a switch component is provided, and accordingly, in any time period, at least one detection element is connected to the first detection output terminal, and the remaining detection elements are connected to the second detection output terminal; and the detection elements connected to the first detection output terminal in each time period are different. It can be seen that the detection result of the detection element can be dynamically compensated by the switch component, so that each detection element is dynamically connected to the first detection output terminal or the second detection output terminal, avoiding the mismatch problem caused by each detection element being fixedly connected to one output terminal in the related art, thereby improving the accuracy of the device and reducing the detection error.

[0012] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0014] Figure 1 A schematic diagram of the structure of a detection circuit in the related art is shown;

[0015] Figure 2 A schematic diagram of the structure of a detection circuit provided by an embodiment of the present disclosure is shown;

[0016] Figure 3 A structural schematic diagram of a detection circuit provided by a specific example of the present disclosure is shown;

[0017] Figure 4 A schematic structural diagram of a calibration switch module provided by an example of the present disclosure is shown. DETAILED DESCRIPTION

[0018] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0019] In the related art, the structural diagram of the PTAT circuit is as follows: Figure 1As shown, the input reference voltage Vpbias / Vpcas can be provided by a conventional mirror current source circuit, and the input reference current source can generally be one of the following current sources: a constant current source, a current source that generates a constant voltage, and a current source that generates a constant transconductance. However, the conventional bias current may cause a PTAT (proportional to absolute temperature) circuit to generate a large error during chip processing. For example, the chip processing process may cause Figure 1 The 1:N PNP transistor shown generates an offset voltage, which causes a large error in the PTAT circuit. It can be seen that the above circuit will inevitably lead to mismatch problems during the chip manufacturing process, and then generate an offset voltage at the output end Vbep-Vben, thereby affecting the accuracy of the final temperature sensor.

[0020] The embodiment of the present disclosure provides a detection circuit to solve the mismatch problem existing in the related art.

[0021] Figure 2 FIG. 2 shows a schematic diagram of a detection circuit provided by an embodiment of the present disclosure. Figure 2 As shown, the detection circuit has a first detection output terminal 23 and a second detection output terminal 24, and the detection circuit includes: a plurality of detection elements 35 and a switch component 34; wherein each detection element 35 is connected to the first detection output terminal 23 or the second detection output terminal 24 through the switch component 34. The first detection output terminal 23 and the second detection output terminal 24 are used to output the detection result. Wherein, the switch component 34 is configured to: in any time period, at least one detection element 35 is connected to the first detection output terminal, and the remaining detection elements 35 are connected to the second detection output terminal. Optionally, the detection elements connected to the first detection output terminal in adjacent time periods are different. Wherein, the plurality of detection elements 35 are used to obtain the detection result by detecting the object to be detected. The first detection output terminal and the second detection output terminal are used to output the detection results obtained by each detection element.

[0022] Among them, the detection element in this embodiment is used to realize the detection function, and can be a detection element of various forms. For example, the detection element can be a triode for detecting the ambient temperature. In the related art, at least one triode is fixedly connected to the first detection output terminal, and the remaining triodes are fixedly connected to the second detection output terminal. However, the inventor found in the process of realizing the present disclosure that since each triode is fixedly connected to a certain output terminal, a mismatch problem will inevitably occur. For example, assuming that there are 9 triodes, in the related art, one of the 9 triodes (such as the first triode) is usually fixedly connected to the first detection output terminal, and the remaining 8 triodes (such as the 2nd to 9th triodes) are fixedly connected to the second detection output terminal. Due to the influence of device differences, the physical properties of the first triode connected to the first detection output terminal cannot be guaranteed to be completely consistent with the physical properties of the remaining triodes connected to the second detection output terminal, and accordingly, a device mismatch problem will be caused.

[0023] In this embodiment, each detection element can be dynamically connected to different output terminals in different time periods through the switch component, thereby avoiding the mismatch problem caused by fixed connection to one output terminal. Among them, the switch component can be a component composed of a multi-way switch, and each switch can control the connection relationship between each detection element and the output terminal respectively. The present invention does not limit the specific form of the switch component, and it can be a switch component of various forms such as an electric control switch, a time control switch, a mechanical switch, etc., as long as it can achieve the above functions.

[0024] In addition, the detection result of each detection element can be either a detection result in the form of voltage (such as detection voltage) or a detection result in the form of current (such as detection current). In addition, the physical meaning of the detection result depends on the specific type of the detection element. For example, when the detection element is a temperature detection element, the physical meaning of the detection result is the measurement result of the ambient temperature; when the detection element is a humidity detection element, the physical meaning of the detection result is the measurement result of the ambient humidity. The present invention does not limit the type of detection element and the specific connotation of the detection result. In short, any scenario that requires the use of multiple groups of detection elements to achieve detection can achieve the effect of avoiding mismatch through the dynamic control function in this application.

[0025] It can be seen that the detection result of the detection element can be dynamically compensated by the switch component 34, so that each detection element is dynamically connected to the first detection output terminal or the second detection output terminal, avoiding the mismatch problem caused by the fixed connection of each detection element to one output terminal in the related art, thereby improving the accuracy of the device and reducing the detection error. In order to solve the above problem, in an optional manner of this embodiment, a plurality of time-controlled switches respectively connected to the plurality of detection elements 35 are further arranged inside the switch component 34, and through the time-sharing control function of the time-controlled switch, each detection element can be dynamically connected to different output terminals in different time periods, thereby avoiding the mismatch problem caused by fixed connection to one output terminal.

[0026] Preferably, the number of time-controlled switches is equal to the number of detection elements, and each time-controlled switch corresponds to each detection element one by one. Through the control of the time-controlled switches, in any time period, at least one detection element 35 is connected to the first detection output terminal 23, and the remaining detection elements 35 are connected in parallel to the second detection output terminal 24. For example, in one implementation, in any time period, there is and only one detection element 35 connected to the first detection output terminal 23, and the remaining detection elements 35 are connected in parallel to the second detection output terminal 24. For example, in another implementation, the multiple detection elements 35 are further divided into a number of detection element groups, and a detection element group contains at least two detection elements. Accordingly, in any time period, at least two detection elements contained in a detection element group are connected to the first detection output terminal 23, and each detection element contained in the remaining detection element groups is connected in parallel to the second detection output terminal 24. The present disclosure does not limit the specific implementation details, as long as the purpose of dynamically connecting each detection element 35 to different output terminals in sequence can be achieved.

[0027] The time period refers to the time length for triggering the switching operation for the detection element 35 connected to the first detection output terminal 23. For example, in the first time period, the first detection element 35 is connected to the first detection output terminal 23 by the time-controlled switch, and the remaining detection elements 35 except the first detection element 35 are connected to the second detection output terminal 24; in the second time period, the second detection element is connected to the first detection output terminal 23 by the time-controlled switch, and the remaining detection elements except the second detection element are connected to the second detection output terminal 24... and so on, until in the Nth time period, the Nth detection element is connected to the first detection output terminal 23 by the time-controlled switch, and the remaining detection elements except the Nth detection element are connected to the second detection output terminal 24. In this case, N is a natural number, and the value of N is equal to the number of detection elements.

[0028] For example, when the number of detection elements is N (N is 9 in the above example), the above-mentioned multiple time periods include: each time period included in at least one time cycle; wherein each time cycle includes N time periods, and in each time period of a time cycle, the switch state of each time-controlled switch changes dynamically, so that the detection element connected to the first detection output terminal in each time period changes dynamically. It can be seen that the detection results obtained by each detection element output by the first detection output terminal and the second detection output terminal correspond to each time period included in at least one time cycle. In specific implementation, the detection results obtained by each detection element output by the first detection output terminal and the second detection output terminal can be multiple time periods included in a time cycle (such as 9 time periods), or multiple time periods included in multiple time cycles (such as multiples of 9 time periods, the specific multiple is the number of time cycles), and the present invention does not limit this.

[0029] In addition, the time-controlled switch in this embodiment can be a level switch or other types of switches, as long as it can realize the time-sharing control function. This embodiment does not limit the specific type of the time-controlled switch.

[0030] Optionally, the circuit may further include a load module, and the load module is used to adjust the detection signal output by the detection element.

[0031] Optionally, the switch assembly includes: a plurality of time-controlled switches, and the plurality of time-controlled switches correspond one to one with the plurality of detection elements. For example, the number of the plurality of time-controlled switches is N, and in the i-th time period, the i-th time-controlled switch is connected to the first detection output terminal, and the remaining time-controlled switches are connected to the second detection output terminal, and N≥i≥2.

[0032] Optionally, when the time-controlled switch is a level switch, each level switch includes a first end, a second end and a third end, the first end is connected to the first detection output end, the second end is connected to the second detection output end, and the third end is connected to the detection element; each level switch corresponds to a switch clock signal end, and the level switch responds to the signal of the switch clock signal end to connect the first end to the third end or the second end to the third end.

[0033] It can be seen that the detection results of the detection elements can be dynamically compensated through multiple time-controlled switches, so that each detection element is dynamically connected to the first detection output terminal or the second detection output terminal, avoiding the mismatch problem caused by each detection element being fixedly connected to one output terminal in the related art, thereby improving the accuracy of the device and reducing the detection error. In short, this embodiment can improve the detection accuracy by means of time-sharing dynamic compensation.

[0034] For ease of understanding, a specific example is used below to describe in detail the circuit structure of the detection circuit in this embodiment. In this example, the detection circuit is arranged in a temperature sensor to implement a temperature detection function.

[0035] Figure 3 FIG. 4 shows a schematic diagram of the structure of the detection circuit provided in this example. Figure 3 As shown, the detection circuit is a PTAT reference current source circuit, including: a power module 30 for providing a PTAT current proportional to absolute temperature (i.e., the VTS_BIAS_PTAT module in the figure), a load module 04, a calibration switch module 05 (i.e., DVBE_DEM_SW in the figure), a switch component 34 (i.e., DVBE_DEM_SW2 in the figure), and a detection element 35.

[0036] The first output terminal P3 of the power module 30 is connected to the first voltage terminal VDDA, the second output terminal P4 of the power module 30 is connected to the second voltage terminal VSSA, and the control output terminal (P1 and P2, the specific number can be flexibly adjusted according to the number of branches of the load module) of the power module 30 is connected to the control voltage terminal. The input terminal of the load module 04 is connected to the first voltage terminal VDDA, and the control terminal of the load module 04 is connected to the control voltage terminal ( Figure 3 The output end of the load module 04 is connected to the first detection output end Vbep and the second detection output end Vben.

[0037] Optionally, the load module 04 includes: a first load branch 31 and a second load branch 32. The input end of the first load branch 31 is connected to the first voltage end VDDA, the control end of the first load branch 31 is connected to the control voltage end (P1, P2), and the output end of the first load branch 31 is connected to the first detection output end Vbep or the second detection output end Vben. The input end of the second load branch 32 is connected to the first voltage end VDDA, the control end of the second load branch 32 is connected to the control voltage end (P1, P2), and the output end of the second load branch 32 is connected to the second detection output end Vben or the first detection output end Vbep.

[0038] The switch component 34 specifically includes a plurality of time-controlled switches. The power module 30 (i.e., the VTS_BIAS_PTAT module), the first load branch 31, the second load branch 32, and the detection element 35 together constitute a detection circuit capable of detecting temperature. The calibration switch module 05 is used to dynamically compensate for the errors generated by the first load branch 31 and the second load branch 32, and the switch component 34 is used to dynamically compensate for the errors generated by the detection element 35. Among them, the calibration switch module 05 is further connected to the first clock signal clk1 and the second clock signal clk2. Among them, the first load branch 31 and the second load branch 32 are collectively referred to as load modules.

[0039] In an optional implementation, the first load branch 31 includes a first load transistor M1 and a second load transistor M2; the first electrode of the first load transistor M1 is connected to the second electrode of the second load transistor, and the second electrode is connected to the first output terminal P3 of the power module; the second load branch 32 includes a third load transistor M3 and a fourth load transistor M4; the first electrode of the third load transistor M3 is connected to the second electrode of the fourth load transistor M4, and the second electrode is connected to the first output terminal P3 of the power module; the first electrode of the second load transistor M2 is connected to the first detection output terminal Vbep or the second detection output terminal Vben through the calibration switch module 05, and the first electrode of the fourth load transistor M4 is connected to the first detection output terminal Vbep or the second detection output terminal Vben through the calibration switch module 05. The first detection output terminal Vbep and the second detection output terminal Vben are used to output the detection result. The first detection output terminal Vbep corresponds to Figure 2 The first detection output terminal 23 in the second detection output terminal Vben corresponds to Figure 2 The second detection output terminal 24 in.

[0040] The first output terminal P3 of the power module 30 is connected to the first voltage terminal VDDA, and the second output terminal P4 is connected to the second voltage terminal VSSA. In addition, the first control output terminal P1 of the power module 30 is respectively connected to the first load transistor M1 and the third load transistor M3, and is used to provide a bias voltage Vpbias to the load transistor M1 / M3, so that M1 / M3 outputs a given current; the second control output terminal P2 of the power module is respectively connected to the second load transistor M2 and the fourth load transistor M4, so as to provide a bias voltage Vpcas to the load transistor M2 / M4. Among them, M1 / M3 and M2 / M4 form two mirror current sources, which respectively provide bias currents to the detection element 35 (i.e., the PNP diode).

[0041] It can be seen that the power module 30 includes: a first output terminal P3 for providing a first power supply voltage (VDDA) for the load module; a control output terminal (such as Figure 3 P1 and P2 in the load module); a second output terminal P4 for providing a second power supply voltage (VSSA) to the detection element 35. The number of control output terminals for providing a bias voltage to the load module depends on the number of transistors included in the branch of the load module. For example, Figure 3 The load module in the embodiment includes a first load branch and a second load branch, and each load branch includes two transistors. Therefore, the number of bias power supply terminals is two, specifically including a first control output terminal P1 and a second control output terminal P2.

[0042] It can be seen that in this example, the first electrode of the first load transistor M1 is connected to the second electrode of the second load transistor M2, and the second electrode of the first load transistor M1 is connected to the first output terminal P3 of the power module 30. The second load branch includes a third load transistor M3 and a fourth load transistor M4; the first electrode of the third load transistor M3 is connected to the second electrode of the fourth load transistor M4, and the second electrode of the third load transistor M3 is connected to the first output terminal P3 of the power module 30; the first electrode of the second load transistor M2 is connected to the first detection output terminal Vbep or the second detection output terminal Vben through the calibration switch module 05, and the first electrode of the fourth load transistor M4 is connected to the first detection output terminal Vbep or the second detection output terminal Vben through the calibration switch module 05; and the control output terminal further includes: a first control output terminal P1 and a second control output terminal P2, then the control electrode of the first load transistor M1 and the control electrode of the third load transistor M3 are respectively connected to the first control output terminal P1, and the control electrode of the second load transistor M2 and the control electrode of the fourth load transistor M4 are respectively connected to the second control output terminal P2. The calibration switch module 05 is used to dynamically compensate the first load branch and the second load branch to avoid the mismatch error caused by the first load branch being fixedly connected to the first detection output terminal and the second load branch being fixedly connected to the second detection output terminal in the related art. Specifically, the output terminal of the first load branch 31 is connected to the first detection output terminal Vbep or the second detection output terminal Vben through the calibration switch module 05, and the output terminal of the second load branch 32 is connected to the first detection output terminal Vbep (corresponding to Figure 2 The first detection output terminal 23) or the second detection output terminal Vben (corresponding to Figure 2The calibration switch module 05 is configured to: control the first load branch 31 and the second load branch 32 to be alternately connected to the first detection output terminal Vbep or the second detection output terminal Vben; wherein the first load branch 31 and the second load branch 32 are not connected to the first detection output terminal Vbep or the second detection output terminal Vben at the same time. For example, when the first load branch 31 is connected to the first detection output terminal Vbep, the second load branch 32 is connected to the second detection output terminal Vben; when the second load branch 32 is connected to the first detection output terminal Vbep, the first load branch 31 is connected to the second detection output terminal Vben.

[0043] In one implementation, the calibration switch module 05 includes: a first switch subcircuit and a second switch subcircuit; wherein the first switch subcircuit includes a first switch and a second switch, the first end of the first switch is connected to the first load branch, and the second end is connected to the first detection output end; the first end of the second switch is connected to the first load branch, and the second end is connected to the second detection output end; the second switch subcircuit includes a third switch and a fourth switch, the first end of the third switch is connected to the second load branch, and the second end is connected to the first detection output end; the first end of the fourth switch is connected to the second load branch, and the second end is connected to the second detection output end; wherein the first switch and the fourth switch are configured to be turned on or off in response to a first control signal; and the second switch and the third switch are configured to be turned on or off in response to a second control signal.

[0044] Wherein, the first switch includes a first switch transistor and a second switch transistor; the first electrode of the first switch transistor is connected to the first electrode of the second switch transistor, and is connected to the output end of the first load branch; the second electrode of the first switch transistor is connected to the second electrode of the second switch transistor, and is connected to the first detection output end; the control electrode of the first switch transistor is connected to the first clock signal end, and the control electrode of the second switch transistor is connected to the second clock signal end; the second switch includes a third switch transistor and a fourth switch transistor; the first electrode of the third switch transistor is connected to the first electrode of the fourth switch transistor, and is connected to the output end of the first load branch; the second electrode of the third switch transistor is connected to the second electrode of the fourth switch transistor, and is connected to the second detection output end; the control electrode of the third switch transistor is connected to the second clock signal end, and the control electrode of the fourth switch transistor is connected to the first clock signal end; the third switch includes a fifth switch transistor and a sixth switch transistor; the first electrode of the fifth switch transistor is connected to the first electrode of the sixth switch transistor, and is connected to the first clock signal end The output end of the second load branch is connected; the second electrode of the fifth switch transistor is connected to the second electrode of the sixth switch transistor, and is connected to the first detection output end; the control electrode of the fifth switch transistor is connected to the second clock signal end, and the control electrode of the sixth switch transistor is connected to the first clock signal end; the fourth switch includes a seventh switch transistor and an eighth switch transistor; the first electrode of the seventh switch transistor is connected to the first electrode of the eighth switch transistor, and is connected to the output end of the second load branch; the second electrode of the seventh switch transistor is connected to the second electrode of the eighth switch transistor, and is connected to the second detection output end; the control electrode of the seventh switch transistor is connected to the first clock signal end, and the control electrode of the eighth switch transistor is connected to the second clock signal end; wherein the first clock signal end is used to provide a first clock signal, and the second clock signal end is used to provide a second clock signal; the first control signal is represented by the first clock signal being a first level and the second clock signal being a second level; the second control signal is represented by the first clock signal being a second level and the second clock signal being a first level.

[0045] Optionally, the first switch transistor, the third switch transistor, the fifth switch transistor, and the seventh switch transistor are P-channel field effect transistors; the second switch transistor, the fourth switch transistor, the sixth switch transistor, and the eighth switch transistor are N-channel field effect transistors.

[0046] For ease of understanding, Figure 4 FIG. 5 shows a schematic diagram of the structure of the calibration switch module 05. Figure 4As shown, the calibration switch module 05 includes: a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The above switches can be various types of switches, for example, they can be level switches or transistor switch circuits, etc. In this example, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are transistor switch circuits for illustration.

[0047] In an optional implementation, the first switch S1 includes a first switch transistor T51 and a second switch transistor T52. A first electrode of the first switch transistor T51 is connected to a first electrode of the second switch transistor T52, and both the first electrode of the first switch transistor T51 and the first electrode of the second switch transistor T52 are connected to a first load branch through a first switch input terminal In1; a second electrode of the first switch transistor T51 is connected to a second electrode of the second switch transistor T52, and both the second electrode of the first switch transistor T51 and the second electrode of the second switch transistor T52 are connected to a first detection output terminal through a first switch output terminal Out1; a control electrode of the first switch transistor T51 is connected to a first clock signal terminal to receive a first clock signal clk1, and a control electrode of the second switch transistor T52 is connected to a second clock signal terminal to receive a second clock signal clk2.

[0048] The second switch S2 includes a third switch transistor T53 and a fourth switch transistor T54. A first electrode of the third switch transistor T53 is connected to a first electrode of the fourth switch transistor T54, and both the first electrode of the third switch transistor T53 and the first electrode of the fourth switch transistor T54 are connected to the first load branch through the first switch input terminal In1; a second electrode of the third switch transistor T53 is connected to a second electrode of the fourth switch transistor T54, and both the second electrode of the third switch transistor T53 and the second electrode of the fourth switch transistor T54 are connected to the second detection output terminal through the second switch output terminal Out2; a control electrode of the third switch transistor T54 is connected to the second clock signal terminal to receive the second clock signal clk2, and a control electrode of the fourth switch transistor T54 is connected to the first clock signal terminal to receive the first clock signal clk1.

[0049] The third switch S3 includes a fifth switch transistor T55 and a sixth switch transistor T56. A first electrode of the fifth switch transistor T55 is connected to a first electrode of the sixth switch transistor T56, and both the first electrode of the fifth switch transistor T55 and the first electrode of the sixth switch transistor T55 are connected to the second load branch through the second switch input terminal In2; a second electrode of the fifth switch transistor T55 is connected to a second electrode of the sixth switch transistor T56, and both the second electrode of the fifth switch transistor T55 and the second electrode of the sixth switch transistor T56 are connected to the first detection output terminal through the first switch output terminal Out1; a control electrode of the fifth switch transistor T55 is connected to the second clock signal terminal to receive the second clock signal clk2, and a control electrode of the sixth switch transistor T56 is connected to the first clock signal terminal to receive the first clock signal clk1.

[0050] The fourth switch S4 includes a seventh switch transistor T57 and an eighth switch transistor T58. A first electrode of the seventh switch transistor T57 is connected to a first electrode of the eighth switch transistor T58, and both the first electrode of the seventh switch transistor T57 and the first electrode of the eighth switch transistor T58 are connected to the second load branch through the second switch input terminal In2; a second electrode of the seventh switch transistor T57 is connected to a second electrode of the eighth switch transistor T58, and both the second electrode of the seventh switch transistor T57 and the second electrode of the eighth switch transistor T58 are connected to the second detection output terminal through the second switch output terminal Out2; a control electrode of the seventh switch transistor T57 is connected to the first clock signal terminal to receive the first clock signal clk1, and a control electrode of the eighth switch transistor T58 is connected to the second clock signal terminal to receive the second clock signal clk2.

[0051] It can be seen from the above structure that any switch among the first switch S1 to the fourth switch S4 includes two switching transistors, and the control electrode of one of the two switching transistors always receives the first clock signal clk1, and the control electrode of the other receives the second clock signal clk2. At the same time, the levels of the first clock signal clk1 and the second clock signal clk2 are always opposite. Therefore, the conduction levels of the two switching transistors included in any switch among the first switch S1 to the fourth switch S4 are opposite. In order to achieve the above effect, one of the two switching transistors included in any switch among the first switch S1 to the fourth switch S4 is a P-type MOS tube, and the other is an N-type MOS tube.

[0052] In some examples, the first switch transistor T51, the third switch transistor T53, the fifth switch transistor T55, and the seventh switch transistor T57 are P-type MOS transistors; the second switch transistor T52, the fourth switch transistor T54, the sixth switch transistor T56, and the eighth switch transistor T58 are N-type MOS transistors, that is, one of the two switch transistors included in any switch of the first switch S1 to the fourth switch S4 is a P-type MOS transistor, and the other is an N-type MOS transistor. Based on this, in the same switch, the first electrodes of the two switch transistors are connected, that is, the source of the P-type MOS tube is connected to the drain of the N-type MOS tube; the second electrodes of the two switch transistors are connected, that is, the drain of the P-type MOS tube is connected to the source of the N-type MOS tube; the control electrodes of the P-type MOS tube and the N-type MOS tube are the gates.

[0053] In summary, when the calibration switch module receives the first control signal, that is, the first clock signal clk1 is at a low level and the second clock signal clk2 is at a high level, the first switch sub-circuit 051 is taken as an example for explanation, and the first switch sub-circuit 051 includes a first switch S1 and a second switch S2; the first switch S1 includes a first switch transistor T51 which is a P-type MOS tube and a second switch transistor T52 which is an N-type MOS tube, and the gate of the first switch transistor T51 which is a P-type MOS tube receives the first clock signal clk1 (currently at a low level), so the first switch transistor T51 is turned on, and the gate of the second switch transistor T52 which is an N-type MOS tube receives the second clock signal clk2 (currently at a high level). ), so the second switch transistor T52 is also turned on, that is, the first switch S1 is turned on, so that the first load branch is connected to the first detection output end; the second switch S2 includes a third switch transistor T53 which is a P-type MOS tube and a fourth switch transistor T54 which is an N-type MOS tube, the gate of the third switch transistor T53 which is a P-type MOS tube receives the second clock signal clk2 (currently at a high level), so the third switch transistor T53 is turned off, and the gate of the fourth switch transistor T54 which is an N-type MOS tube receives the first clock signal clk1 (currently at a low level), so the fourth switch transistor T54 is also turned off, that is, the second switch S2 is not turned on, so that the first load branch will not be connected to the second detection output end. Similarly to the above, the fifth switch transistor T55 of the third switch S3, which is a P-type MOS tube, and the sixth switch transistor T56 of the N-type MOS tube, are turned off, so the third switch S3 is not turned on, so that the second load branch is not connected to the first detection output terminal; the seventh switch transistor T57 of the fourth switch S4, which is a P-type MOS tube, and the eighth switch transistor T58 of the fourth switch S4 are turned on, so the fourth switch S4 is turned on, so that the second load branch is connected to the second detection output terminal. When the calibration switch module receives the second control signal, the levels of the first clock signal clk1 and the second clock signal clk2 in the second control signal are opposite to the levels of the first clock signal clk1 and the second clock signal clk2 in the first control signal, that is, when the first clock signal clk1 is high and the second clock signal clk2 is low, correspondingly, the on and off states of each switch transistor are opposite to the states under the first control signal, so the first switch S1 and the fourth switch S4 are not turned on, and the second switch S2 and the third switch S4 are turned on. The first load branch and the second load branch are controlled to alternately connect to the first detection output terminal and the second detection output terminal through the first clock signal clk1 and the second clock signal clk2, so that the error of the output signal of the operational amplifier caused by the offset voltage can be eliminated or reduced. In addition, the circuit provided by the present disclosure is implemented only with transistors (MOS tubes), and the circuit structure is relatively simple, so there is no need to add complex circuits and occupy circuit resources.

[0054] In addition, the first load transistor M1 and the second load transistor M2 in the first load branch 31 can be P-type MOS transistors or N-type MOS transistors. In this example, the first load transistor M1 and the second load transistor M2 are P-type MOS transistors. The source of the first load transistor M1 is connected to the drain of the second load transistor M2, and the drain of the first load transistor M1 is connected to the first switch input terminal In1 of the calibration switch module 05.

[0055] The third load transistor M3 and the fourth load transistor M4 in the second load branch 32 can be a P-type MOS transistor or an N-type MOS transistor. In this example, the third load transistor M3 and the fourth load transistor M4 are P-type MOS transistors. The source of the third load transistor M3 is connected to the drain of the fourth load transistor M4, and the drain of the third load transistor M3 is connected to the second switch input terminal In2 of the calibration switch module.

[0056] Further, the first load transistor M1 and the third load transistor M3 are cascode transistors, which are used to increase the output impedance of the operational amplifier. Specifically, the gate of the first load transistor M1 is connected to the gate of the third load transistor M3, and is commonly connected to the first bias voltage terminal to receive the first bias voltage, and the first bias voltage is used to bias the first load transistor M1 and the third load transistor M3. Further, the second load transistor M2 and the fourth load transistor M4 are common-mode output voltage load transistors.

[0057] In addition, in this example, the detection element 35 specifically includes N PNP tubes, for example, N=9. Figure 3 T1, T2, ... T9 in the figure are PNP tubes respectively, wherein, in the related art, T1 is connected alone to the first detection output terminal (i.e., connected to the left path), and eight PNP tubes T2-T9 are connected in parallel to the second detection output terminal (i.e., connected to the right path). Due to the changes brought about in the process manufacturing process, T1, T2, ... T9 cannot be completely consistent, so errors will be caused by mismatch. In order to avoid the mismatch problem, in this example, the principle of dynamic device matching is adopted, and dynamic compensation operation is performed through the switch component 34. Among them, the switch component 34 includes a plurality of time-controlled switches. Each time-controlled switch is respectively connected to the corresponding PNP tube. The plurality of time-controlled switches are configured as follows: in any time period, one detection element is connected to the first detection output terminal, and the remaining detection elements are connected to the second detection output terminal; and the detection elements connected to the first detection output terminal in each time period are different.

[0058] In this example, the time-controlled switch is a level switch, and each level switch is respectively connected to a switch clock signal terminal, and is used to change the switch state according to the switch clock signal output by the switch clock signal terminal; wherein, when the switch clock signal output by the switch clock signal terminal is a first switch level, the switch state of the time-controlled switch is a first switch state connected to the first detection output terminal; when the switch clock signal output by the switch clock signal terminal is a second switch level, the switch state of the time-controlled switch is a second switch state connected to the second detection output terminal.

[0059] It should be noted that the input signal to the switch clock signal terminal corresponding to each level switch may be controlled by software, or may be controlled manually.

[0060] In order to ensure that each PNP tube is connected to the first detection output terminal for the same length of time, the switch clock signals generated by the switch clock signal terminals corresponding to each level switch are synchronized with each other and the length of each time period is equal.

[0061] In addition, in actual situations, the detection elements in the detection circuit will implement multiple detection processes. Therefore, in order to ensure the accuracy of each detection process, the timing switch performs periodic control on each PNP tube, and accordingly, the clock signal end connected to each level switch generates a periodic clock signal according to a preset time period; therefore, when the number of detection elements and timing switches is N respectively, the preset time period includes N time periods, where N is a natural number, thereby achieving the effect of continuous dynamic compensation.

[0062] For example, at time 1, T1 is connected to the first detection output terminal, and T2 to T9 are connected to the second detection output terminal; at time 2, T9 is connected to the first detection output terminal, and T1-T8 are connected to the second detection output terminal; at time 3, T8 is connected to the first detection output terminal, and T9 and T1 to T7 are connected to the second detection output terminal; and so on, at time 9, T2 is connected to the first detection output terminal, and T3 to T9 and T1 are connected to the second detection output terminal. In this way, within the 9 moments included in a time period, the PNP tubes connected to the first detection output terminal and the second detection output terminal achieve an average of 1:8, thereby eliminating mismatch. The implementation method in each time period is similar and will not be repeated here.

[0063] It can be seen that when the number of detection elements is N (N is 9 in the above example), the multiple time periods include: each time period contained in at least one time cycle; wherein each time cycle includes N time periods, and within each time period of a time cycle, the switching state of each time-controlled switch changes dynamically, so that the detection element connected to the first detection output terminal within each time period changes dynamically. Wherein, when switching from the i-th time period to the i+1-th time period, the i-th time-controlled switch changes from the first switch state connected to the first output terminal to the second switch state connected to the second output terminal, so that the i-th detection element changes from the first detection state connected to the first detection output terminal to the second detection state connected to the second detection output terminal; and, the i+1-th time-controlled switch changes from the second switch state connected to the second output terminal to the first switch state connected to the first output terminal, so that the i+1-th detection element changes from the second detection state connected to the second detection output terminal to the first detection state connected to the first detection output terminal; wherein i and N are natural numbers, and i is less than N; and, in the i-th time period, the remaining N-1 detection elements except the i-th detection element are in the second detection state connected to the second output terminal. It can be seen that in the above process, each level switch includes a first end 01, a second end 02 and a third end 03, wherein the first end 01 is connected to the first detection output end, the second end 02 is connected to the second detection output end, and the third end 03 is connected to the detection element 35; each level switch corresponds to a switch clock signal end, and the level switch responds to the signal of the switch clock signal end to connect the first end 01 with the third end 03 or the second end 02 with the third end 03. When the first end 01 is connected to the third end 03, the level switch controls the corresponding detection element 35 to be in the first detection state connected to the first detection output end Vbep; when the second end 02 is connected to the third end 03, the level switch controls the corresponding detection element 35 to be in the second detection state connected to the second detection output end Vben.

[0064] In summary, the conventional bias current will cause a large error in the PTAT circuit during the chip processing. Furthermore, the chip processing will cause an offset voltage to the 1:1 PMOS current mirror circuit (i.e., the first load branch and the second load branch mentioned above) and the 1:N PNP tube (i.e., the detection element), thereby causing a large error in the PTAT circuit. The present disclosure uses a PTAT current to bias the existing PTAT circuit, and uses dynamic device matching technology to eliminate the mismatch error corresponding to the 1:1 PMOS current mirror and the 1:N PNP tube, thereby eliminating the mismatch voltage generated during the chip processing. The PTAT circuit used in the present disclosure can obtain better PTAT performance at a lower hardware cost, thereby improving the accuracy of the temperature sensor.

[0065] exist Figure 3 The circuit shown includes a first circuit loop composed of a load module and a calibration switch module, and a second circuit loop composed of a detection element and a switch component. In the first circuit loop, the current flows from the first output terminal P3 to the first load transistor M1 and the third load transistor M3, and from the first load transistor M1 and the third load transistor M3 to the second load transistor M2 and the fourth load transistor M4, respectively, and flows to the first detection output terminal Vbep and the second detection output terminal Vben through the calibration switch module 05. In the second circuit loop, the current flows from the second power supply terminal P4 to each detection element 35, and then flows to the first detection output terminal Vbep and the second detection output terminal Vben through each time-controlled switch 34.

[0066] In addition, another embodiment of the present invention further provides a detection method implemented based on the above-mentioned detection circuit, wherein the method includes: within any time period, at least one detection element of the switch component is connected to the first detection output terminal, and the remaining detection elements are controlled to be connected to the second detection output terminal, so that the first detection output terminal and the second detection output terminal output the detection results obtained by each detection element.

[0067] Among them, when the switch component includes N time-controlled switches, in the i-1th time period, the i-1th time-controlled switch is connected to the first detection output terminal, and the remaining time-controlled switches are connected to the second detection output terminal; in the i-th time period, the i-th time-controlled switch is connected to the first detection output terminal, and the remaining time-controlled switches are connected to the second detection output terminal, N≥i≥2.

[0068] And, when the control switch is Figure 3 In the level switch shown, in the i-1th time period, the first end of the i-1th time-controlled switch is connected to the third end, and the second ends of the remaining time-controlled switches are connected to the third end; in the i-th time period, the first end of the i-th time-controlled switch is connected to the third end, and the second ends of the remaining time-controlled switches are connected to the third end.

[0069] Wherein, in the case where the switch assembly includes a plurality of time-controlled switches respectively connected to a plurality of detection elements, when switching from the i-th time period to the i+1-th time period, the i-th time-controlled switch changes from the first switch state connected to the first output terminal to the second switch state connected to the second output terminal, so that the i-th detection element changes from the first detection state connected to the first detection output terminal to the second detection state connected to the second detection output terminal; and the i+1-th time-controlled switch changes from the second switch state connected to the second output terminal to the first switch state connected to the first output terminal, so that the i+1-th detection element changes from the second detection state connected to the second detection output terminal to the first detection state connected to the first detection output terminal; wherein i and N are natural numbers, and i is less than N; and, in the i-th time period, the remaining N-1 detection elements except the i-th detection element are in the second detection state connected to the second output terminal. The specific implementation details of the above method can refer to the description of the corresponding part in the previous embodiment, which will not be repeated here.

[0070] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A detection circuit having a first detection output terminal and a second detection output terminal, wherein: The detection circuit comprises: A plurality of detection elements are used to detect the object to be detected to obtain the detection result; a switch component, each of the detection elements is connected to the first detection output end or the second detection output end through the switch component, and the first detection output end and the second detection output end are used to output the detection result; The switch component is configured to: in any time period, connect at least one of the detection elements to the first detection output terminal, and connect the remaining detection elements to the second detection output terminal.

2. The circuit according to claim 1, wherein The switch assembly includes: a plurality of time-controlled switches, and the plurality of time-controlled switches correspond one-to-one to the plurality of detection elements.

3. The circuit according to claim 2, wherein: The number of the plurality of time-controlled switches is N. In the i-th time period, the i-th time-controlled switch is connected to the first detection output end, and the remaining time-controlled switches are connected to the second detection output end, and N≥i≥2.

4. The circuit according to claim 3, wherein: The time-controlled switches are level switches, each of which includes a first end, a second end, and a third end, the first end is connected to the first detection output end, the second end is connected to the second detection output end, and the third end is connected to the corresponding detection element; Each of the level switches corresponds to a switch clock signal terminal, and the level switch responds to a signal at the switch clock signal terminal to connect the first terminal to the third terminal or the second terminal to the third terminal.

5. The circuit according to claim 1, wherein: The detection circuit also includes: A load module, wherein an input end of the load module is connected to a first voltage end, a control end of the load module is connected to a control voltage end, and an output end of the load module is connected to the first detection output end and the second detection output end.

6. The circuit according to claim 5, wherein: The load module comprises: A first load branch, wherein an input end of the first load branch is connected to a first voltage end, a control end of the first load branch is connected to the control voltage end, and an output end of the first load branch is connected to the first detection output end or the second detection output end; A second load branch, wherein an input end of the second load branch is connected to the first voltage end, a control end of the second load branch is connected to the control voltage end, and an output end of the second load branch is connected to the second detection output end or the first detection output end.

7. The circuit according to claim 6, wherein: The detection circuit also includes: a calibration switch module, wherein the output end of the first load branch is connected to the first detection output end or the second detection output end through the calibration switch module, and the output end of the second load branch is connected to the first detection output end or the second detection output end through the calibration switch module; Wherein, the calibration switch module is configured to: control the first load branch and the second load branch to be alternately connected to the first detection output end or the second detection output end, and the first load branch and the second load branch are not connected to the first detection output end or the second detection output end at the same time.

8. The circuit according to claim 7, wherein: The calibration switch module comprises: A first switch subcircuit comprises a first switch and a second switch, wherein a first end of the first switch is connected to the first load branch, and a second end of the first switch is connected to the first detection output terminal; a first end of the second switch is connected to the first load branch, and a second end of the second switch is connected to the second detection output terminal; The second switch subcircuit comprises a third switch and a fourth switch, wherein a first end of the third switch is connected to the second load branch, and a second end of the third switch is connected to the first detection output terminal; a first end of the fourth switch is connected to the second load branch, and a second end of the fourth switch is connected to the second detection output terminal; The first switch and the fourth switch are configured to be turned on or off in response to a first control signal; and the second switch and the third switch are configured to be turned on or off in response to a second control signal.

9. The circuit according to claim 8, wherein The first switch includes a first switch transistor and a second switch transistor; a first electrode of the first switch transistor is connected to a first electrode of the second switch transistor, and is connected to an output end of the first load branch; a second electrode of the first switch transistor is connected to a second electrode of the second switch transistor, and is connected to the first detection output end; a control electrode of the first switch transistor is connected to a first clock signal end, and a control electrode of the second switch transistor is connected to a second clock signal end; The second switch includes a third switch transistor and a fourth switch transistor; a first electrode of the third switch transistor is connected to a first electrode of the fourth switch transistor, and is connected to the output end of the first load branch; a second electrode of the third switch transistor is connected to a second electrode of the fourth switch transistor, and is connected to the second detection output end; a control electrode of the third switch transistor is connected to the second clock signal end, and a control electrode of the fourth switch transistor is connected to the first clock signal end; The third switch includes a fifth switch transistor and a sixth switch transistor; The first electrode of the fifth switch transistor is connected to the first electrode of the sixth switch transistor, and is connected to the output end of the second load branch; the second electrode of the fifth switch transistor is connected to the second electrode of the sixth switch transistor, and is connected to the first detection output end; the control electrode of the fifth switch transistor is connected to the second clock signal end, and the control electrode of the sixth switch transistor is connected to the first clock signal end; The fourth switch includes a seventh switch transistor and an eighth switch transistor; The first electrode of the seventh switch transistor is connected to the first electrode of the eighth switch transistor, and is connected to the output end of the second load branch; the second electrode of the seventh switch transistor is connected to the second electrode of the eighth switch transistor, and is connected to the second detection output end; the control electrode of the seventh switch transistor is connected to the first clock signal end, and the control electrode of the eighth switch transistor is connected to the second clock signal end; Wherein, the first clock signal terminal is used to provide a first clock signal, and the second clock signal terminal is used to provide a second clock signal; The first control signal indicates that the first clock signal is at a first level and the second clock signal is at a second level; the second control signal indicates that the first clock signal is at a second level and the second clock signal is at a first level.

10. The circuit according to claim 9, wherein: The first switch transistor, the third switch transistor, the fifth switch transistor, and the seventh switch transistor are P-channel field effect transistors; The second switch transistor, the fourth switch transistor, the sixth switch transistor, and the eighth switch transistor are N-channel field effect transistors.

11. The circuit according to any one of claims 7 to 10, wherein: The circuit further comprises: A power supply module, wherein a first output end of the power supply module is connected to the first voltage end, a second output end of the power supply module is connected to the second voltage end, and a control output end of the power supply module is connected to the control voltage end.

12. The circuit according to claim 11, wherein The control output terminal of the power module includes: a first control output terminal and a second control output terminal; and the control voltage terminal includes: a first control voltage terminal connected to the first control output terminal, and a second control voltage terminal connected to the second control output terminal; The first load branch includes a first load transistor and a second load transistor; Wherein, the first electrode of the first load transistor is connected to the second electrode of the second load transistor, and the second electrode of the first load transistor is connected to the first voltage terminal; The second load branch includes a third load transistor and a fourth load transistor; the first electrode of the third load transistor is connected to the second electrode of the fourth load transistor, and the second electrode of the third load transistor is connected to the first voltage terminal; the first electrode of the second load transistor is connected to the first detection output terminal or the second detection output terminal through the calibration switch module, and the first electrode of the fourth load transistor is connected to the first detection output terminal or the second detection output terminal through the calibration switch module; Furthermore, the control electrode of the first load transistor and the control electrode of the third load transistor are respectively connected to the first control voltage terminal, and the control electrode of the second load transistor and the control electrode of the fourth load transistor are respectively connected to the second control voltage terminal.

13. The circuit according to any one of claims 1 to 10, wherein: The detection circuit is a reference source circuit.

14. A temperature sensor, wherein: The temperature sensor comprises: a detection circuit as described in any one of claims 1-13.

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