Data processing circuit board for TTE analyzer

Abstract

The utility model provides a data processing circuit board for a TTE analyzer. The data processing circuit board is designed to solve the problems of difficulty in clock distribution, low power management efficiency, limited network communication capability, low bus interface integration level and the like in the prior art. The circuit board integrates a plurality of key function modules such as the clock management module, the power management module, the processor module, the PCIE interface, the Ethernet interface and the DB9 debugging serial port, the overall performance and reliability of the system are improved, and the circuit board is suitable for a high-performance computing and communication system.

Description

Technical Field

[0001] The utility model relates to the field of electronic circuit design, and in particular to a data processing circuit board for a TTE analyzer. The circuit board integrates multiple high-speed Ethernet ports, an efficient power management module, a clock distributor, and an intelligent bus interface, and is intended to meet the high requirements for data transmission, synchronization, and power management in high-performance computing and communication systems. Background Art

[0002] With the continuous development of modern electronic equipment and communication systems, the demand for high-performance, high-reliability and multi-functional integrated circuit boards is increasing. Traditional circuit board design often faces the following problems:

[0003] Difficulty in clock signal distribution and synchronization: In complex electronic systems, each module requires a precisely synchronized clock signal. Traditional clock distribution methods may not provide sufficient output signals or meet the requirements of high-speed applications, resulting in reduced system performance.

[0004] Low power management efficiency: As more functional modules are integrated on circuit boards, the requirements for power management are getting higher and higher. Traditional power management modules are often inefficient and cannot provide stable power for high loads and complex systems.

[0005] Limited network communication capabilities: For systems that require high-speed data transmission and multi-port connections, traditional Ethernet port designs may not be able to meet the requirements of high bandwidth and low latency, affecting the overall system performance.

[0006] The bus interface integration is not high: Under the requirements of big data processing and high-speed computing, how to efficiently integrate multiple PCIe bus interfaces and ensure their stability and speed is an urgent problem to be solved.

[0007] In view of the above problems, the utility model provides an improved circuit board design, which integrates a high-performance clock distributor MC100LVEP111FA, an efficient power management module, a multi-port high-speed Ethernet connection and an intelligent bus interface, aiming to improve the overall performance and reliability of the system and meet the needs of modern high-performance computing and communication systems. Utility Model Content

[0008] The utility model aims to at least solve the technical problems existing in the prior art, and particularly innovatively proposes a data processing circuit board for a TTE analyzer.

[0009] In order to achieve the above-mentioned purpose of the utility model, the utility model provides a data processing circuit board for a TTE analyzer, which is designed to solve the problems of difficult clock distribution, low power management efficiency, limited network communication capability, and low bus interface integration in the prior art. The circuit board integrates a variety of key functional modules, improves the overall performance and reliability of the system, and is suitable for high-performance computing and communication systems.

[0010] Key Features

[0011] The integrated MC100LVEP111FA clock driver / distributor provides multiple synchronous output clock signals to ensure accurate synchronization of various parts within the system.

[0012] The LTM4644EY#PBF high-efficiency power management module is used to provide stable power for each functional module of the circuit board, adapt to the requirements of different workloads, and improve the power management efficiency of the system.

[0013] Contains 2 Ethernet ports to support high-speed data transmission and various network connection requirements, integrated P-RJHS-538XRJ45 jack and related signal processing circuits (such as GBE0_LINK1000_N and GBE0_ACT_N) to ensure the stability and efficiency of network communication.

[0014] Efficiently integrated PCIe bus interface provides fast data transmission channel and supports connection and communication of multiple devices, suitable for big data processing and high-speed computing needs.

[0015] Reasonable circuit board layout ensures signal integrity and anti-interference, especially in the case of high-speed data transmission and multi-function integration, improving the overall performance and reliability of the system.

[0016] like Figure 1 to Figure 8 As shown, the utility model provides a data processing circuit board for a TTE analyzer, which is designed to solve the problems of difficult clock distribution, low power management efficiency, limited network communication capability, and low bus interface integration in the prior art. The circuit board integrates a variety of key functional modules, improves the overall performance and reliability of the system, and is suitable for high-performance computing and communication systems. It includes a clock management module, a power management module, a processor module, a PCIE interface, an Ethernet interface, and a DB9 debugging serial port.

[0017] The clock management module receives the input clock signal from the clock generator and is connected to the power management module and the processor module to provide them with a stable and accurate clock signal.

[0018] The power management module obtains electrical energy from the main power input, and then provides stable and accurate voltage for all modules that require power, such as the processor module, clock management module, PCIE interface, Ethernet interface, etc.

[0019] The processor module is connected to the PCIE interface, the switching chip PEX8648, the Ethernet interface, and the VPX connector, and data interaction is performed through these interfaces.

[0020] The above clock management module, such as Figure 2 and Figure 3 The system shown includes a clock distribution chip D1 of model MC100LVE111FA, a clock generator U3, a decoupling capacitor for reducing power supply noise, a resistor network for impedance matching, and a resistor network for voltage division. These parts together constitute a clock management module for ensuring signal integrity and clock signal stability.

[0021] The control pin OE of the clock generator U3 is connected to the first end of the resistor R102, the second end of the resistor R102 is connected to the second end of the inductor L1, the first end of the capacitor C53 and the voltage input pin VDD of the clock generator U3, the first end of the inductor L1 is connected to the input voltage VCC3.3V, the second end of the capacitor C53 is grounded, the clock signal output pin CLK of the clock generator U3 is connected to the first end of the capacitor C58, the second end of the capacitor C58 is connected to the clock input pin CLK0 of the clock distribution chip D1, the clock signal output pin CLK* of the clock generator U3 is connected to the first end of the capacitor C95, the second end of the capacitor C95 is connected to the clock input pin CLK0* of the clock distribution chip D1, and the ground pin GND of the clock generator U3 is grounded.

[0022] The clock input pin CLK0 of the clock distribution chip D1 and the clock input pin CLK0* of the clock distribution chip D1 are connected to the clock signal output pin CLK of the clock generator U3 and the clock signal output pin CLK* of the clock generator U3 to receive the synchronous differential signal from the clock generator U3, the first end of the resistor R86 is connected to the input voltage VCC3.3V, the second end of the resistor R86 is connected to the first end of the resistor R87 and the clock input pin CLK0 of the clock distribution chip D1, the second end of the resistor R87 is grounded, the first end of the resistor R88 is connected to the input voltage VCC3.3V, the second end of the resistor R88 is connected to the first end of the resistor R89 ​​and the clock input pin CLK0* of the clock distribution chip D1, and the second end of the resistor R89 ​​is grounded;

[0023] The first end of the resistor R90 is connected to the clock input pin CLK1 of the clock distribution chip D1, the second end of the resistor R90 is grounded, the first end of the resistor R101 is connected to the clock input pin CLK1* of the clock distribution chip D1, the second end of the resistor R101 is grounded, the first end of the resistor R62 is connected to the clock selection pin CLK_SET of the clock distribution chip D1, the second end of the resistor R62 is grounded, the clock selection pin CLK_SET of the clock distribution chip D1 is connected to the clock selection signal, the first end of the capacitor C54, the first end of the capacitor C55, the The first end of capacitor C56 is connected to the input voltage VCC3.3V, the second end of capacitor C54, the second end of capacitor C55, and the second end of capacitor C56 are all grounded, the first end of capacitor C54 is also connected to the voltage input pin VCC0 of the clock distribution chip D1, the voltage input pin VCC1 of the clock distribution chip D1, the voltage input pin VCC2 of the clock distribution chip D1, the voltage input pin VCC3 of the clock distribution chip D1, and the voltage input pin VCC4 of the clock distribution chip D1, and the voltage pin VEE of the clock distribution chip D1 is grounded;

[0024] A first end of the resistor R103 is connected to a signal output pin Q0 of the clock distribution chip D1 and a first end of the capacitor C18, a second end of the resistor R103 is grounded, and a second end of the capacitor C18 is connected to a VPX connector, a first end of the resistor R104 is connected to a signal output pin Q0* of the clock distribution chip D1 and a first end of the capacitor C60, a second end of the resistor R104 is grounded, and a second end of the capacitor C60 is connected to a VPX connector, a first end of the resistor R1 is connected to a signal output pin Q1 of the clock distribution chip D1 and a first end of the capacitor C21, a second end of the resistor R1 is grounded, and a second end of the capacitor C21 is connected to the VPX connector, a first end of the resistor R8 is connected to a signal output pin Q1* of the clock distribution chip D1 and a first end of the capacitor C61, a second end of the resistor R8 is grounded, and a second end of the capacitor C61 is connected to the VPX connector, A first end of the resistor R21 is connected to a signal output pin Q2 of the clock distribution chip D1 and a first end of the capacitor C38, a second end of the resistor R21 is grounded, and a second end of the capacitor C38 is connected to a VPX connector, a first end of the resistor R35 is connected to a signal output pin Q2* of the clock distribution chip D1 and a first end of the capacitor C62, a second end of the resistor R35 is grounded, and a second end of the capacitor C62 is connected to the VPX connector, a first end of the resistor R36 is connected to a signal output pin Q3 of the clock distribution chip D1 and a first end of the capacitor C44, a second end of the resistor R36 is grounded, and a second end of the capacitor C44 is connected to the VPX connector, a first end of the resistor R57 is connected to a signal output pin Q3* of the clock distribution chip D1 and a first end of the capacitor C17, a second end of the resistor R57 is grounded, and a second end of the capacitor C17 is connected to the VPX connector;

[0025] The second end of the capacitor C18 is connected to the first end of the resistor R58 and the first end of the resistor R59, the second end of the resistor R58 is connected to the input voltage VCC3.3V, and the second end of the resistor R59 is grounded. The second end of the capacitor C60 is connected to the first end of the resistor R60 and the first end of the resistor R61, the second end of the resistor R60 is connected to the input voltage VCC3.3V, and the second end of the resistor R61 is grounded. The second end of the capacitor C21 is connected to the first end of the resistor R63 and the first end of the resistor R64, the second end of the resistor R63 is connected to the input voltage VCC3.3V, and the second end of the resistor R64 is grounded. The second end of the capacitor C61 is connected to the first end of the resistor R66 and the first end of the resistor R67, the second end of the resistor R66 is connected to the input voltage VCC3.3V, and the second end of the resistor R67 is grounded. The second end of capacitor C38 is connected to the first end of resistor R68 and the first end of resistor R69, the second end of resistor R68 is connected to the input voltage VCC3.3V, and the second end of resistor R69 is grounded. The second end of capacitor C62 is connected to the first end of resistor R70 and the first end of resistor R72, the second end of resistor R70 is connected to the input voltage VCC3.3V, and the second end of resistor R72 is grounded. The second end of capacitor C44 is connected to the first end of resistor R73 and the first end of resistor R74, the second end of resistor R73 is connected to the input voltage VCC3.3V, and the second end of resistor R74 is grounded. The second end of capacitor C17 is connected to the first end of resistor R75 and the first end of resistor R76, the second end of resistor R75 is connected to the input voltage VCC3.3V, and the second end of resistor R76 is grounded.

[0026] The clock management module in the utility model inputs a precisely synchronized clock signal to each module, so that the clock signal has a high degree of integrity and anti-interference.

[0027] The above processor modules, such as Figure 4 The processor IC1 shown has multiple voltage input pins, SATA signal pins, clock signal pins and reset signal pins;

[0028] Capacitor and inductor network for voltage input and signal processing of processor IC1,

[0029] In the above-mentioned processor module, the first end of capacitor C88, the first end of capacitor C89, the first end of capacitor C96, the first end of capacitor C98, the first end of capacitor C100, the first end of capacitor C102, the first end of capacitor C105, the first end of capacitor C108 and the first end of capacitor C111 are connected to the input voltage VCC3.3V and the voltage input pin VCC of processor IC1, the second end of capacitor C88, the second end of capacitor C89, the second end of capacitor C96, the second end of capacitor C98, the second end of capacitor C100, the second end of capacitor C102, the second end of capacitor C105, the second end of capacitor C108 and the second end of capacitor C111 are grounded and connected to the voltage input pin VCC of processor IC1, the first end of capacitor C106, the first end of capacitor C109 and the first end of capacitor C112 are connected to the input voltage VCC1.8V connected to the voltage input pin VCCQ of the processor IC1, the second end of the capacitor C106, the second end of the capacitor C109 and the second end of the capacitor C112 are grounded, the first end of the resistor R152 is connected to the input voltage VCC1.2V, the second end is connected to the first end of the capacitor C90, the first end of the capacitor C97, the first end of the capacitor C99, the first end of the capacitor C101, the first end of the capacitor C103, the first end of the capacitor C107, the first end of the capacitor C110, the first end of the capacitor C113, the voltage input pin VDDC of the processor IC1 and the voltage input pin VDD of the processor IC1, the second end of the capacitor C90, the second end of the capacitor C97, the second end of the capacitor C99, the second end of the capacitor C101, the second end of the capacitor C103, the second end of the capacitor C107, the second end of the capacitor C110 and the second end of the capacitor C113 are grounded;

[0030] The first SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C120, the first end of the capacitor C122, the first end of the capacitor C124 and the first end of the inductor L11, the second end of the capacitor C120, the second end of the capacitor C122 and the second end of the capacitor C124 are all grounded, and the second end of the inductor L11 is connected to the input voltage VCC1.2V;

[0031] The second SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C121, the first end of the capacitor C123, the first end of the capacitor C125 and the first end of the inductor L12, the second end of the capacitor C121, the second end of the capacitor C123 and the second end of the capacitor C125 are all grounded, and the second end of the inductor L12 is connected to the input voltage VCC1.2V;

[0032] The SATA voltage pin SATA_VSS of the processor IC1 is grounded, the sleep signal pin DEVSLP of the processor IC1 is connected to the first end of the resistor R155, the second end of the resistor R155 is grounded, when the pin receives the sleep signal, the device will enter the low power mode, the crystal oscillator output pin XTAL_OUT of the processor IC1 and the crystal oscillator input pin XTAL_IN of the processor IC1 are connected to the external crystal oscillator, the power reset pin PWR_RESETN of the processor IC1 is connected to the first end of the resistor R158, the second end of the resistor R158 is connected to the external reset signal, and the power reset pin PWR_RESETN of the processor IC1 is connected to the external SATA power reset signal;

[0033] The spare pin NC34 of the processor IC1 is connected to the LED indicator light, and the spare pin NC37 of the processor IC1 and the spare pin NC38 of the processor IC1 are connected to the SATA device for receiving and sending control commands and data of the SATA device.

[0034] The power management module is as follows Figure 4 As shown, the voltage input pin VIN1_0 of the buck voltage regulator chip D4, the voltage input pin VIN1_1 of the buck voltage regulator chip D4, and the voltage input pin SVIN_1 of the buck voltage regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C91, and the second end of the capacitor C91 is grounded, and the voltage input pin VIN2_0 of the buck voltage regulator chip D4, the voltage input pin VIN2_1 of the buck voltage regulator chip D4, and the voltage input pin SVIN_2 of the buck voltage regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C92, and the second end of the capacitor C92 is grounded. The voltage input pin VIN3_0 of the buck voltage regulator chip D4, the voltage input pin VIN3_1 of the buck voltage regulator chip D4, and the voltage input pin SVIN_3 of the buck voltage regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C93, and the second end of the capacitor C93 is grounded. The voltage input pin VIN4_0 of the buck regulator chip D4, the voltage input pin VIN4_1 of the buck regulator chip D4, and the voltage input pin SVIN_4 of the buck regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C94, and the second end of the capacitor C94 is grounded;

[0035] The enable pin RUN1 of the buck regulator chip D4, the enable pin RUN2 of the buck regulator chip D4, the enable pin RUN3 of the buck regulator chip D4, and the enable pin RUN4 of the buck regulator chip D4 are connected to the PEX8648 switching module and the first end of the resistor R283, and the second end of the resistor R283 is connected to the input voltage VCC5V;

[0036] The voltage output pin VOUT1_0 of the buck voltage regulator chip D4, the voltage output pin VOUT1_1 of the buck voltage regulator chip D4 and the voltage output pin VOUT1_2 of the buck voltage regulator chip D4 are connected to the first end of the capacitor C283 and the output voltage PEX_2V5, the second end of the capacitor C283 is grounded, the feedback pin FB1 of the buck voltage regulator chip D4 is connected to the first end of the resistor R284, the second end of the resistor R284 is connected to the second end of the capacitor C280, the second end of the capacitor C280 is grounded, the first end of the capacitor C280 is connected to the voltage tracking and soft start pin TRACK|SS1 of the buck voltage regulator chip D4, the power good indication pin PGOOD1 of the buck voltage regulator chip D4 is connected to the first end of the resistor R285, and the second end of the resistor R285 is connected to the internal power pin INTVCC1 of the buck voltage regulator chip D4;

[0037] The voltage output pin VOUT2_0 of the buck voltage regulator chip D4, the voltage output pin VOUT2_1 of the buck voltage regulator chip D4, the voltage output pin VOUT2_2 of the buck voltage regulator chip D4, the voltage output pin VOUT3_0 of the buck voltage regulator chip D4, the voltage output pin VOUT3_1 of the buck voltage regulator chip D4, the voltage output pin VOUT3_2 of the buck voltage regulator chip D4, the voltage output pin VOUT4_0 of the buck voltage regulator chip D4, the voltage output pin VOUT4_1 of the buck voltage regulator chip D4 and the voltage output pin VOUT4_2 of the buck voltage regulator chip D4 are connected to the first end of the capacitor C282, the first end of the capacitor C284, the first end of the capacitor C285 and the output voltage PEX_1V0, the second end of the capacitor C282, the second end of the capacitor C284 and the second end of the capacitor C285 are grounded, and the reverse end of the buck voltage regulator chip D4 is connected to the ground. The feedback pin FB2, the feedback pin FB3 of the buck regulator chip D4 and the feedback pin FB4 of the buck regulator chip D4 are connected to the first end of the resistor R287, the second end of the resistor R287 is grounded, the voltage tracking and soft-start pin TRACK|SS2 of the buck regulator chip D4, the voltage tracking and soft-start pin TRACK|SS3 of the buck regulator chip D4 and the voltage tracking and soft-start pin TRACK|SS4 of the buck regulator chip D4 are connected to the first end of the capacitor C281, the second end of the capacitor C281 is grounded, the power good indication pin PGOOD2 of the buck regulator chip D4, the power good indication pin PGOOD3 of the buck regulator chip D4 and the power good indication pin PGOOD4 of the buck regulator chip D4 are connected to the first end of the resistor R286, and the second end of the resistor R286 is connected to the internal power pin INTVCC2 of the buck regulator chip D4;

[0038] The internal power supply pin INTVCC1 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE1 of the buck voltage regulator chip D4, the internal power supply pin INTVCC2 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE2 of the buck voltage regulator chip D4, the internal power supply pin INTVCC3 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE3 of the buck voltage regulator chip D4, and the internal power supply pin INTVCC4 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE4 of the buck voltage regulator chip D4;

[0039] The ground pin SGND of the buck regulator chip D4, the ground pin GND_0 of the buck regulator chip D4, the ground pin GND_1 of the buck regulator chip D4, the ground pin GND_2 of the buck regulator chip D4, the ground pin GND_3 of the buck regulator chip D4, the ground pin GND_4 of the buck regulator chip D4, the ground pin GND_5 of the buck regulator chip D4, the ground pin GND_6 of the buck regulator chip D4, the ground pin GND_7 of the buck regulator chip D4, the ground pin GND_8 of the buck regulator chip D4, the ground pin GND_9 of the buck regulator chip D 4, the ground pin GND_11 of the buck voltage regulator chip D4, the ground pin GND_12 of the buck voltage regulator chip D4, the ground pin GND_13 of the buck voltage regulator chip D4, the ground pin GND_14 of the buck voltage regulator chip D4, the ground pin GND_15 of the buck voltage regulator chip D4, the ground pin GND_16 of the buck voltage regulator chip D4, the ground pin GND_17 of the buck voltage regulator chip D4, the ground pin GND_18 of the buck voltage regulator chip D4, the ground pin GND_19 of the buck voltage regulator chip D4 and the ground pin GND_20 of the buck voltage regulator chip D4 are all grounded;

[0040] The input voltage VCC5V is converted into stable output voltages PEX_2V5 and PEX_1V0 through the step-down regulator chip D4.

[0041] In a preferred implementation manner of the present utility model, the power management module further includes a step-down voltage regulator chip D4 whose model is LTM4644EY#PBF.

[0042] The power management module in the utility model is used to solve the problem that as more functional modules are integrated on a circuit board, the traditional power management module has low efficiency and cannot provide stable power for high-load and complex systems.

[0043] The above PEX8648 switch module is as follows Figure 5As shown, it includes a switching chip U2, 4 PCIE X4 interfaces and a single PCIE X4 interface. The first end of the 4 PCIE X4 interface is connected to the VPX connector, the second end of the 4 PCIE X4 interface is connected to the switching chip U2, the first end of the single PCIE X4 interface is connected to the switching chip, and the second end of the single PCIE X4 interface is connected to the processor module.

[0044] The above-mentioned PEX8648 switching module includes a network transmission indication pin of a U2 switching chip connected to an LED lamp holder to indicate the network transmission status.

[0045] The Ethernet interface module is as follows Figure 6 As shown, it includes an Ethernet interface ETH0, a network transmission indicator light and a capacitor filtering network. The network signal transmission pins 1 to 8 of the Ethernet interface ETH0 are used for data transmission of Gigabit Ethernet. The indicator light pin 9 of the Ethernet interface ETH0 receives the network activity signal GBE0_ACT_N. When data is transmitted, the LED light is on. The indicator light pin 9 of the Ethernet interface ETH0 is connected to the first end of the capacitor C6, and the second end of the capacitor C6 is grounded. The indicator light pin 10 of the Ethernet interface ETH0 is connected to the first end of the resistor R9, and the second end of the resistor R9 is connected to the input voltage LED_2V5.

[0046] The indicator light pin 11 of the Ethernet interface ETH0 receives the network connection signal LINK1000_N. When the link is successful, the LED light is on. The indicator light pin 11 of the Ethernet interface ETH0 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded. The indicator light pin 12 of the Ethernet interface ETH0 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the input voltage LED_2V5;

[0047] The above VPX connector modules are as follows Figure 7 As shown, the first end of the VPX connector is connected to the PEX8648 switching module of the data processing circuit board through a 4-way PCIE X4 interface, the second end of the VPX connector module is connected to four data acquisition circuit boards through four single-way PCIE X4 interfaces, and the power transmission end of the VPX connector module is connected to the power board.

[0048] The processor module, VPX connector, PEX8648 switching module, PCIE interface module and Ethernet interface module in the utility model together constitute a data processing and transmission module. After network data is obtained from a 4-way data acquisition circuit board, the data is transmitted to a host computer through an Ethernet interface after being processed by the processor module. The utility model is used to solve the problem of low bus interface integration in the current TTE network analyzer, and can ensure that multiple PCIe bus interfaces can be efficiently integrated and their stability and speed can be guaranteed under the requirements of big data processing and high-speed computing.

[0049] In summary, due to the adoption of the above technical solutions, the utility model can improve the stability and synchronization of clock signals, enhance power management efficiency, improve network communication capabilities, and enhance data transmission speed and reliability.

[0050] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0052] Figure 1 It is the system block diagram of the data processing circuit board.

[0053] Figure 2 It is the circuit diagram of the clock generator.

[0054] Figure 3 This is the circuit diagram of the clock management module.

[0055] Figure 4 This is the circuit diagram of the power management module.

[0056] Figure 5 This is a partial circuit diagram of the processor module.

[0057] Figure 6 This is a partial circuit diagram of the switching module.

[0058] Figure 7 This is a partial circuit diagram of the Ethernet interface module.

[0059] Figure 8 This is a partial circuit diagram of the VPX connector module. DETAILED DESCRIPTION

[0060] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0061] The utility model provides a data processing circuit board for a TTE analyzer, which is designed to solve the problems of difficult clock distribution, low power management efficiency, limited network communication capabilities, and low bus interface integration in the prior art. The circuit board integrates multiple key functional modules, improves the overall performance and reliability of the system, and is suitable for high-performance computing and communication systems.

[0062] like Figure 1 to Figure 8 As shown, it includes a clock management module, a power management module, a processor module, a PCIE interface, an Ethernet interface, and a DB9 debugging serial port.

[0063] The clock management module receives the input clock signal from the main clock source and is connected to the power management module and the processor module to provide them with a stable and accurate clock signal.

[0064] The power management module obtains electrical energy from the main power input, and then provides stable and accurate voltage for all modules that require power, such as the processor module, clock management module, PCIE interface, Ethernet interface, etc.

[0065] The processor module is connected to the PCIE interface, the switching chip PEX8648, the Ethernet interface, and the VPX connector, and data interaction is performed through these interfaces.

[0066] The above-mentioned clock management module includes the MC100LVE111FA clock distribution chip D1, the clock generator U3, the decoupling capacitor for reducing power supply noise, and the resistor network for impedance matching and the resistor network for voltage division. These three parts together constitute the clock management module for ensuring the signal integrity and stability of the clock signal.

[0067] The control pin OE of the clock generator U3 is connected to the first end of the resistor R102, the second end of the resistor R102 is connected to the second end of the inductor L1, the first end of the capacitor C53 and the voltage input pin VDD of the clock generator U3, the first end of the inductor L1 is connected to the input voltage VCC3.3V, the second end of the capacitor C53 is grounded, the clock signal output pin CLK of the clock generator U3 is connected to the first end of the capacitor C58, the second end of the capacitor C58 is connected to the clock input pin CLK0 of the clock distribution chip D1, the clock signal output pin CLK* of the clock generator U3 is connected to the first end of the capacitor C95, the second end of the capacitor C95 is connected to the clock input pin CLK0* of the clock distribution chip D1, and the ground pin GND of the clock generator U3 is grounded.

[0068] The clock input pin CLK0 of the clock distribution chip D1 and the clock input pin CLK0* of the clock distribution chip D1 are connected to the clock signal output pin CLK of the clock generator U3 and the clock signal output pin CLK* of the clock generator U3 to receive the synchronous differential signal from the clock generator U3, the first end of the resistor R86 is connected to the input voltage VCC3.3V, the second end of the resistor R86 is connected to the first end of the resistor R87 and the clock input pin CLK0 of the clock distribution chip D1, the second end of the resistor R87 is grounded, the first end of the resistor R88 is connected to the input voltage VCC3.3V, the second end of the resistor R88 is connected to the first end of the resistor R89 ​​and the clock input pin CLK0* of the clock distribution chip D1, and the second end of the resistor R89 ​​is grounded;

[0069] The first end of the resistor R90 is connected to the clock input pin CLK1 of the clock distribution chip D1, the second end of the resistor R90 is grounded, the first end of the resistor R101 is connected to the clock input pin CLK1* of the clock distribution chip D1, the second end of the resistor R101 is grounded, the first end of the resistor R62 is connected to the clock selection pin CLK_SET of the clock distribution chip D1, the second end of the resistor R62 is grounded, the clock selection pin CLK_SET of the clock distribution chip D1 is connected to the clock selection signal, the first end of the capacitor C54, the first end of the capacitor C55, the The first end of capacitor C56 is connected to the input voltage VCC3.3V, the second end of capacitor C54, the second end of capacitor C55, and the second end of capacitor C56 are all grounded, the first end of capacitor C54 is also connected to the voltage input pin VCC0 of the clock distribution chip D1, the voltage input pin VCC1 of the clock distribution chip D1, the voltage input pin VCC2 of the clock distribution chip D1, the voltage input pin VCC3 of the clock distribution chip D1, and the voltage input pin VCC4 of the clock distribution chip D1, and the voltage pin VEE of the clock distribution chip D1 is grounded;

[0070] A first end of the resistor R103 is connected to a signal output pin Q0 of the clock distribution chip D1 and a first end of the capacitor C18, a second end of the resistor R103 is grounded, and a second end of the capacitor C18 is connected to a VPX connector, a first end of the resistor R104 is connected to a signal output pin Q0* of the clock distribution chip D1 and a first end of the capacitor C60, a second end of the resistor R104 is grounded, and a second end of the capacitor C60 is connected to a VPX connector, a first end of the resistor R1 is connected to a signal output pin Q1 of the clock distribution chip D1 and a first end of the capacitor C21, a second end of the resistor R1 is grounded, and a second end of the capacitor C21 is connected to the VPX connector, a first end of the resistor R8 is connected to a signal output pin Q1* of the clock distribution chip D1 and a first end of the capacitor C61, a second end of the resistor R8 is grounded, and a second end of the capacitor C61 is connected to the VPX connector, A first end of the resistor R21 is connected to a signal output pin Q2 of the clock distribution chip D1 and a first end of the capacitor C38, a second end of the resistor R21 is grounded, and a second end of the capacitor C38 is connected to a VPX connector, a first end of the resistor R35 is connected to a signal output pin Q2* of the clock distribution chip D1 and a first end of the capacitor C62, a second end of the resistor R35 is grounded, and a second end of the capacitor C62 is connected to the VPX connector, a first end of the resistor R36 is connected to a signal output pin Q3 of the clock distribution chip D1 and a first end of the capacitor C44, a second end of the resistor R36 is grounded, and a second end of the capacitor C44 is connected to the VPX connector, a first end of the resistor R57 is connected to a signal output pin Q3* of the clock distribution chip D1 and a first end of the capacitor C17, a second end of the resistor R57 is grounded, and a second end of the capacitor C17 is connected to the VPX connector;

[0071] The second end of the capacitor C18 is connected to the first end of the resistor R58 and the first end of the resistor R59, the second end of the resistor R58 is connected to the input voltage VCC3.3V, and the second end of the resistor R59 is grounded. The second end of the capacitor C60 is connected to the first end of the resistor R60 and the first end of the resistor R61, the second end of the resistor R60 is connected to the input voltage VCC3.3V, and the second end of the resistor R61 is grounded. The second end of the capacitor C21 is connected to the first end of the resistor R63 and the first end of the resistor R64, the second end of the resistor R63 is connected to the input voltage VCC3.3V, and the second end of the resistor R64 is grounded. The second end of the capacitor C61 is connected to the first end of the resistor R66 and the first end of the resistor R67, the second end of the resistor R66 is connected to the input voltage VCC3.3V, and the second end of the resistor R67 is grounded. The second end of capacitor C38 is connected to the first end of resistor R68 and the first end of resistor R69, the second end of resistor R68 is connected to the input voltage VCC3.3V, and the second end of resistor R69 is grounded. The second end of capacitor C62 is connected to the first end of resistor R70 and the first end of resistor R72, the second end of resistor R70 is connected to the input voltage VCC3.3V, and the second end of resistor R72 is grounded. The second end of capacitor C44 is connected to the first end of resistor R73 and the first end of resistor R74, the second end of resistor R73 is connected to the input voltage VCC3.3V, and the second end of resistor R74 is grounded. The second end of capacitor C17 is connected to the first end of resistor R75 and the first end of resistor R76, the second end of resistor R75 is connected to the input voltage VCC3.3V, and the second end of resistor R76 is grounded.

[0072] In a preferred embodiment of the present utility model, the clock management module includes: the inductance value of the inductor L1 is 22uH, the capacitance value of the capacitor C53 is 0.1uF, the resistance value of the resistor R102 is 4.7kΩ, and the capacitance values ​​of the capacitors C58 and C95 are 0.1uF;

[0073] The resistance values ​​of resistors R86 and R87 are 7.5kΩ, the resistance values ​​of resistors R87, R89, R90, R101 and R62 are 10kΩ, the capacitance of capacitor C54 is 10uF, the resistance values ​​of capacitors C55 and C56 are 0.1uF, the resistance values ​​of resistors R103, R104, R1, R8, R21, R35, R36 and R57 are 120Ω, the resistance values ​​of resistors R59, R61, R64, R67, R69, R72, R74 and R76 are 1kΩ, and the resistance values ​​of resistors R58, R60, R63, R66, R68, R70, R73 and R75 are 10kΩ.

[0074] In the above-mentioned processor module, the first end of capacitor C88, the first end of capacitor C89, the first end of capacitor C96, the first end of capacitor C98, the first end of capacitor C100, the first end of capacitor C102, the first end of capacitor C105, the first end of capacitor C108 and the first end of capacitor C111 are connected to the input voltage VCC3.3V and the voltage input pin VCC of processor IC1, the second end of capacitor C88, the second end of capacitor C89, the second end of capacitor C96, the second end of capacitor C98, the second end of capacitor C100, the second end of capacitor C102, the second end of capacitor C105, the second end of capacitor C108 and the second end of capacitor C111 are grounded and connected to the voltage input pin VCC of processor IC1, the first end of capacitor C106, the first end of capacitor C109 and the first end of capacitor C112 are connected to the input voltage VCC1.8V connected to the voltage input pin VCCQ of the processor IC1, the second end of the capacitor C106, the second end of the capacitor C109 and the second end of the capacitor C112 are grounded, the first end of the resistor R152 is connected to the input voltage VCC1.2V, the second end is connected to the first end of the capacitor C90, the first end of the capacitor C97, the first end of the capacitor C99, the first end of the capacitor C101, the first end of the capacitor C103, the first end of the capacitor C107, the first end of the capacitor C110, the first end of the capacitor C113, the voltage input pin VDDC of the processor IC1 and the voltage input pin VDD of the processor IC1, the second end of the capacitor C90, the second end of the capacitor C97, the second end of the capacitor C99, the second end of the capacitor C101, the second end of the capacitor C103, the second end of the capacitor C107, the second end of the capacitor C110 and the second end of the capacitor C113 are grounded;

[0075] The first SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C120, the first end of the capacitor C122, the first end of the capacitor C124 and the first end of the inductor L11, the second end of the capacitor C120, the second end of the capacitor C122 and the second end of the capacitor C124 are all grounded, and the second end of the inductor L11 is connected to the input voltage VCC1.2V;

[0076] The second SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C121, the first end of the capacitor C123, the first end of the capacitor C125 and the first end of the inductor L12, the second end of the capacitor C121, the second end of the capacitor C123 and the second end of the capacitor C125 are all grounded, and the second end of the inductor L12 is connected to the input voltage VCC1.2V;

[0077] The SATA voltage pin SATA_VSS of the processor IC1 is grounded, the sleep signal pin DEVSLP of the processor IC1 is connected to the first end of the resistor R155, the second end of the resistor R155 is grounded, when the pin receives the sleep signal, the device will enter the low power mode, the crystal oscillator output pin XTAL_OUT of the processor IC1 and the crystal oscillator input pin XTAL_IN of the processor IC1 are connected to the external crystal oscillator, the power reset pin PWR_RESETN of the processor IC1 is connected to the first end of the resistor R158, the second end of the resistor R158 is connected to the external reset signal, and the power reset pin PWR_RESETN of the processor IC1 is connected to the external SATA power reset signal;

[0078] The spare pin NC34 of the processor IC1 is connected to the LED indicator light, and the spare pin NC37 of the processor IC1 and the spare pin NC38 of the processor IC1 are connected to the SATA device for receiving and sending control commands and data of the SATA device.

[0079] In a preferred embodiment of the present invention, the processor module further includes: the capacitance of capacitor C88, capacitor C89 and capacitor C96 is 1uF, the capacitance of capacitor C98, capacitor C100, capacitor C102, capacitor C105, capacitor C10 and capacitor C111 is 0.1uF, the capacitance of capacitor C106 is 1uF, the capacitance of capacitor C109 and capacitor C112 is 1uF, the capacitance of capacitor C90, capacitor C99 and capacitor C The capacitance of 101 is 10uF, the capacitance of capacitor C101, capacitor C103, capacitor C107, capacitor C110 and capacitor C113 is 4.7uF, the capacitance of capacitor C120, capacitor C121, capacitor C122 and capacitor C123 is 0.1uF, the capacitance of capacitor C124 and capacitor C125 is 10uF, the inductance of inductor L11 and inductor L12 is 22uH, and the resistance of resistor R155 is 1kΩ.

[0080] In the above solution, the power management module includes: Figure 3As shown, the voltage input pin VIN1_0 of the buck voltage regulator chip D4, the voltage input pin VIN1_1 of the buck voltage regulator chip D4, and the voltage input pin SVIN_1 of the buck voltage regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C91, and the second end of the capacitor C91 is grounded, and the voltage input pin VIN2_0 of the buck voltage regulator chip D4, the voltage input pin VIN2_1 of the buck voltage regulator chip D4, and the voltage input pin SVIN_2 of the buck voltage regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C92, and the second end of the capacitor C92 is grounded. The voltage input pin VIN3_0 of the buck voltage regulator chip D4, the voltage input pin VIN3_1 of the buck voltage regulator chip D4, and the voltage input pin SVIN_3 of the buck voltage regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C93, and the second end of the capacitor C93 is grounded. The voltage input pin VIN4_0 of the buck regulator chip D4, the voltage input pin VIN4_1 of the buck regulator chip D4, and the voltage input pin SVIN_4 of the buck regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C94, and the second end of the capacitor C94 is grounded;

[0081] The enable pin RUN1 of the buck regulator chip D4, the enable pin RUN2 of the buck regulator chip D4, the enable pin RUN3 of the buck regulator chip D4, and the enable pin RUN4 of the buck regulator chip D4 are connected to the PEX8648 switching module and the first end of the resistor R283, and the second end of the resistor R283 is connected to the input voltage VCC5V;

[0082] The voltage output pin VOUT1_0 of the buck voltage regulator chip D4, the voltage output pin VOUT1_1 of the buck voltage regulator chip D4 and the voltage output pin VOUT1_2 of the buck voltage regulator chip D4 are connected to the first end of the capacitor C283 and the output voltage PEX_2V5, the second end of the capacitor C283 is grounded, the feedback pin FB1 of the buck voltage regulator chip D4 is connected to the first end of the resistor R284, the second end of the resistor R284 is connected to the second end of the capacitor C280, the second end of the capacitor C280 is grounded, the first end of the capacitor C280 is connected to the voltage tracking and soft start pin TRACK|SS1 of the buck voltage regulator chip D4, the power good indication pin PGOOD1 of the buck voltage regulator chip D4 is connected to the first end of the resistor R285, and the second end of the resistor R285 is connected to the internal power pin INTVCC1 of the buck voltage regulator chip D4;

[0083] The voltage output pin VOUT2_0 of the buck voltage regulator chip D4, the voltage output pin VOUT2_1 of the buck voltage regulator chip D4, the voltage output pin VOUT2_2 of the buck voltage regulator chip D4, the voltage output pin VOUT3_0 of the buck voltage regulator chip D4, the voltage output pin VOUT3_1 of the buck voltage regulator chip D4, the voltage output pin VOUT3_2 of the buck voltage regulator chip D4, the voltage output pin VOUT4_0 of the buck voltage regulator chip D4, the voltage output pin VOUT4_1 of the buck voltage regulator chip D4 and the voltage output pin VOUT4_2 of the buck voltage regulator chip D4 are connected to the first end of the capacitor C282, the first end of the capacitor C284, the first end of the capacitor C285 and the output voltage PEX_1V0, the second end of the capacitor C282, the second end of the capacitor C284 and the second end of the capacitor C285 are grounded, and the reverse end of the buck voltage regulator chip D4 is connected to the ground. The feedback pin FB2, the feedback pin FB3 of the buck regulator chip D4 and the feedback pin FB4 of the buck regulator chip D4 are connected to the first end of the resistor R287, the second end of the resistor R287 is grounded, the voltage tracking and soft-start pin TRACK|SS2 of the buck regulator chip D4, the voltage tracking and soft-start pin TRACK|SS3 of the buck regulator chip D4 and the voltage tracking and soft-start pin TRACK|SS4 of the buck regulator chip D4 are connected to the first end of the capacitor C281, the second end of the capacitor C281 is grounded, the power good indication pin PGOOD2 of the buck regulator chip D4, the power good indication pin PGOOD3 of the buck regulator chip D4 and the power good indication pin PGOOD4 of the buck regulator chip D4 are connected to the first end of the resistor R286, and the second end of the resistor R286 is connected to the internal power pin INTVCC2 of the buck regulator chip D4;

[0084] The internal power supply pin INTVCC1 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE1 of the buck voltage regulator chip D4, the internal power supply pin INTVCC2 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE2 of the buck voltage regulator chip D4, the internal power supply pin INTVCC3 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE3 of the buck voltage regulator chip D4, and the internal power supply pin INTVCC4 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE4 of the buck voltage regulator chip D4;

[0085] The ground pin SGND of the buck regulator chip D4, the ground pin GND_0 of the buck regulator chip D4, the ground pin GND_1 of the buck regulator chip D4, the ground pin GND_2 of the buck regulator chip D4, the ground pin GND_3 of the buck regulator chip D4, the ground pin GND_4 of the buck regulator chip D4, the ground pin GND_5 of the buck regulator chip D4, the ground pin GND_6 of the buck regulator chip D4, the ground pin GND_7 of the buck regulator chip D4, the ground pin GND_8 of the buck regulator chip D4, the ground pin GND_9 of the buck regulator chip D 4, the ground pin GND_11 of the buck voltage regulator chip D4, the ground pin GND_12 of the buck voltage regulator chip D4, the ground pin GND_13 of the buck voltage regulator chip D4, the ground pin GND_14 of the buck voltage regulator chip D4, the ground pin GND_15 of the buck voltage regulator chip D4, the ground pin GND_16 of the buck voltage regulator chip D4, the ground pin GND_17 of the buck voltage regulator chip D4, the ground pin GND_18 of the buck voltage regulator chip D4, the ground pin GND_19 of the buck voltage regulator chip D4 and the ground pin GND_20 of the buck voltage regulator chip D4 are all grounded;

[0086] The input voltage VCC5V is converted into stable output voltages PEX_2V5 and PEX_1V0 through the step-down regulator chip D4.

[0087] In a preferred embodiment of the utility model, the power management module also includes capacitors C91, C92, C93 and C94, each having a capacitance of 22uF, resistor R284 having a resistance of 19.1kΩ, capacitor C280 having a capacitance of 0.1uF, resistor R285 and resistor R286 having a resistance of 10kΩ, capacitor C281 having a capacitance of 0.1uF, resistor R287 having a resistance of 30.1kΩ, and capacitors C282, C284 and C285 having a capacitance of 47uF.

[0088] The above-mentioned PEX8648 switching module includes a switching chip U2, 4 PCIE X4 interfaces and a single PCIE X4 interface, the first end of the 4 PCIE X4 interface is connected to the VPX connector, the second end of the 4 PCIE X4 interface is connected to the switching chip U2, the first end of the single PCIE X4 interface is connected to the switching chip, and the second end of the single PCIE X4 interface is connected to the processor module.

[0089] The above-mentioned PEX8648 switching module includes a network transmission indication pin of a U2 switching chip connected to an LED lamp holder to indicate the network transmission status.

[0090] The Ethernet interface module includes an Ethernet interface ETH0, a network transmission indicator light and a capacitor filter network. The network signal transmission pins 1 to 8 of the Ethernet interface ETH0 are used for Gigabit Ethernet data transmission. The indicator light pin 9 of the Ethernet interface ETH0 receives a network activity signal GBE0_ACT_N. When data is transmitted, the LED light is on. The indicator light pin 9 of the Ethernet interface ETH0 is connected to a first end of a capacitor C6, and a second end of the capacitor C6 is grounded. The indicator light pin 10 of the Ethernet interface ETH0 is connected to a first end of a resistor R9, and a second end of the resistor R9 is connected to an input voltage LED_2V5.

[0091] The indicator light pin 11 of the Ethernet interface ETH0 receives the network connection signal LINK1000_N. When the link is successful, the LED light is on. The indicator light pin 11 of the Ethernet interface ETH0 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded. The indicator light pin 12 of the Ethernet interface ETH0 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the input voltage LED_2V5;

[0092] In a preferred implementation manner of the present utility model, the Ethernet interface module further includes: the capacitance of capacitor C4 and capacitor C6 is 4700pF, and the resistance of capacitor R9 and capacitor R10 is 330Ω.

[0093] The first end of the above-mentioned VPX connector module is connected to the PEX8648 switching module of the data processing circuit board through a 4-way PCIE X4 interface, the second end of the VPX connector module is connected to the four data acquisition circuit boards through four single-way PCIE X4 interfaces, and the power transmission end of the VPX connector module is connected to the power board.

[0094] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A data processing circuit board for a TTE analyzer, characterized in that: include: Clock management module, power management module, processor module, PEX8648 switch module, VPX connector, PCIE interface, Ethernet interface module and DB9 debug serial port; The clock signal output pin of the clock management module is connected to the VPX connector and the PEX8648 switch module, the voltage output pin of the power management module is connected to the PEX8648 switch module, the processor module is connected to the PEX8648 switch module through a single PCIE X4 interface, the processor module is connected to the Ethernet interface, the processor module is connected to the DB9 debug serial port, the PEX8648 switch module is connected to the VPX connector through a 4-way PCIE X4 interface, the data processing circuit board transmits the network signal to the host computer through the Ethernet interface module, and the data processing circuit board receives the TTE network data from the data acquisition circuit board through the VPX connector.

2. The data processing circuit board for a TTE analyzer according to claim 1, characterized in that: The clock management module includes: The control pin OE of the clock generator U3 is connected to the first end of the resistor R102, the second end of the resistor R102 is connected to the first end of the inductor L1, the first end of the capacitor C53 and the voltage input pin VDD of the clock generator U3, the second end of the inductor L1 is connected to the input voltage VCC3.3V, the second end of the capacitor C53 is grounded, the clock signal output pin CLK of the clock generator U3 is connected to the first end of the capacitor C58, the second end of the capacitor C58 is connected to the clock input pin CLK0 of the clock distribution chip D1, the clock signal output pin CLK* of the clock generator U3 is connected to the first end of the capacitor C95, the second end of the capacitor C95 is connected to the clock input pin CLK0* of the clock distribution chip D1, and the ground pin GND of the clock generator U3 is grounded; A first end of the resistor R86 is connected to the input voltage VCC3.3V, a second end of the resistor R86 is connected to a first end of the resistor R87 and a clock input pin CLK0 of the clock distribution chip D1, a second end of the resistor R87 is grounded, a first end of the resistor R88 is connected to the input voltage VCC3.3V, a second end of the resistor R88 is connected to a first end of the resistor R89 ​​and a clock input pin CLK0* of the clock distribution chip D1, and a second end of the resistor R89 ​​is grounded; The first end of the resistor R90 is connected to the clock input pin CLK1 of the clock distribution chip D1, the second end of the resistor R90 is grounded, the first end of the resistor R101 is connected to the clock input pin CLK1* of the clock distribution chip D1, the second end of the resistor R101 is grounded, the first end of the resistor R62 is connected to the clock selection pin CLK_SET of the clock distribution chip D1, the second end of the resistor R62 is grounded, the clock selection pin CLK_SET of the clock distribution chip D1 is connected to the clock selection signal, the first end of the capacitor C54, the first end of the capacitor C55, the The first end of capacitor C56 is connected to the input voltage VCC3.3V, the second end of capacitor C54, the second end of capacitor C55, and the second end of capacitor C56 are all grounded, the first end of capacitor C54 is also connected to the voltage input pin VCC0 of the clock distribution chip D1, the voltage input pin VCC1 of the clock distribution chip D1, the voltage input pin VCC2 of the clock distribution chip D1, the voltage input pin VCC3 of the clock distribution chip D1, and the voltage input pin VCC4 of the clock distribution chip D1, and the voltage pin VEE of the clock distribution chip D1 is grounded; A first end of the resistor R103 is connected to a signal output pin Q0 of the clock distribution chip D1 and a first end of the capacitor C18, a second end of the resistor R103 is grounded, and a second end of the capacitor C18 is connected to a VPX connector, a first end of the resistor R104 is connected to a signal output pin Q0* of the clock distribution chip D1 and a first end of the capacitor C60, a second end of the resistor R104 is grounded, and a second end of the capacitor C60 is connected to a VPX connector, a first end of the resistor R1 is connected to a signal output pin Q1 of the clock distribution chip D1 and a first end of the capacitor C21, a second end of the resistor R1 is grounded, and a second end of the capacitor C21 is connected to the VPX connector, a first end of the resistor R8 is connected to a signal output pin Q1* of the clock distribution chip D1 and a first end of the capacitor C61, a second end of the resistor R8 is grounded, and a second end of the capacitor C61 is connected to the VPX connector, A first end of the resistor R21 is connected to a signal output pin Q2 of the clock distribution chip D1 and a first end of the capacitor C38, a second end of the resistor R21 is grounded, and a second end of the capacitor C38 is connected to a VPX connector, a first end of the resistor R35 is connected to a signal output pin Q2* of the clock distribution chip D1 and a first end of the capacitor C62, a second end of the resistor R35 is grounded, and a second end of the capacitor C62 is connected to the VPX connector, a first end of the resistor R36 is connected to a signal output pin Q3 of the clock distribution chip D1 and a first end of the capacitor C44, a second end of the resistor R36 is grounded, and a second end of the capacitor C44 is connected to the VPX connector, a first end of the resistor R57 is connected to a signal output pin Q3* of the clock distribution chip D1 and a first end of the capacitor C17, a second end of the resistor R57 is grounded, and a second end of the capacitor C17 is connected to the VPX connector; The second end of the capacitor C18 is connected to the first end of the resistor R58 and the first end of the resistor R59, the second end of the resistor R58 is connected to the input voltage VCC3.3V, and the second end of the resistor R59 is grounded. The second end of the capacitor C60 is connected to the first end of the resistor R60 and the first end of the resistor R61, the second end of the resistor R60 is connected to the input voltage VCC3.3V, and the second end of the resistor R61 is grounded. The second end of the capacitor C21 is connected to the first end of the resistor R63 and the first end of the resistor R64, the second end of the resistor R63 is connected to the input voltage VCC3.3V, and the second end of the resistor R64 is grounded. The second end of the capacitor C61 is connected to the first end of the resistor R66 and the first end of the resistor R67, the second end of the resistor R66 is connected to the input voltage VCC3.3V, and the second end of the resistor R67 is grounded. The second end of capacitor C38 is connected to the first end of resistor R68 and the first end of resistor R69, the second end of resistor R68 is connected to the input voltage VCC3.3V, and the second end of resistor R69 is grounded. The second end of capacitor C62 is connected to the first end of resistor R70 and the first end of resistor R72, the second end of resistor R70 is connected to the input voltage VCC3.3V, and the second end of resistor R72 is grounded. The second end of capacitor C44 is connected to the first end of resistor R73 and the first end of resistor R74, the second end of resistor R73 is connected to the input voltage VCC3.3V, and the second end of resistor R74 is grounded. The second end of capacitor C17 is connected to the first end of resistor R75 and the first end of resistor R76, the second end of resistor R75 is connected to the input voltage VCC3.3V, and the second end of resistor R76 is grounded.

3. The data processing circuit board for a TTE analyzer according to claim 1, characterized in that: The processor module comprises: A first end of capacitor C88, a first end of capacitor C89, a first end of capacitor C96, a first end of capacitor C98, a first end of capacitor C100, a first end of capacitor C102, a first end of capacitor C105, a first end of capacitor C108 and a first end of capacitor C111 are connected to input voltage VCC3.3V and voltage input pin VCC of processor IC1, and a second end of capacitor C88, a second end of capacitor C89, a second end of capacitor C96, a second end of capacitor C98, a second end of capacitor C100, a second end of capacitor C102, a second end of capacitor C105, a second end of capacitor C108 and a second end of capacitor C111 are grounded; A first end of capacitor C106, a first end of capacitor C109 and a first end of capacitor C112 are connected to input voltage VCC1.8V and voltage input pin VCCQ of processor IC1, and a second end of capacitor C106, a second end of capacitor C109 and a second end of capacitor C112 are grounded; A first end of the resistor R152 is connected to the input voltage VCC1.2V, a second end of the resistor R152 is connected to a first end of a capacitor C90, a first end of a capacitor C97, a first end of a capacitor C99, a first end of a capacitor C101, a first end of a capacitor C103, a first end of a capacitor C107, a first end of a capacitor C110, a first end of a capacitor C113, a voltage input pin VDDC of the processor IC1, and a voltage input pin VDD of the processor IC1, and a second end of the capacitor C90, a second end of the capacitor C97, a second end of the capacitor C99, a second end of the capacitor C101, a second end of the capacitor C103, a second end of the capacitor C107, a second end of the capacitor C110, and a second end of the capacitor C113 are grounded; The first SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C120, the first end of the capacitor C122, the first end of the capacitor C124 and the first end of the inductor L11, the second end of the capacitor C120, the second end of the capacitor C122 and the second end of the capacitor C124 are all grounded, and the second end of the inductor L11 is connected to the input voltage VCC1.2V; The second SATA power supply pin SATA_VDD of the processor IC1 is connected to the first end of the capacitor C121, the first end of the capacitor C123, the first end of the capacitor C125 and the first end of the inductor L12, the second end of the capacitor C121, the second end of the capacitor C123 and the second end of the capacitor C125 are all grounded, and the second end of the inductor L12 is connected to the input voltage VCC1.2V; The SATA voltage pin SATA_VSS of the processor IC1 is grounded, the sleep signal pin DEVSLP of the processor IC1 is connected to the first end of the resistor R155, the second end of the resistor R155 is grounded, the crystal oscillator output pin XTAL_OUT of the processor IC1 and the crystal oscillator input pin XTAL_IN of the processor IC1 are connected to the crystal oscillator input pin 1 of the crystal oscillator G1 and the crystal oscillator output pin 3 of the crystal oscillator G1, the power reset pin PWR_RESETN of the processor IC1 is connected to the first end of the resistor R158, the second end of the resistor R158 is connected to the external reset signal, and the power reset pin PWR_RESETN of the processor IC1 is connected to the external SATA power reset signal; The spare pin NC34 of the processor IC1 is connected to the LED indicator light, and the spare pin NC37 of the processor IC1 and the spare pin NC38 of the processor IC1 are connected to the SATA device for receiving and sending control commands and data of the SATA device; The processor module includes a crystal oscillator, wherein the crystal oscillator input pin 1 of the crystal oscillator G1 is connected to the first end of the capacitor C104, the first end of the resistor R153 and the crystal oscillator output pin XTAL_OUT of the processor IC1, the second end of the capacitor C104 is grounded, the crystal oscillator output pin 3 of the crystal oscillator G1 is connected to the first end of the resistor R154, the second end of the resistor R154 is connected to the first end of the capacitor C114, the second end of the resistor R153 and the crystal oscillator input pin STAL_IN of the processor IC1, the second end of the capacitor C114 is grounded, and the ground pin 2 of the crystal oscillator G1 and the ground pin 4 of the crystal oscillator G1 are grounded.

4. The data processing circuit board for a TTE analyzer according to claim 1, characterized in that: The power management module comprises: The voltage input pin VIN1_0 of the buck voltage regulator chip D4, the voltage input pin VIN1_1 of the buck voltage regulator chip D4, and the voltage input pin SVIN1 of the buck voltage regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C91, and the second end of the capacitor C91 is grounded. The voltage input pin VIN2_0 of the buck voltage regulator chip D4, the voltage input pin VIN2_1 of the buck voltage regulator chip D4, and the voltage input pin SVIN2 of the buck voltage regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C92, and the second end of the capacitor C92 is grounded. The voltage input pin VIN3_0 of the buck voltage regulator chip D4, the voltage input pin VIN3_1 of the buck voltage regulator chip D4, and the voltage input pin SVIN3 of the buck voltage regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C93, and the second end of the capacitor C93 is grounded, and the voltage input pin VIN4_0 of the buck voltage regulator chip D4, the voltage input pin VIN4_1 of the buck voltage regulator chip D4, and the voltage input pin SVIN4 of the buck voltage regulator chip D4 are connected to the input voltage VCC5V and the first end of the capacitor C94, and the second end of the capacitor C94 is grounded; The enable pin RUN1 of the buck regulator chip D4, the enable pin RUN2 of the buck regulator chip D4, the enable pin RUN3 of the buck regulator chip D4, and the enable pin RUN4 of the buck regulator chip D4 are connected to the PEX8648 switching module and the first end of the resistor R283, and the second end of the resistor R283 is connected to the input voltage VCC5V; The voltage output pin VOUT1_0 of the buck regulator chip D4, the voltage output pin VOUT1_1 of the buck regulator chip D4, and the voltage output pin VOUT1_2 of the buck regulator chip D4 are connected to the first end of the capacitor C283, the voltage output pin VOUT1_0 of the buck regulator chip D4, the voltage output pin VOUT1_1 of the buck regulator chip D4, and the voltage output pin VOUT1_2 of the buck regulator chip D4 output voltage PEX_2V5, and the second end of the capacitor C283 grounded, a feedback pin FB1 of the buck regulator chip D4 is connected to a first end of a resistor R284, a second end of the resistor R284 and a second end of the capacitor C280 are grounded, a second end of the capacitor C280 is connected to a voltage tracking and soft-start pin TRACK|SS1 of the buck regulator chip D4, a power good indication pin PGOOD1 of the buck regulator chip D4 is connected to a first end of a resistor R285, and a second end of the resistor R285 is connected to an internal power pin INTVCC1 of the buck regulator chip D4; The voltage output pin VOUT2_0 of the buck regulator chip D4, the voltage output pin VOUT2_1 of the buck regulator chip D4, the voltage output pin VOUT2_2 of the buck regulator chip D4, the voltage output pin VOUT3_0 of the buck regulator chip D4, the voltage output pin VOUT3_1 of the buck regulator chip D4, the voltage output pin VOUT3_2 of the buck regulator chip D4, the voltage output pin VOUT4_0 of the buck regulator chip D4, the voltage output pin VOUT4_1 of the buck regulator chip D4 and the voltage output pin VOUT4 of the buck regulator chip D4 T4_2 is connected to the first end of capacitor C282, the first end of capacitor C284, and the first end of capacitor C285, and the voltage output pin VOUT2_0 of the buck voltage regulator chip D4, the voltage output pin VOUT2_1 of the buck voltage regulator chip D4, the voltage output pin VOUT2_2 of the buck voltage regulator chip D4, the voltage output pin VOUT3_0 of the buck voltage regulator chip D4, the voltage output pin VOUT3_1 of the buck voltage regulator chip D4, the voltage output pin VOUT3_2 of the buck voltage regulator chip D4, the voltage output pin VOUT4_0 of the buck voltage regulator chip D4, and the voltage output pin VOUT4_1 of the buck voltage regulator chip D4. The voltage output pin VOUT4_1 of the buck regulator chip D4 and the voltage output pin VOUT4_2 of the step-down regulator chip D4 are connected to the output voltage PEX_1V0, the second end of the capacitor C282, the second end of the capacitor C284 and the second end of the capacitor C285 are grounded, the feedback pin FB2 of the buck regulator chip D4, the feedback pin FB3 of the buck regulator chip D4 and the feedback pin FB4 of the buck regulator chip D4 are connected to the first end of the resistor R287, the second end of the resistor R287 is grounded, the voltage tracking and soft start pin TRACK|SS2 of the buck regulator chip D4, the buck regulator The voltage tracking and soft-start pin TRACK|SS3 of the buck regulator chip D4 and the voltage tracking and soft-start pin TRACK|SS4 of the buck regulator chip D4 are connected to the first end of the capacitor C281, the second end of the capacitor C281 is grounded, the power good indication pin PGOOD2 of the buck regulator chip D4, the power good indication pin PGOOD3 of the buck regulator chip D4 and the power good indication pin PGOOD4 of the buck regulator chip D4 are connected to the first end of the resistor R286, and the second end of the resistor R286 is connected to the internal power pin INTVCC2 of the buck regulator chip D4; The internal power supply pin INTVCC1 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE1 of the buck voltage regulator chip D4, the internal power supply pin INTVCC2 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE2 of the buck voltage regulator chip D4, the internal power supply pin INTVCC3 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE3 of the buck voltage regulator chip D4, and the internal power supply pin INTVCC4 of the buck voltage regulator chip D4 is connected to the working mode configuration pin MODE4 of the buck voltage regulator chip D4; The ground pin SGND of the buck regulator chip D4, the ground pin GND_0 of the buck regulator chip D4, the ground pin GND_1 of the buck regulator chip D4, the ground pin GND_2 of the buck regulator chip D4, the ground pin GND_3 of the buck regulator chip D4, the ground pin GND_4 of the buck regulator chip D4, the ground pin GND_5 of the buck regulator chip D4, the ground pin GND_6 of the buck regulator chip D4, the ground pin GND_7 of the buck regulator chip D4, the ground pin GND_8 of the buck regulator chip D4, the ground pin GND_9 of the buck regulator chip D 4, the ground pin GND_11 of the buck voltage regulator chip D4, the ground pin GND_12 of the buck voltage regulator chip D4, the ground pin GND_13 of the buck voltage regulator chip D4, the ground pin GND_14 of the buck voltage regulator chip D4, the ground pin GND_15 of the buck voltage regulator chip D4, the ground pin GND_16 of the buck voltage regulator chip D4, the ground pin GND_17 of the buck voltage regulator chip D4, the ground pin GND_18 of the buck voltage regulator chip D4, the ground pin GND_19 of the buck voltage regulator chip D4 and the ground pin GND_20 of the buck voltage regulator chip D4 are all grounded.

5. The data processing circuit board for a TTE analyzer according to claim 1, characterized in that: The PEX8648 switching module includes: Switching chip U2; Multiple PCIE X4 interfaces; Indicator lamp for indicating the network transmission status; The PEX8648 switching module includes a switching chip U2, 4 PCIE X4 interfaces and a single PCIE X4 interface, wherein a first end of the 4 PCIE X4 interface is connected to the VPX connector, a second end of the 4 PCIE X4 interface is connected to the switching chip U2, a first end of the single PCIE X4 interface is connected to the switching chip, and a second end of the single PCIE X4 interface is connected to the processor module; The above-mentioned PEX8648 switching module includes a network transmission indication pin of a U2 switching chip connected to an LED lamp holder to indicate the network transmission status.

6. The data processing circuit board for a TTE analyzer according to claim 1, characterized in that: The Ethernet interface module comprises: Ethernet interface, network transmission indicator light, capacitor filter network; The network signal transmission pins 1 to 8 of the Ethernet interface ETH0 are used for data transmission of Gigabit Ethernet. The indicator pin 9 of the Ethernet interface ETH0 receives the network activity signal GBE0_ACT_N. When data is transmitted, the LED light is on. The indicator pin 9 of the Ethernet interface ETH0 is connected to the first end of the capacitor C6, and the second end of the capacitor C6 is grounded. The indicator pin 10 of the Ethernet interface ETH0 is connected to the first end of the resistor R9, and the second end of the resistor R9 is connected to the input voltage LED_2V5. The indicator light pin 11 of the Ethernet interface ETH0 receives the network connection signal LINK1000_N. When the link is successful, the LED lights up. The indicator light pin 11 of the Ethernet interface ETH0 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded. The indicator light pin 12 of the Ethernet interface ETH0 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the input voltage LED_2V5.

7. The data processing circuit board for a TTE analyzer according to claim 1, characterized in that: The first end of the VPX connector is connected to the PEX8648 switching module of the data processing circuit board through a 4-way PCIE X4 interface, the second end of the VPX connector is connected to four data acquisition circuit boards through four single-way PCIE X4 interfaces, and the power transmission end of the VPX connector is connected to the power board.

8. The data processing circuit board for a TTE analyzer according to claim 1, characterized in that: The clock distribution chip D1 is MC100LVE111FA.

9. The data processing circuit board for a TTE analyzer according to claim 1, characterized in that: The model of the buck regulator chip D4 of the power management module is LTM4644EY#PBF.

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