Display panel structure of electronic paper
By adopting a combined control technology of matrix pixel array and multi-logic unit in the electronic paper panel, the problem of low resolution of existing electronic paper panels is solved, and higher image resolution and image quality are achieved.
Patent Information
- Application Number
- CN202421052618.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-15
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2034-05-15
AI Technical Summary
The maximum resolution of existing electronic paper panel designs is low and cannot meet the user's requirements for image quality.
A pixel array consisting of a matrix arranged multiple pixel units is adopted, and efficient control and data writing of the pixel units are realized through the combination of a plurality of first logic units, CNC signal lines, gated signal lines and negative voltage signal lines.
By driving pixel units with twice the number of rows under the same number of gated signals, the resolution of the electronic paper display panel is significantly improved and the image quality requirements of users are met.
Smart Images
Figure CN222636839U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electronic paper display, in particular to a display panel structure of electronic paper. Background Art
[0002] The wave of paperless office has begun to become popular in all walks of life. With the development of electronic screen display technology, the advantages of ultra-low power consumption and low-frequency display of e-paper ink screens have been revealed. E-paper ink screens have been widely used, and "e-paper +" products such as electronic tags, e-paper educational tablets, and electronic bus stops have also emerged.
[0003] In electronic paper products, electronic paper panel design is particularly important. In conventional electronic paper panel design, each pixel is controlled by a gate line to turn on and off, and a signal line to write data. At this time, the maximum resolution of the electronic paper panel is the product of the number of gate channels and the number of signal channels. However, under technical limitations, the maximum resolution that conventional panel design can provide is still low and cannot meet users' requirements for image quality. Therefore, how to improve the resolution of electronic paper panels still needs to be solved. Utility Model Content
[0004] The utility model provides a display panel structure of electronic paper to solve the technical problem that the conventional panel design in the prior art has low resolution and cannot meet the image quality requirements of users.
[0005] The utility model provides an electronic paper display panel structure, comprising a pixel array composed of a plurality of pixel units arranged in a matrix, a plurality of first logic units, a plurality of digital control signal lines, a plurality of first gate signal lines, a plurality of second gate signal lines, a negative voltage signal line and a group of drive signal lines; wherein the first logic unit comprises a first logic output terminal and a second logic output terminal; the pixel unit comprises a data input terminal and a gate input terminal;
[0006] Each first logic unit is connected to the driving signal line for receiving a clock driving signal; each first logic unit is connected to the negative voltage signal line for receiving a constant negative voltage signal; each first logic unit is respectively connected to a first gating signal line for receiving a gating signal;
[0007] The data input terminals of the plurality of pixel units on each column of the pixel array are connected to a digital control signal line for receiving a digital control signal;
[0008] The multiple pixel units on every two rows of the pixel array are connected to a first logic unit through two second gating signal lines; wherein the gating input terminals of the multiple pixel units on the odd rows are connected to the first logic output terminals of the corresponding first logic units through the corresponding second gating signal lines, and the gating input terminals of the multiple pixel units on the even rows are connected to the second logic output terminals of the corresponding first logic units through the corresponding second gating signal lines.
[0009] The utility model provides an electronic paper display panel structure. Through the above connection, when it is necessary to control the display content of the electronic paper panel, data is written to the pixel units of the pixel array through the digital control signal line, and the first gate signal line, the first logic unit and the second gate signal line are combined to control the order of writing data to the pixel units of the pixel array. Specifically, a gate signal transmitted by a first gate signal line passes through a first logic unit, and the first logic unit is controlled by a driving signal line that transmits a clock driving signal and a negative voltage signal line that transmits a constant negative voltage signal to perform conversion. After the conversion, two rows of pixel units of the pixel array are controlled through two second gate signal lines, so that the effect of driving the pixel units with twice the number of gate signals under the condition of the same number of gate signals is achieved, thereby improving the resolution of the electronic paper display panel, thereby meeting the image quality requirements of users.
[0010] Preferably, the first logic unit includes a first triode, a second triode, a third triode and a fourth triode;
[0011] The first triode, the second triode, the third triode and the fourth triode are connected to the driving signal line;
[0012] The first transistor and the fourth transistor are connected to the first gate control signal line;
[0013] The first transistor and the second transistor are connected to the corresponding second gate control signal line through the first logic output terminal;
[0014] The second transistor and the third transistor are connected to the negative voltage signal line;
[0015] The third transistor and the fourth transistor are connected to the corresponding second gate control signal line through the second logic output terminal.
[0016] This preferred solution forms a first logic unit through a combination of four transistors, realizes the reception of the clock drive signal transmitted by the drive signal line, the constant negative voltage signal transmitted by the negative voltage signal line and the gating signal transmitted by the first gating signal line, and then converts and controls the drive of two rows of pixel units through the second gating signal line.
[0017] Preferably, the first transistor and the third transistor are N-MOS transistors, and the second transistor and the fourth transistor are P-MOS transistors;
[0018] The driving signal line includes a first driving signal line.
[0019] This preferred solution uses N-MOS tubes as the first and third transistors, P-MOS tubes as the second and fourth transistors, and one signal line as a driving signal line. It can achieve the control of the front and back writing of two rows of pixel units through the combination of four transistors under the control of a single clock driving signal, thereby meeting the circuit requirements.
[0020] Preferably, the gate of the first triode, the gate of the second triode, the gate of the third triode and the gate of the fourth triode are connected to the first driving signal line;
[0021] The drain of the first transistor and the source of the fourth transistor are connected to the first gate control signal line;
[0022] The source of the first transistor and the drain of the second transistor are connected to a corresponding second gating signal line through the first logic output terminal;
[0023] The source of the second transistor and the drain of the third transistor are connected to the negative voltage signal line;
[0024] The source of the third transistor and the drain of the fourth transistor are connected to a corresponding second gating signal line through the second logic output terminal.
[0025] This preferred solution forms a first logic unit through a combination of four transistors, which can receive a first gating signal and, under the control of a clock drive signal transmitted by a first drive signal line and a constant negative voltage signal transmitted by a negative voltage signal line, realizes conversion of the gating signal and controls the front and back writing of two rows of pixel units through a second gating signal line.
[0026] Preferably, the first triode, the second triode, the third triode and the fourth triode are N-MOS transistors;
[0027] The driving signal line includes a second driving signal line and a third driving signal line.
[0028] This preferred solution uses N-MOS transistors as the first transistor, the second transistor, the third transistor and the fourth transistor, and uses two signal lines as drive signal lines. It can achieve the control of the front and back writing of two rows of pixel units through the combination of four transistors under the control of two clock drive signals, thereby meeting the circuit requirements.
[0029] Preferably, the gate of the first triode and the gate of the third triode are connected to the second driving signal line; the gate of the second triode and the gate of the fourth triode are connected to the third driving signal line;
[0030] The drain of the first transistor and the drain of the fourth transistor are connected to the second gate control signal line;
[0031] The source of the first transistor and the source of the second transistor are connected to a corresponding second gating signal line through the first logic output terminal;
[0032] The drain of the second transistor and the drain of the third transistor are connected to the negative voltage signal line;
[0033] The source of the third transistor and the source of the fourth transistor are connected to a corresponding second gating signal line through the second logic output terminal.
[0034] The preferred solution forms a first logic unit through a combination of four transistors, which can receive a first gating signal and, under the control of two alternating clock drive signals transmitted by the second drive signal line and the third drive signal line and a constant negative voltage signal transmitted by the negative voltage signal line, realize the conversion of the gating signal and control the front and back writing of two rows of pixel units through the second gating signal line. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 : A schematic diagram of a panel structure of an embodiment of a display panel structure of an electronic paper provided by the utility model;
[0036] Figure 2 : A schematic diagram of the circuit structure of a first logic unit of an embodiment of a display panel structure of an electronic paper provided by the utility model;
[0037] Figure 3 : A schematic diagram of a panel structure of another embodiment of an electronic paper display panel structure provided by the utility model;
[0038] Figure 4 : A schematic diagram of the circuit structure of a first logic unit of another embodiment of an electronic paper display panel structure provided by the utility model;
[0039] Among them, the specific reference numerals are:
[0040] G1~G m : The first gate signal line;
[0041] GA1~GA 2m : The second gate signal line;
[0042] L1~L m : The first logical unit;
[0043] S1~S n : CNC signal line;
[0044] VGL: negative pressure signal line;
[0045] VC1: first drive signal line;
[0046] VC2: second driving signal line;
[0047] VC3: The third driving signal line. DETAILED DESCRIPTION
[0048] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0049] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, unless otherwise clearly and specifically defined, "multiple" and "several" mean two or more.
[0050] Embodiment 1
[0051] Please refer to Figure 1 , is a display panel structure of an electronic paper provided by the utility model, comprising a pixel array composed of a plurality of pixel units arranged in a matrix, a plurality of first logic units L1~L m , multiple CNC signal lines S1~S n , multiple first gate signal lines G1~G m , multiple second gate signal lines GA1~GA 2m , a negative voltage signal line VGL and a first driving signal line VC1; wherein the first logic unit includes a first logic output terminal and a second logic output terminal; the pixel unit includes a data input terminal and a gate input terminal;
[0052] Each first logic unit is connected to the first driving signal line for receiving a clock driving signal; each first logic unit is connected to the negative voltage signal line for receiving a constant negative voltage signal; each first logic unit is respectively connected to a first gating signal line for receiving a gating signal;
[0053] The data input terminals of the plurality of pixel units on each column of the pixel array are connected to a digital control signal line for receiving a digital control signal;
[0054] The multiple pixel units on every two rows of the pixel array are connected to a first logic unit through two second gating signal lines; wherein the gating input terminals of the multiple pixel units on the odd rows are connected to the first logic output terminals of the corresponding first logic units through the corresponding second gating signal lines, and the gating input terminals of the multiple pixel units on the even rows are connected to the second logic output terminals of the corresponding first logic units through the corresponding second gating signal lines.
[0055] Please refer to Figure 2 , is a schematic diagram of a circuit structure of a first logic unit provided in this embodiment, wherein the first logic unit includes a first triode 21, a second triode 22, a third triode 23 and a fourth triode 24;
[0056] The first transistor 21, the second transistor 22, the third transistor 23 and the fourth transistor 24 are connected to the first driving signal line VC1;
[0057] The first transistor and the fourth transistor are connected to the first gate control signal line;
[0058] The first transistor and the second transistor are connected to the corresponding second gate control signal line through the first logic output terminal;
[0059] The second transistor and the third transistor are connected to the negative voltage signal line VGL;
[0060] The third transistor and the fourth transistor are connected to the corresponding second gate control signal line through the second logic output terminal.
[0061] Continue to refer to Figure 2 In this embodiment, a first logic unit is formed by combining and connecting four transistors, which realizes the reception of the clock driving signal transmitted by the driving signal line, the constant negative voltage signal transmitted by the negative voltage signal line, and the gating signal transmitted by the first gating signal line, and then converts and controls the driving of two rows of pixel units through the second gating signal line.
[0062] Preferably, the first transistor and the third transistor are N-MOS transistors, and the second transistor and the fourth transistor are P-MOS transistors.
[0063] Continue to refer to Figure 2 In this embodiment, by using N-MOS tubes as the first and third transistors, using P-MOS tubes as the second and fourth transistors, and driving through the first drive signal line, it is possible to control the front and back writing of two rows of pixel units through a combination of four transistors under the control of a single clock drive signal, thereby meeting the circuit requirements.
[0064] Preferably, the gate of the first triode, the gate of the second triode, the gate of the third triode and the gate of the fourth triode are connected to the first driving signal line;
[0065] The drain of the first transistor and the source of the fourth transistor are connected to the first gate control signal line;
[0066] The source of the first transistor and the drain of the second transistor are connected to a corresponding second gating signal line through the first logic output terminal;
[0067] The source of the second transistor and the drain of the third transistor are connected to the negative voltage signal line;
[0068] The source of the third transistor and the drain of the fourth transistor are connected to a corresponding second gating signal line through the second logic output terminal.
[0069] Continue to refer to Figure 2 In this embodiment, a first logic unit is formed by a combination of four transistors, which can receive a first gating signal and, under the control of a clock drive signal transmitted by a first drive signal line and a constant negative voltage signal transmitted by a negative voltage signal line, realize the conversion of the gating signal and control the front and back writing of two rows of pixel units through a second gating signal line.
[0070] Specifically, the working principle of this embodiment is explained by taking G1 receiving a gate signal to drive corresponding two rows of pixel units as an example:
[0071] When the two rows of pixel units corresponding to G1 need to be written, the gate signal connected to G1 is initially set to a high potential, and G2~G m The gate control signal connected is set to low potential, and the signal connected to VGL is a constant low voltage signal;
[0072] First, the clock driving signal connected to VC1 is set to a high potential. At this time, the first transistor and the third transistor in L1 are turned on, the second transistor and the fourth transistor are turned off, the first logic output terminal outputs a high potential, and the second logic output terminal outputs a low potential. Then, the entire row of pixel units corresponding to GA1 is in an on state and can correspond to normal data writing, while the entire row of pixel units corresponding to GA2 is in a off state and cannot correspond to data writing;
[0073] Then the clock drive signal connected to VC1 is set to a low potential. At this time, the second and fourth transistors in L1 are turned on, the first and third transistors are turned off, the first logic output terminal outputs a low potential, and the second logic output terminal outputs a high potential. Then the entire row of pixel units corresponding to GA2 is in an on state and can correspond to normal data writing, while the entire row of pixel units corresponding to GA1 is in a closed state and cannot correspond to data writing. Thus, the effect of controlling two rows of pixel units by a single gating signal is achieved, and the resolution of the electronic paper display panel is improved.
[0074] In this embodiment, when it is necessary to control the display content of the electronic paper panel, data is written to the pixel units of the pixel array through the digital control signal line, and the first gating signal line, the first logic unit and the second gating signal line are combined to control the order in which the pixel units of the pixel array write data. Specifically, a gating signal transmitted by a first gating signal line passes through a first logic unit, and the first driving signal line that transmits a clock driving signal and the negative voltage signal line that transmits a constant negative voltage signal control the first logic unit for conversion. After the conversion, two rows of pixel units of the pixel array are controlled through two second gating signal lines, thereby achieving the effect of driving the number of pixel units twice the number of gating signals under the condition of the same number of gating signals, thereby improving the resolution of the electronic paper display panel, thereby meeting the image quality requirements of users.
[0075] Embodiment 2
[0076] Please refer to Figure 3 , is another electronic paper display panel structure provided by the utility model, comprising a pixel array composed of a plurality of pixel units arranged in a matrix, a plurality of first logic units L1~L m , multiple CNC signal lines S1~S n , multiple first gate signal lines G1~G m , multiple second gate signal lines GA1~GA 2m , a negative voltage signal line VGL and a group of drive signal lines; wherein the first logic unit includes a first logic output terminal and a second logic output terminal; the pixel unit includes a data input terminal and a gate input terminal; the drive signal line includes a second drive signal line VC2 and a third drive signal line VC3;
[0077] Each first logic unit is connected to the driving signal line for receiving a clock driving signal; each first logic unit is connected to the negative voltage signal line for receiving a constant negative voltage signal; each first logic unit is respectively connected to a first gating signal line for receiving a gating signal;
[0078] The data input terminals of the plurality of pixel units on each column of the pixel array are connected to a digital control signal line for receiving a digital control signal;
[0079] The multiple pixel units on every two rows of the pixel array are connected to a first logic unit through two second gating signal lines; wherein the gating input terminals of the multiple pixel units on the odd rows are connected to the first logic output terminals of the corresponding first logic units through the corresponding second gating signal lines, and the gating input terminals of the multiple pixel units on the even rows are connected to the second logic output terminals of the corresponding first logic units through the corresponding second gating signal lines.
[0080] Please refer to Figure 4 , is a schematic diagram of a circuit structure of a first logic unit provided in this embodiment, wherein the first logic unit includes a first triode 41, a second triode 42, a third triode 43 and a fourth triode 44;
[0081] The first triode 41, the second triode 42, the third triode 43 and the fourth triode 44 are connected to the driving signal line;
[0082] The first transistor and the fourth transistor are connected to the first gate control signal line;
[0083] The first transistor and the second transistor are connected to the corresponding second gate control signal line through the first logic output terminal;
[0084] The second transistor and the third transistor are connected to the negative voltage signal line VGL;
[0085] The third transistor and the fourth transistor are connected to the corresponding second gate control signal line through the second logic output terminal.
[0086] Continue to refer to Figure 4 In this embodiment, a first logic unit is formed by combining and connecting four transistors, which realizes the reception of the clock driving signal transmitted by the driving signal line, the constant negative voltage signal transmitted by the negative voltage signal line, and the gating signal transmitted by the first gating signal line, and then converts and controls the driving of two rows of pixel units through the second gating signal line.
[0087] Preferably, the first transistor, the second transistor, the third transistor and the fourth transistor are N-MOS transistors.
[0088] Continue to refer to Figure 4 In this embodiment, by using N-MOS transistors as the first transistor, the second transistor, the third transistor and the fourth transistor, and driving them through the second drive signal line and the third drive signal line, it is possible to control the front and back writing of two rows of pixel units through the combination of four transistors under the control of two clock drive signals, thereby meeting the circuit requirements.
[0089] Preferably, the gate of the first triode and the gate of the third triode are connected to the second driving signal line; the gate of the second triode and the gate of the fourth triode are connected to the third driving signal line;
[0090] The drain of the first transistor and the drain of the fourth transistor are connected to the second gate control signal line;
[0091] The source of the first transistor and the source of the second transistor are connected to a corresponding second gating signal line through the first logic output terminal;
[0092] The drain of the second transistor and the drain of the third transistor are connected to the negative voltage signal line;
[0093] The source of the third transistor and the source of the fourth transistor are connected to a corresponding second gating signal line through the second logic output terminal.
[0094] Continue to refer to Figure 4 In this embodiment, a first logic unit is formed by a combination of four transistors, which can receive a first gating signal and, under the control of two alternating clock drive signals transmitted by the second drive signal line and the third drive signal line and a constant negative voltage signal transmitted by the negative voltage signal line, realize the conversion of the gating signal and control the front and back writing of two rows of pixel units through the second gating signal line.
[0095] Specifically, the working principle of this embodiment is explained by taking G1 receiving a gate signal to drive corresponding two rows of pixel units as an example:
[0096] When the two rows of pixel units corresponding to G1 need to be written, the gate signal connected to G1 is initially set to a high potential, and G2~G m The gate control signal connected is set to low potential, and the signal connected to VGL is a constant low voltage signal;
[0097] First, the clock drive signal connected to VC2 is set to a low potential, and the clock drive signal connected to VC3 is set to a high potential. At this time, the first transistor and the third transistor in L1 are turned on, the second transistor and the third transistor are turned off, the first logic output terminal outputs a high potential, and the second logic output terminal outputs a low potential. Then, the entire row of pixel units corresponding to GA1 is in an on state, and data can be written normally, while the entire row of pixel units corresponding to GA2 is in a off state, and data cannot be written.
[0098] Then the clock drive signal connected to VC2 is set to a high potential, and the clock drive signal connected to VC3 is set to a low potential. At this time, the second and fourth transistors in L1 are turned on, the first and third transistors are turned off, the first logic output terminal outputs a low potential, and the second logic output terminal outputs a high potential. Then the entire row of pixel units corresponding to GA2 is in an on state, and can correspond to normal writing of data, while the entire row of pixel units corresponding to GA1 is in a closed state, and cannot correspond to writing of data. Thus, the effect of controlling two rows of pixel units by a single gating signal is achieved, and the resolution of the electronic paper display panel is improved.
[0099] In this embodiment, when it is necessary to control the display content of the electronic paper panel, data is written to the pixel units of the pixel array through the digital control signal line, and the first gating signal line, the first logic unit and the second gating signal line are combined to control the order in which the pixel units of the pixel array write data. Specifically, a gating signal transmitted by a first gating signal line passes through a first logic unit, and is converted by the second drive signal line and the third drive signal line that transmit the clock drive signal and the negative voltage signal line that transmits the constant negative voltage signal. After the conversion, two rows of pixel units of the pixel array are controlled by two second gating signal lines, thereby achieving the effect of driving the pixel units with twice the number of rows as the number of gating signals under the condition of the same number of gating signals, thereby improving the resolution of the electronic paper display panel, thereby meeting the image quality requirements of the user.
[0100] The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the utility model in detail. It should be understood that the above description is only a specific embodiment of the utility model and is not intended to limit the protection scope of the utility model. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model should be included in the protection scope of the utility model.
Claims
1. A display panel structure of an electronic paper, characterized in that: The invention comprises a pixel array composed of a plurality of pixel units arranged in a matrix, a plurality of first logic units, a plurality of digital control signal lines, a plurality of first gate signal lines, a plurality of second gate signal lines, a negative voltage signal line and a group of drive signal lines; wherein the first logic unit comprises a first logic output terminal and a second logic output terminal; the pixel unit comprises a data input terminal and a gate input terminal; Each first logic unit is connected to the driving signal line for receiving a clock driving signal; each first logic unit is connected to the negative voltage signal line for receiving a constant negative voltage signal; each first logic unit is respectively connected to a first gating signal line for receiving a gating signal; The data input terminals of the plurality of pixel units on each column of the pixel array are connected to a digital control signal line for receiving a digital control signal; The multiple pixel units on every two rows of the pixel array are connected to a first logic unit through two second gating signal lines; wherein the gating input terminals of the multiple pixel units on the odd rows are connected to the first logic output terminals of the corresponding first logic units through the corresponding second gating signal lines, and the gating input terminals of the multiple pixel units on the even rows are connected to the second logic output terminals of the corresponding first logic units through the corresponding second gating signal lines.
2. The display panel structure of electronic paper according to claim 1, characterized in that: The first logic unit includes a first triode, a second triode, a third triode and a fourth triode; The first triode, the second triode, the third triode and the fourth triode are connected to the driving signal line; The first transistor and the fourth transistor are connected to the first gate control signal line; The first transistor and the second transistor are connected to the corresponding second gate control signal line through the first logic output terminal; The second transistor and the third transistor are connected to the negative voltage signal line; The third transistor and the fourth transistor are connected to the corresponding second gate control signal line through the second logic output terminal.
3. The display panel structure of electronic paper according to claim 2, characterized in that: The first transistor and the third transistor are N-MOS transistors, and the second transistor and the fourth transistor are P-MOS transistors; The driving signal line includes a first driving signal line.
4. The electronic paper display panel structure according to claim 3, characterized in that: The gate of the first triode, the gate of the second triode, the gate of the third triode and the gate of the fourth triode are connected to the first driving signal line; The drain of the first transistor and the source of the fourth transistor are connected to the first gate control signal line; The source of the first transistor and the drain of the second transistor are connected to a corresponding second gating signal line through the first logic output terminal; The source of the second transistor and the drain of the third transistor are connected to the negative voltage signal line; The source of the third transistor and the drain of the fourth transistor are connected to a corresponding second gating signal line through the second logic output terminal.
5. The display panel structure of electronic paper according to claim 2, characterized in that: The first triode, the second triode, the third triode and the fourth triode are N-MOS tubes; The driving signal line includes a second driving signal line and a third driving signal line.
6. The electronic paper display panel structure according to claim 5, characterized in that: The gate of the first triode and the gate of the third triode are connected to the second driving signal line; the gate of the second triode and the gate of the fourth triode are connected to the third driving signal line; The drain of the first transistor and the drain of the fourth transistor are connected to the second gate control signal line; The source of the first transistor and the source of the second transistor are connected to a corresponding second gating signal line through the first logic output terminal; The drain of the second transistor and the drain of the third transistor are connected to the negative voltage signal line; The source of the third transistor and the source of the fourth transistor are connected to a corresponding second gating signal line through the second logic output terminal.