Substrate double-sided packaging system-level structure

Abstract

The utility model discloses a substrate double-sided packaging system-level structure, which relates to the technical field of semiconductor packaging and comprises a substrate, a component, a controller, an NAND chip and a DRAM (dynamic random access memory) chip, and the component, the controller, the NAND chip and the DRAM chip are respectively arranged on two sides of the substrate. The component is fixed on the substrate through solder paste, the controller is inversely arranged on the substrate, the NAND chip is bonded on the substrate through a DAF film, and the NAND chip is electrically connected with the substrate; the component, the controller and the NAND chip are packaged on the upper side of the substrate through epoxy resin; according to the scheme, a traditional bonding wire technology is changed into a flip-chip and bonding wire mixed technology, a flip-chip interconnection method is adopted, the circuit characteristics of more excellent high frequency, low delay and low crosstalk are achieved, the method is more suitable for high-frequency and high-speed modern electronic products, meanwhile, corresponding chip packaging is conducted on the two faces of the same substrate, and the product quality is improved. The combination of different connection modes of the chip and the substrate can better meet the requirements of high function and small size.

Description

Technical Field

[0001] The utility model relates to a system-level structure for double-sided packaging of a substrate, belonging to the technical field of semiconductor packaging. Background Art

[0002] In the existing system-level structure of single-sided packaging of substrates, different functional chips inside can only be arranged on one side. With fixed external dimensions, it is impossible to perform more integrated packaging and design, which makes the packaging layout space small. If the number of chips is to be increased, the overall packaging size and area will increase. Moreover, when packaging on the same side, different functional chips cannot use the substrate as an isolation layer, making them more susceptible to interference. Utility Model Content

[0003] The utility model aims to overcome the shortcomings of the prior art and provide a system-level structure of double-sided packaging of a substrate.

[0004] To achieve the above-mentioned purpose, the technical solution adopted by the utility model is: a system-level structure with double-sided packaging of a substrate, comprising a substrate, components, a controller, a NAND chip and a DRAM chip, wherein the components, the controller, the NAND chip and the DRAM chip are respectively arranged on both sides of the substrate; the components are fixed to the substrate by solder paste, the controller is flipped on the substrate, the NAND chip is bonded to the substrate by a DAF film, and the NAND chip and the substrate are electrically connected; the components, the controller and the NAND chip are all encapsulated on the upper side of the substrate by epoxy resin; the DRAM chip is bonded to the lower side of the substrate by bottom filling glue.

[0005] Preferably, the NAND chip is a stepped stacking structure, the NAND chip of the lower layer is bonded to the substrate through a DAF film, and is electrically connected to the substrate through a gold wire; the NAND chip of the upper layer is bonded to the NAND chip of the lower layer through a DAF film, and is electrically connected through a gold wire, and the upper surface of the NAND chip of the upper layer is directly in contact with the epoxy resin.

[0006] Preferably, the controller is flip-mounted on the upper surface of the substrate through a plurality of first bumps and is electrically connected to the substrate.

[0007] Preferably, the DRAM chip is flip-mounted on the lower surface of the substrate via a plurality of second bumps and is electrically connected to the substrate.

[0008] Preferably, a plurality of solder balls are further disposed on the lower surface of the substrate, and the plurality of solder balls are evenly distributed on both sides of the DRAM chip.

[0009] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:

[0010] 1. The system-level structure of this solution is to perform corresponding chip packaging on both sides of the same substrate. The combination of different connection methods between the chip and the substrate can better meet the needs of high functionality and small size.

[0011] 2. This solution transitions from traditional wire bonding technology to a hybrid process of flip-chip and wire bonding. The flip-chip interconnection method has more superior high-frequency, low-latency, and low-crosstalk circuit characteristics, and is more suitable for high-frequency, high-speed modern electronic products. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The technical solution of the utility model is further described below in conjunction with the accompanying drawings:

[0013] Attached Figure 1 The utility model is a schematic structural diagram of a system-level structure of a double-sided package of a substrate.

[0014] In the figure: 1. substrate; 2. components; 3. controller; 4. NAND chip; 5. solder paste; 6. DAF film; 7. epoxy resin; 8. underfill; 9. DRAM chip; 10. gold wire; 11. first bump; 12. second bump; 13. solder ball. DETAILED DESCRIPTION

[0015] The utility model is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0016] As attached Figure 1 As shown, a system-level structure of a substrate double-sided package described in the present invention includes a substrate 1, components 2, a controller 3, a NAND chip 4 and a DRAM chip 9.

[0017] Components 2, controller 3, NAND chip 4 and DRAM chip 9 are respectively arranged on both sides of substrate 1; component 2 is fixed on substrate 1 by solder paste 5, wherein component 2, controller 3 and NAND chip 4 are all encapsulated on the upper side of substrate 1 by epoxy resin 7; DRAM chip 9 is bonded to the lower side of substrate 1 by bottom filling glue 8, thereby realizing double-sided packaging of substrate 1, which not only promotes the integrated development of system-level packaging technology, but also meets the demand for miniaturization of the overall chip, and can achieve richer performance.

[0018] The controller 3 is flipped on the substrate 1. The upper surface of the substrate 1 has undergone a special substrate design. The controller 3 is flipped on the upper surface of the substrate 1 through a plurality of first bumps 11 and is electrically connected to the substrate 1. The lower surface of the substrate 1 has undergone the same special substrate design as the upper surface of the substrate 1. The DRAM chip 9 is flipped on the lower surface of the substrate 1 through a plurality of second bumps 12 and is electrically connected to the substrate 1.

[0019] The NAND chip 4 is bonded to the substrate 1 through the DAF film 6, and the NAND chip 4 and the substrate 1 are electrically connected, wherein the NAND chip 4 is a stepped stacking structure, the lower NAND chip 4 is bonded to the substrate 1 through the DAF film 6, and is electrically connected to the substrate 1 through the gold wire 10; the upper NAND chip 4 is bonded to the lower NAND chip 4 through the DAF film 6, and is electrically connected through the gold wire 10, and the upper surface of the upper NAND chip 4 is directly in contact with the epoxy resin 7 to improve the heat dissipation efficiency of the NAND chip 4.

[0020] A plurality of solder balls 13 are also disposed on the lower surface of the substrate 1 , and the plurality of solder balls 13 are evenly distributed on both sides of the DRAM chip 9 .

[0021] The processing process of the system-level structure of this scheme is as follows:

[0022] Step 1: Substrate selection and component placement:

[0023] Apply solder paste to the corresponding position on the upper surface of the substrate and mount the components.

[0024] Step 2: Paste the controller:

[0025] The controller is tightly combined with the substrate through a flip-chip process to achieve electrical conduction with the substrate.

[0026] Step 3: Mount the flash memory chip:

[0027] The flash memory chip is mounted on the same side of the substrate and connected to the substrate through a wire bonding process to achieve conduction.

[0028] Step 4: Plastic sealing of substrate surface:

[0029] Use special plastic sealing material to fill the bottom of the controller at one time and simultaneously seal the entire surface.

[0030] Step 5: Flip the substrate and mount the memory chip:

[0031] Use the corresponding fixture to flip the substrate to the other side, combine the memory with the substrate through the flip-chip process, and then fill it with bottom filling glue, using capillary phenomenon to protect the bump.

[0032] Step 6: Planting the ball:

[0033] Select appropriate solder balls and carry out ball planting.

[0034] Step 7: Cutting:

[0035] Use a cutting knife to cut the Strip into individual particles.

[0036] The system-level structure of this solution is to perform corresponding chip packaging on both sides of the same substrate. The combination of different connection methods between the chip and the substrate can better meet the needs of high functionality and small size.

[0037] This solution transitions from traditional wire bonding technology to a hybrid process of flip-chip and wire bonding. The flip-chip interconnection method has more superior high-frequency, low-latency, and low-crosstalk circuit characteristics, and is more suitable for high-frequency, high-speed modern electronic products.

[0038] The above are only specific application examples of the utility model and do not constitute any limitation to the protection scope of the utility model; any technical solutions formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the utility model.

Claims

1. A system-level structure for double-sided packaging of a substrate (1), characterized in that: The invention comprises a substrate (1), components (2), a controller (3), a NAND chip (4) and a DRAM chip (9), wherein the components (2), the controller (3), the NAND chip (4) and the DRAM chip (9) are respectively arranged on both sides of the substrate (1); the components (2) are fixed on the substrate (1) by means of solder paste (5), the controller (3) is flip-chip mounted on the substrate (1), the NAND chip (4) is bonded to the substrate (1) by means of a DAF film (6), and the NAND chip (4) and the substrate (1) are electrically connected; the components (2), the controller (3) and the NAND chip (4) are all encapsulated on the upper side of the substrate (1) by means of epoxy resin (7); and the DRAM chip (9) is bonded to the lower side of the substrate (1) by means of an underfill (8).

2. A system-level structure for double-sided packaging of a substrate (1) according to claim 1, characterized in that: The NAND chips (4) are in a stepped stacking structure, wherein the NAND chips (4) of the lower layer are bonded to the substrate (1) via a DAF film (6) and are electrically connected to the substrate (1) via a gold wire (10); the NAND chips (4) of the upper layer are bonded to the NAND chips (4) of the lower layer via a DAF film (6) and are electrically connected via a gold wire (10), and the upper surface of the NAND chips (4) of the upper layer is in direct contact with the epoxy resin (7).

3. A system-level structure for double-sided packaging of a substrate (1) according to claim 1, characterized in that: The controller (3) is flip-mounted on the upper surface of the substrate (1) via a plurality of first bumps (11) and is electrically connected to the substrate (1).

4. A system-level structure for double-sided packaging of a substrate (1) according to claim 1, characterized in that: The DRAM chip (9) is flip-mounted on the lower surface of the substrate (1) via a plurality of second bumps (12) and is electrically connected to the substrate (1).

5. The system-level structure of double-sided packaging of a substrate (1) according to claim 1, characterized in that: A plurality of solder balls (13) are also provided on the lower surface of the substrate (1), and the plurality of solder balls (13) are evenly distributed on both sides of the DRAM chip (9).

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