Delay power-on control circuit based on in-situ detection

Abstract

The utility model relates to a time-delay power-on control circuit based on in-situ detection. The time-delay power-on control circuit comprises a connector part and a control circuit part, the connector part comprises a socket J1 and a plug J2, pins at the two ends of the J1 are respectively provided with an in-place signal PRESENT1 # and a PRESENT2 #, the in-place signals PRESENT1 # and PRESENT2 # are respectively pulled up to a power supply + V3P3A through resistors, and pins at the two ends, corresponding to the J1, of the J2 are connected with GND; when the J1 and the J2 are embedded, an in-place signal is pulled down to GND and is connected to the control circuit part at the same time; when the J1 and the J2 are not connected or are not connected in place, the PWREN is pulled down to the GND, and the power supply enabling is invalid; when the J1 and the J2 are connected in place, the PWREN outputs a high level, and the power supply enables to take effect. The circuit can realize time-delay power-on based on in-situ detection, so that the safety of hot plugging of the connector is improved, and the circuit is simple in structure, practical and low in implementation cost.

Description

Technical Field

[0001] The utility model relates to a delayed power-on control circuit based on in-situ detection. Background Art

[0002] There are many connectors on the hardware circuit motherboard, some of which are relatively fixed and do not need to support hot plugging; while some have the need for hot plugging. For hot plug connectors, if they are not electrically processed, they may cause damage to the motherboard or external devices. In the prior art, most of the hot plugging problems are solved by delaying power-on. The prior art solutions basically adopt a dedicated control chip to realize delayed power-on, which has a complex structure and high implementation cost. For example, patent CN209402490U discloses a delayed power-on circuit, including a power chip U1, a transistor Q1, a capacitor C1, and a capacitor C2. One end of the capacitor C1 and the input pin of the power chip U1 are both connected to the power input, and the conversion pin of the power chip U1 is used as the output end of the delayed power-on circuit. The other end of the capacitor C1 is connected to the base of the transistor Q1, and the collector of the transistor Q1 and one end of the capacitor C2 are both connected to the enable end of the power chip U1. The collector of the transistor Q1, the other end of the capacitor C2 and the ground end of the power chip U1 are all grounded. However, the delayed power-on circuit requires a dedicated power chip and cannot detect the mating state of the connector. Summary of the invention

[0003] The utility model aims to provide a delayed power-on control circuit based on in-place detection, which can realize delayed power-on based on in-place detection, thereby improving the safety of hot plugging of connectors, and has a simple and practical structure and low implementation cost.

[0004] In order to achieve the above-mentioned purpose, the technical solution adopted by the utility model is: a delayed power-on control circuit based on in-position detection, including a connector part and a control circuit part; the connector part includes a socket J1 and a plug J2, and the pins at both ends of the socket J1 each have a in-position signal PRESENT1# and PRESENT2#, and the in-position signal is pulled up to the ALWAYS power supply +V3P3A through resistors R5 and R6, and the pins at both ends of the plug J2 and the socket J1 are connected to GND; when the socket J1 and the plug J2 are engaged, the in-position signals PRESENT1# and PRESENT2# are pulled down to GND and connected to the control circuit part at the same time; the control circuit part includes an N-channel MOS tube Q1, an N-channel MOS tube Q2, an N-channel MOS tube Q3, an N-channel MOS tube Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a capacitor C1; the G pole of the N-channel MOS tube Q1 is connected to the in-position signal PRESENT1# and the G pole of the N-channel MOS tube Q1 is connected to the G pole of the N-channel MOS tube Q1. #, the S pole is connected to GND, and the D pole is connected to the D pole of the N-channel MOS tube Q4 and the pin 1 of the resistor R4 at the same time; the G pole of the N-channel MOS tube Q4 is connected to the in-position signal PRESENT2#, and the S pole is connected to GND; the pin 2 of the resistor R4 is simultaneously connected to the G pole of the N-channel MOS tube Q3, the pin 1 of the capacitor C1 and the pin 2 of the resistor R2; the pin 2 of the capacitor C1 is connected to GND; the pin 1 of the resistor R2 is connected to the ALWAYS power supply + V3P3A; the D pole of the N-channel MOS tube Q3 is simultaneously connected to the G pole of the N-channel MOS tube Q2 and the pin 2 of the resistor R3, and the S pole is connected to GND; the pin 1 of the resistor R3 is connected to the ALWAYS power supply +V3P3A; the pin 1 of the resistor R1 is connected to the ALWAYS power supply +V3P3A, and the pin 2 is connected to the D pole of the N-channel MOS tube Q2; the S pole of the N-channel MOS tube Q2 is connected to GND, and the D pole outputs the power enable signal PWREN.

[0005] Further, when the socket J1 and the plug J2 are not connected or not connected in place, at least one of the presence signals PRESENT1# and PRESENT2# is at a high level, and at least one of the N-channel MOS transistor Q1 and the N-channel MOS transistor Q4 is in an on state; the pin 1 of the resistor R4 is pulled low, the pin 1 of the capacitor C1 is quickly discharged to GND through the resistor R4, the G-pole level of the N-channel MOS transistor Q3 is equal to the voltage divided by +V3P3A through the resistor R2 and the resistor R4, and the N-channel MOS transistor Q3 is in an off state; the G-pole of the N-channel MOS transistor Q2 is pulled up to +V3P3A, the N-channel MOS transistor Q2 is turned on, PWREN is pulled down to GND, and the power enable is invalid.

[0006] Further, when the socket J1 and the plug J2 are connected in place, the presence signals PRESENT1# and PRESENT2# are both pulled down to a low level, the N-channel MOS transistors Q1 and Q4 are both in the off state, and +V3P3A slowly charges the capacitor C1 through the resistor R2; when the voltage on the pin 1 of the capacitor C1 reaches the turn-on voltage of the N-channel MOS transistor Q3, the N-channel MOS transistor Q3 is turned on, the G pole of the N-channel MOS transistor Q2 is pulled low, the N-channel MOS transistor Q2 is turned off, the D pole of the N-channel MOS transistor Q2 is pulled up to +V3P3A, PWREN outputs a high level, and the power enable takes effect.

[0007] Compared with the prior art, the utility model has the following beneficial effects: the utility model provides a delayed power-on control circuit based on in-situ detection, which can detect the mating state of the connector and control the delayed power-on on this basis, which can effectively solve the problem of reliability of connector-related circuits, thereby improving the safety of connector hot plugging; the circuit is simple and practical, low in implementation cost, and has strong practicality and broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a circuit diagram of the connector part of an embodiment of the utility model;

[0009] Figure 2 It is a circuit diagram of the control circuit part of the embodiment of the utility model. DETAILED DESCRIPTION

[0010] The utility model is further described below in conjunction with the accompanying drawings and embodiments.

[0011] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0012] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0013] like Figure 1-2 As shown, this embodiment provides a delayed power-on control circuit based on presence detection, including a connector part and a control circuit part.

[0014] like Figure 1As shown, the connector part includes a socket J1 and a plug J2. The pins at both ends of the socket J1 each have a presence signal PRESENT1# and PRESENT2#. The presence signal is pulled up to the ALWAYS power supply +V3P3A through resistors R5 and R6 by default. The pins at both ends of the plug J2 and the socket J1 are connected to GND.

[0015] When the socket J1 and the plug J2 are mated with each other, the presence signals PRESENT1# and PRESENT2# are pulled down to GND, and the presence signals PRESENT1# and PRESENT2# are connected to the control circuit part.

[0016] like Figure 2 The control circuit part includes an N-channel MOS transistor Q1, an N-channel MOS transistor Q2, an N-channel MOS transistor Q3, an N-channel MOS transistor Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a capacitor C1.

[0017] The G pole (pin 1) of the N-channel MOS tube Q1 is connected to the in-position signal PRESENT1#, the S pole (pin 2) is connected to GND, and the D pole (pin 3) is simultaneously connected to the D pole (pin 3) of the N-channel MOS tube Q4 and the pin 1 of the resistor R4; the G pole (pin 1) of the N-channel MOS tube Q4 is connected to the in-position signal PRESENT2#, and the S pole (pin 2) is connected to GND; the pin 2 of the resistor R4 is simultaneously connected to the G pole (pin 1) of the N-channel MOS tube Q3, the pin 1 of the capacitor C1 and the pin 2 of the resistor R2; the pin 2 of the capacitor C1 is connected to GND; the resistor R Pin 1 of the resistor R2 is connected to the ALWAYS power supply +V3P3A; the D pole (pin 3) of the N-channel MOS tube Q3 is simultaneously connected to the G pole (pin 1) of the N-channel MOS tube Q2 and the pin 2 of the resistor R3, and the S pole (pin 2) is connected to GND; the pin 1 of the resistor R3 is connected to the ALWAYS power supply +V3P3A; the pin 1 of the resistor R1 is connected to the ALWAYS power supply +V3P3A, and the pin 2 is connected to the D pole (pin 3) of the N-channel MOS tube Q2; the S pole (pin 2) of the N-channel MOS tube Q2 is connected to GND, and the D pole (pin 3) outputs the power enable signal PWREN.

[0018] exist Figure 1 In the embodiment, when the connectors J1 and J2 are not engaged, the presence signals PRESENT1# and PRESENT2# are in a pull-up state (high level); when the connectors J1 and J2 are engaged, the presence signals PRESENT1# and PRESENT2# are pulled down to GND (low level) by the J2 end.

[0019] exist Figure 2In the example, the in-position signal PRESENT1# is connected to pin 1 of Q1, and PRESENT2# is connected to pin 1 of Q2. Pin 2 of Q1 and Q4 are both grounded, and pin 3 are connected together and connected to pin 1 of R4. Pin 2 of R4 is connected to pin 1 of C1, pin 2 of R2, and pin 1 of Q3. Pin 1 of R2 is connected to +V3P3A, pin 2 of C1 is grounded, and pin 2 of Q3 is grounded. Pin 3 of Q3 is connected to pin 2 of R3 and pin 1 of Q2. Pin 1 of R3 is connected to +V3P3A, and pin 2 of Q2 is grounded. Pin 3 of Q2 is connected to pin 2 of R1, and the power enable signal PWREN is brought out. Pin 1 of R1 is connected to +V3P3A.

[0020] When the socket J1 and the plug J2 are not connected or not connected in place, at least one of the in-place signals PRESENT1# and PRESENT2# is high level, and at least one of the N-channel MOS transistors Q1 and Q4 is in the on state. At this time, the pin 1 of the resistor R4 is pulled low, the pin 1 of the capacitor C1 is quickly discharged to GND through the resistor R4, the G pole (pin 1) level of the N-channel MOS transistor Q3 is equal to the voltage divided by +V3P3A through the resistor R2 and the resistor R4, which is only about 0.7mV, and the N-channel MOS transistor Q3 is in the off state; the G pole (pin 1) of the N-channel MOS transistor Q2 is pulled up to +V3P3A, the N-channel MOS transistor Q2 is turned on, PWREN is pulled down to GND, and the power enable is invalid.

[0021] When the socket J1 and the plug J2 are connected in place, the presence signals PRESENT1# and PRESENT2# are both pulled down to a low level, the N-channel MOS transistors Q1 and Q4 are both in the off state, and +V3P3A slowly charges the capacitor C1 through the resistor R2; when the voltage on pin 1 of the capacitor C1 reaches the turn-on voltage of the N-channel MOS transistor Q3, the N-channel MOS transistor Q3 is turned on, the G pole (pin 1) of the N-channel MOS transistor Q2 is pulled low, the N-channel MOS transistor Q2 is turned off, the D pole (pin 3) of the N-channel MOS transistor Q2 is pulled up to +V3P3A, PWREN outputs a high level, and the power enable takes effect.

[0022] The above is only the preferred embodiment of the utility model, and does not limit the utility model in other forms. Any technician familiar with the profession may use the technical content disclosed above to change or modify it into an equivalent embodiment with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the utility model without departing from the technical solution of the utility model still belongs to the protection scope of the technical solution of the utility model.

Claims

1. A delayed power-on control circuit based on in-position detection, characterized in that: The invention comprises a connector part and a control circuit part; the connector part comprises a socket J1 and a plug J2, the pins at both ends of the socket J1 respectively have a presence signal PRESENT1# and PRESENT2#, the presence signal is pulled up to the ALWAYS power supply +V3P3A through resistors R5 and R6, and the pins at both ends of the plug J2 and the socket J1 are connected to GND; when the socket J1 and the plug J2 are engaged, the presence signals PRESENT1# and PRESENT2# are pulled down to GND and connected to the control circuit part at the same time; the control circuit part comprises an N-channel MOS transistor Q1, an N-channel MOS transistor Q2, an N-channel MOS transistor Q3, an N-channel MOS transistor Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a capacitor C1; the G pole of the N-channel MOS transistor Q1 is connected to the presence signal PRESENT1#, the S pole is connected to GND, and the D pole is simultaneously connected to the N-channel MOS transistor Q4. The D pole of the OS transistor Q4 and the pin 1 of the resistor R4; the G pole of the N-channel MOS transistor Q4 is connected to the in-position signal PRESENT2#, and the S pole is connected to GND; the pin 2 of the resistor R4 is simultaneously connected to the G pole of the N-channel MOS transistor Q3, the pin 1 of the capacitor C1 and the pin 2 of the resistor R2; the pin 2 of the capacitor C1 is connected to GND; the pin 1 of the resistor R2 is connected to the ALWAYS power supply +V3P3A; the D pole of the N-channel MOS transistor Q3 is simultaneously connected to the G pole of the N-channel MOS transistor Q2 and the pin 2 of the resistor R3, and the S pole is connected to GND; the pin 1 of the resistor R3 is connected to the ALWAYS power supply +V3P3A; the pin 1 of the resistor R1 is connected to the ALWAYS power supply +V3P3A, and the pin 2 is connected to the D pole of the N-channel MOS transistor Q2; the S pole of the N-channel MOS transistor Q2 is connected to GND, and the D pole outputs the power enable signal PWREN.

2. A delayed power-on control circuit based on in-position detection according to claim 1, characterized in that: When the socket J1 and the plug J2 are not connected or not connected in place, at least one of the presence signals PRESENT1# and PRESENT2# is at a high level, and at least one of the N-channel MOS transistor Q1 and the N-channel MOS transistor Q4 is in an on state; the pin 1 of the resistor R4 is pulled low, the pin 1 of the capacitor C1 is quickly discharged to GND through the resistor R4, the G-pole level of the N-channel MOS transistor Q3 is equal to the voltage divided by +V3P3A through the resistor R2 and the resistor R4, and the N-channel MOS transistor Q3 is in an off state; the G-pole of the N-channel MOS transistor Q2 is pulled up to +V3P3A, the N-channel MOS transistor Q2 is turned on, PWREN is pulled down to GND, and the power enable is invalid.

3. The delayed power-on control circuit based on in-position detection according to claim 1, characterized in that: When the socket J1 and the plug J2 are connected in place, the presence signals PRESENT1# and PRESENT2# are both pulled down to a low level, the N-channel MOS transistors Q1 and Q4 are both in the off state, and +V3P3A slowly charges the capacitor C1 through the resistor R2; when the voltage on the pin 1 of the capacitor C1 reaches the turn-on voltage of the N-channel MOS transistor Q3, the N-channel MOS transistor Q3 is turned on, the G pole of the N-channel MOS transistor Q2 is pulled low, the N-channel MOS transistor Q2 is turned off, the D pole of the N-channel MOS transistor Q2 is pulled up to +V3P3A, PWREN outputs a high level, and the power enable takes effect.

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