Semiconductor device

Abstract

The utility model discloses a semiconductor device which comprises a substrate, a plurality of storage node pads and a capacitor structure. The substrate comprises a peripheral area, and the storage node bonding pads are arranged on the substrate in a mutually separated mode to form an array. The capacitor structure is located on the substrate and comprises a plurality of capacitors arranged in an array, and at least two capacitors are in physical contact in the direction parallel to the substrate. Therefore, the dummy capacitors are arranged around the storage array, so that the structure defect of the semiconductor device possibly derived due to continuous increase of the density of the storage unit can be improved, and the relatively optimized device efficiency can be achieved.

Description

Technical Field

[0001] The utility model relates to a semiconductor device, in particular to a semiconductor device comprising a capacitor structure. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the density of memory cells in the array area must be continuously improved, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technology or structure needs to be further improved to effectively improve the performance and reliability of related memory devices. Utility Model Content

[0003] One purpose of the utility model is to provide a semiconductor device, which sets dummy capacitors around the memory array to improve the structural defects of the semiconductor device that may be derived from the continuous increase in the density of memory cells. In this way, the semiconductor device can have a more stable and reliable structure and achieve relatively optimized device performance.

[0004] To achieve the above object, an embodiment of the present invention provides a semiconductor device, comprising a substrate and a capacitor structure. The capacitor structure is located on the substrate and comprises a plurality of capacitors arranged in an array, wherein at least two capacitors are in physical contact in a direction parallel to the substrate.

[0005] In order to achieve the above-mentioned object, an embodiment of the utility model provides a semiconductor device, comprising a substrate, a capacitor structure and a support structure. The capacitor structure is arranged on the substrate. The capacitor comprises at least one first capacitor and at least one second capacitor, the bottom surface of the at least one first capacitor is lower than the bottom surface of the at least one second capacitor, and at least one of the at least one first capacitor and the at least one second capacitor has a bent end. The support structure is arranged on the substrate and between the capacitors, and the support structure comprises a first support layer and a second support layer arranged in sequence from bottom to top.

[0006] In general, according to the semiconductor device of the present invention, a bottom electrode layer, a capacitor dielectric layer, and / or a virtual capacitor with physical contact between the top electrode layer and the top electrode layer are arranged around the memory array, thereby improving the structural defects of the semiconductor device that may be derived from the continuous increase in the density of memory cells. In this way, the semiconductor device can have a more stable and reliable structure and achieve relatively optimized device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings provide a deeper understanding of this embodiment and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0008] Figure 1 to Figure 2 FIG. 1 is a schematic diagram of a semiconductor device according to a first embodiment of the present invention, wherein:

[0009] Figure 1 is a schematic top view of a semiconductor device;

[0010] Figure 2 is a cross-sectional schematic diagram of a semiconductor device;

[0011] Figure 3 to Figure 4 The diagram depicts a semiconductor device in a second embodiment of the present invention, wherein:

[0012] Figure 3 is a schematic top view of a semiconductor device;

[0013] Figure 4 is a cross-sectional schematic diagram of a semiconductor device;

[0014] Figure 5 Illustrated is a cross-sectional schematic diagram of a semiconductor device in a third embodiment of the present utility model;

[0015] Figure 6Illustrated is a cross-sectional schematic diagram of a semiconductor device in a fourth embodiment of the present utility model;

[0016] Figure 7 Illustrated is a cross-sectional schematic diagram of a semiconductor device in a fifth embodiment of the present utility model;

[0017] Figure 8 FIG. 1 is a cross-sectional schematic diagram of a semiconductor device in a sixth embodiment of the present invention.

[0018] The reference numerals are described as follows:

[0019] 10, 20, 30, 40, 50, 60 semiconductor devices

[0020] 100 Substrate

[0021] 102 Surrounding Area

[0022] 104 Storage Area

[0023] 112 Shallow Trench Isolation

[0024] 114 Active Area

[0025] 120 buried gate

[0026] 122 Dielectric layer

[0027] 124 Gate dielectric layer

[0028] 126 Gate

[0029] 128 Covering layer

[0030] 130 Plug

[0031] 132 Storage Node Plug

[0032] 134 Storage node pad

[0033] 136 Insulation structure

[0034] 138 Insulation layer

[0035] 140, 2 40 Capacitor

[0036] 142, 144, 146, 242, 244, 246 capacitors

[0037] 144, 144a, 144b, 144c Capacitors

[0038] 150, 250, 350, 450, 550, 650 capacitor structure

[0039] 152, 152a, 152b bottom electrode layer

[0040] 154, 254, 354, 454, 554, 654 capacitor dielectric layer

[0041] 156, 256 Top electrode layer

[0042] 160 Support layer structure

[0043] 162 First support layer

[0044] 164 Second support layer

[0045] 244, 244a, 244b, 244c Capacitors

[0046] 252, 252a, 252b, 252c bottom electrode layer

[0047] 344, 344a, 344b Capacitors

[0048] 352, 352a, 352b bottom electrode layer

[0049] 444, 444a Capacitor

[0050] 452, 452a bottom electrode layer

[0051] 544, 544a, 544b capacitors

[0052] 552, 552a, 552b bottom electrode layer

[0053] 642, 644, 644a, 644b capacitors

[0054] 652, 652a, 652b, 652c bottom electrode layer

[0055] D1 Horizontal direction

[0056] D2 vertical direction

[0057] D3 vertical direction

[0058] h1, h2, h3 height

[0059] W1, W2 Width DETAILED DESCRIPTION

[0060] In order to enable those skilled in the art to further understand the present invention, the following lists the preferred embodiments of the present invention, and with the accompanying drawings, describes in detail the composition and intended effects of the present invention. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention.

[0061] Please refer to Figure 1 to Figure 2 , which is a schematic diagram of a semiconductor device 10 in the first embodiment of the utility model, wherein: Figure 1 and Figure 2 1 and 2 are schematic top view and cross-sectional view of the semiconductor device 10, respectively. Figure 1 As shown in the top view of the semiconductor device 10, the semiconductor device 10 includes a substrate 100 and a capacitor structure 150 located on the substrate 100. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate (such as SiC, SiGe, etc.) or a silicon-on-insulator (SOI) substrate, etc. The substrate 100 includes a region with a relatively high component density, such as a storage region (cell region) 104 and another region with a relatively low component density, such as a peripheral region (periphery region) 102. The storage region 104 and the peripheral region 102 are, for example, arranged adjacent to each other. Preferably, the peripheral region 102 can surround the outside of the storage region 104 and can be freely Figure 1 As shown, but not limited to.

[0062] The capacitor structure 150 is disposed on the substrate 100, and includes a plurality of capacitors 140 arranged in a staggered manner in a horizontal direction D1 parallel to the substrate 100, wherein the capacitors 140 are arranged in an array along the horizontal direction D1 and the vertical direction D2, for example. The capacitors 142 located in the storage area 104 are separated from each other by a support structure 160 disposed therebetween, so that each capacitor 142 located in the storage area 104 can be connected to the storage area 104 by means of a plug ( Figure 1 The peripheral area 100 (not shown) is electrically connected to the transistor components (not shown) in the substrate 100 to form a storage array. It should be noted that at least two capacitors 144 and 146 arranged in the peripheral area 102 are in physical contact with each other in the horizontal direction D1 to form a dummy capacitor. In this way, by arranging dummy capacitors that are in physical contact with each other around the storage array, the component density difference between the storage area 104 and the peripheral area 102 can be balanced during the process of manufacturing the semiconductor device 10, thereby improving the structural defects of the semiconductor device 10 of this embodiment that may be derived from the continuous increase in the setting density of the storage array. Under this setting, the semiconductor device 10 is able to have a more stable and reliable structure and achieve relatively optimized device performance.

[0063] In detail, Figure 1As shown, the capacitor structure 150 includes a bottom electrode layer 152, a capacitor dielectric layer 154, and a top electrode layer 156 arranged in the horizontal direction D1, wherein the capacitor dielectric layer 154 is arranged on one side of the bottom electrode layer 152, and the top electrode layer 156 is further arranged on one side of the capacitor dielectric layer 154, to form each capacitor 140. In this embodiment, the bottom electrode layer 152 includes, for example, a bottom electrode with a U-shaped cross section (please refer to Figure 2 ), and the top electrode layer 156 fills the gap between the bottom electrode layers 156. In one embodiment, the top electrode layer 156 may selectively include a single layer or a multi-layer structure, and the multi-layer structure is, for example, respectively disposed on the inner side and the outer side of the bottom electrode layer 152, as shown in FIG. Figure 1 As shown, but not limited to this. Thus, each capacitor 140 presents a cylindrical cross-sectional structure as a whole, but not limited to this. In one embodiment, two capacitors 144 located in the peripheral area 102 and physically contacting each other, for example, have their bottom electrode layers 152, their capacitor dielectric layers 154, and their top electrode layers 156 physically contact each other to form a virtual capacitor, such as Figure 1 As shown, but not limited thereto. Alternatively, at least one capacitor 146 located in the peripheral region 102 has a relatively small width W1 in the horizontal direction D1, for example, so as to contact the adjacent capacitor 144. In this way, the top electrode layers 156 of two or more capacitors 144 and 146 located in the peripheral region 102 and physically contacting each other are physically contacted with each other, or the top electrode layers 156 and the capacitor dielectric layers 154 are physically contacted with each other, so as to form a virtual capacitor.

[0064] On the other hand, Figure 2As shown in the cross-sectional schematic diagram of , the semiconductor device 10 includes a substrate 100, a capacitor structure 150, and a support structure 160 disposed on the substrate 100 and located between each capacitor 140. The support structure 160 includes a first support layer 162 and a second support layer 164 disposed in sequence from bottom to top, respectively supporting the middle section and the top of each capacitor 140, but not limited thereto. It should be noted that the capacitor 144 disposed in the peripheral area 102 does not contact any plug and cannot be electrically connected to the transistor element (not shown) in the substrate 100 to form a dummy capacitor. The bottom surfaces of the bottom electrode layers 152a, 152b, 152c of at least two capacitors 144a, 144b, 144c have different heights h1, h2, and h3 from the surface of the substrate 100 in the vertical direction D3, so that the bottom surface of the bottom electrode layer 152a of one capacitor 144a is lower than the bottom surface of the bottom electrode layer 152b of another capacitor 144b, and the bottom ends of the bottom electrode layer 152a of the capacitor 144a and / or the bottom electrode layer 152b of the capacitor 144b have a bent end portion, but the invention is not limited thereto. Alternatively, the bottom surface of the bottom electrode layer 152c of one capacitor 144c is lower than the bottom surfaces of the bottom electrode layers 152a, 152b of the capacitors 144a and 144b, and the bottom ends of the bottom electrode layer 152a of the capacitor 144a and / or the bottom electrode layer 152b of the capacitor 144b have the bent end portion. Under this configuration, the density difference between the storage area 104 and the peripheral area 102 can also be balanced during the process of manufacturing the semiconductor device 10, thereby improving the structural defects of the semiconductor device 10 of this embodiment that may be derived from the continuous increase in the density of the storage array. The semiconductor device 10 can have a more stable and reliable structure and achieve relatively optimized device performance.

[0065] In detail, Figure 2As shown, the capacitor structure 150 includes a bottom electrode layer 152, a capacitor dielectric layer 154, and a top electrode layer 156 stacked in sequence in the vertical direction D3. In this embodiment, the bottom electrode layer 152 has a continuously extending U-shaped cross section, the capacitor dielectric layer 154 is arranged on the side wall and the bottom surface of the U-shaped cross section of the bottom electrode layer 152, and the top electrode layer 156 fills the gap between the bottom electrode layers 156, so that each capacitor 144 arranged in the peripheral area 102 generally presents a cylindrical cross section, but is not limited thereto. Among them, the bent end portions of the bottom electrode layers 152a, 152b of the capacitors 144a, 144b are, for example, respectively arranged between the surface of the substrate 100 and the first support layer 162, or between the first support layer 162 and the second support layer 164, and are gradually bent from the vertical direction D3 toward the capacitor 144c arranged on one side. In one embodiment, the bent ends of the bottom electrode layers 152a, 152b preferably do not physically contact the bottom electrode layers 152b, 152a, 152c of the adjacent capacitors 144 on both sides; however, the capacitor dielectric layer 154 covering the bent ends of the bottom electrode layers 152a, 152b may be in physical contact with the capacitor dielectric layer 154 covering the bottom electrode layers 152b, 152a, 152c of the adjacent capacitors 144, such as Figure 2 As shown, but not limited to.

[0066] The semiconductor device 10 further includes a plurality of buried gate structures 120 disposed in the substrate 100, and a plurality of plugs 130 disposed on the substrate 100, wherein the gate structures 120 and the plugs 130 are both located in the storage region 104. Specifically, the gate structures 120 extend along a direction (not shown) in the substrate 100 and intersect with the shallow trench isolation 112 and the plurality of active regions 114 disposed in the substrate 100. Each gate structure 120 includes a dielectric layer 122, a gate dielectric layer 124, a gate 126, and a cap layer 128 stacked in sequence, wherein the surface of the cap layer 128 can be flush with the top surface of the substrate 100, so that each gate structure 120 can serve as a buried word line (BWL) of the semiconductor device 10. The plug 130 includes a storage node plug 132 and a storage node pad 134 sequentially stacked on the substrate 100, and adjacent plugs 130 are isolated from each other by an insulating structure (storage node contact isolation, SCISO) 136 disposed directly above each gate structure 120. In one embodiment, the storage node plug 132 includes, for example, epitaxial materials such as silicon (Si), silicon phosphorus (SiP), silicon germanium (SiGe), or germanium (Ge), and the storage node pad 134 includes, for example, a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), but is not limited thereto. In another embodiment, the storage node pad 134 can also be integrally formed with the storage node plug 132 and include the same conductive material, but is not limited thereto.

[0067] Thus, each capacitor 142 disposed in the storage area 104 can be electrically connected to the transistor components (not shown) in the substrate 100 by means of the plug 130 disposed below, forming the storage array, so as to serve as the smallest component unit (memory cell) of a dynamic random access memory (DRAM, not shown) device and receive voltage information from a bit line (BL, not shown) and a word line (i.e., a gate structure 120). Each capacitor 144 disposed in the peripheral area 102 can only contact the insulating layer 138 below, and cannot be electrically connected to the transistor components in the substrate 100, and constitutes a dummy capacitor disposed around the storage array. In addition, although the bit lines are not specifically drawn in the drawings of the present embodiment, those skilled in the art should be able to easily understand that the bit lines are parallel to each other and extend in a direction perpendicular to the word lines (i.e., the gate structure 120), are electrically connected to the substrate 100 through a bit line plug (not shown, bit line contact, BLC) formed below, and are electrically isolated from the gate structure 120 in the substrate 100 by an insulating layer (not shown, for example, including a silicon oxide-silicon nitride-silicon oxide structure) covering the top surface of the substrate 100. The semiconductor device 10 of the first embodiment of the present invention can form a dummy capacitor by setting a bottom electrode layer 152, a capacitor dielectric layer 154, and / or a top electrode layer 156 that are in physical contact with each other in the peripheral area 102, and use the setting of the dummy capacitor to balance the difference in component density between the storage area 104 and the peripheral area 102, thereby improving the structural defects that may be derived from the continuous increase in the setting density of the storage array of the semiconductor device 10 of the present embodiment, thereby having a more stable and reliable structure and achieving relatively optimized device performance.

[0068] Those skilled in the art should be able to easily understand that, in order to meet the actual product needs, the semiconductor device of the present invention may also have other aspects, not limited to the above. The following will further describe other embodiments or variations of the semiconductor device in the present invention. And to simplify the description, the following description mainly describes the differences between the embodiments, and no longer repeats the same parts. In addition, the same components in each embodiment of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0069] Please refer to Figure 3 to Figure 4 As shown, what is depicted is a schematic diagram of a semiconductor device 20 in a second embodiment of the present utility model, wherein: Figure 3 and Figure 41 and 2 are schematic top views and cross-sectional views of the semiconductor device 20, respectively. The main difference between the semiconductor device 20 of the present embodiment and the semiconductor device 10 of the aforementioned embodiment is that the capacitor structure 250 includes a bottom electrode layer 252, a capacitor dielectric layer 254, and a top electrode layer 256 stacked in sequence in the horizontal direction D1, wherein the bottom electrode layer 252 is a columnar bottom electrode, and the capacitor dielectric layer 254 and the top electrode layer 256 sequentially cover the outside of the bottom electrode layer 252 and are arranged around the columnar bottom electrode. Thus, the capacitor structure 250 includes a plurality of capacitors 240 in detail, each of which has a cylindrical cross-sectional structure, but is not limited thereto.

[0070] The capacitors 240 are arranged in an array in the horizontal direction D1 and the vertical direction D2. The capacitors 242 located in the storage area 104 are also separated from each other by the support structure 160 disposed therebetween, so that each capacitor 242 located in the storage area 104 can be connected to the plug 130 disposed below (please refer to Figure 4 In one embodiment, the two capacitors 244 located in the peripheral region 102 and in physical contact with each other, for example, have their bottom electrode layers 252, their capacitor dielectric layers 254, and their top electrode layers 256 all in physical contact with each other, forming a dummy capacitor. Figure 1 As shown, but not limited thereto. Alternatively, at least one capacitor 246 located in the peripheral region 102 has a relatively small width W1 in the horizontal direction D1, for example, so as to contact the adjacent capacitor 244. In this way, the top electrode layers 256 of two or more capacitors 244 and 246 located in the peripheral region 102 and physically contacting each other are physically contacted with each other, or the top electrode layers 256 and the capacitor dielectric layers 254 are physically contacted with each other, so as to form a virtual capacitor.

[0071] On the other hand, Figure 4As shown in the cross-sectional schematic diagram of , the bottom surfaces of the bottom electrode layers 252a, 252b, 252c of at least two capacitors 244a, 244b, 244c have different heights h1, h2, and h3 from the surface of the substrate 100 in the vertical direction D3, so that the bottom surface of the bottom electrode layer 252a of one capacitor 244a is lower than the bottom surface of the bottom electrode layer 252b of another capacitor 244b, and the bottom ends of the bottom electrode layer 252a of the capacitor 244a and / or the bottom electrode layer 252b of the capacitor 244b have a bent end portion, but the invention is not limited thereto. Alternatively, the bottom surface of the bottom electrode layer 252c of one capacitor 244c is lower than the bottom surfaces of the bottom electrode layers 252a and 252b of the capacitors 244a and 244b, and the bottom ends of the bottom electrode layer 252a of the capacitor 244a and / or the bottom electrode layer 252b of the capacitor 244b have the bent end portion.

[0072] Under this setting, the semiconductor device 20 can still form a virtual capacitor by setting a bottom electrode layer 252, a capacitor dielectric layer 254 and / or a top electrode layer 256 that are in physical contact with each other in the peripheral area 102, and balance the component density difference between the storage area 104 and the peripheral area 102 through the virtual capacitor, thereby improving the structural defects that may be derived from the continuous increase in the setting density of the storage array of the semiconductor device 20 of this embodiment, thereby having a more stable and reliable structure and achieving relatively optimized device performance.

[0073] Please refer to Figure 5 , which is a schematic diagram of a semiconductor device 30 in the third embodiment of the utility model. The semiconductor device 30 in this embodiment is substantially the same as the semiconductor device 10 in the first embodiment, and the similarities will not be repeated. The main difference between the semiconductor device 30 in this embodiment and the semiconductor device 10 in the first embodiment is that the capacitor structure 350 includes a bottom electrode layer 352, a capacitor dielectric layer 354 and a top electrode layer 156 stacked in sequence, forming a plurality of capacitors 142, 344 respectively arranged in the storage area 104 and the peripheral area 102, and the bottom of the bottom electrode layer 352a, 352b of at least one capacitor 344a, 344b arranged in the peripheral area 102 has a discontinuous film layer.

[0074] Specifically, the bottom electrode layer 352a of the capacitor 344a and the bottom electrode layer 352b of the capacitor 344b respectively include two portions that gradually bend from the vertical direction D3 toward the adjacent capacitor 144c / 344b on the same side, and the bottoms of the two portions are not connected to each other, so that the bottom electrode layers 352a and 352b of the capacitors 344a and 344b have discontinuous bottoms, such as Figure 5 Moreover, the capacitor dielectric layer 354 covering the two parts is not connected to each other and is also discontinuous. Figure 5As shown, but not limited to this. However, in another embodiment, the capacitor dielectric layer 354 covering the two parts can also selectively physically contact the capacitor dielectric layer 354 covering the bottom electrode layer 352b, 352a, 152 of the adjacent capacitor 344 (not shown). Under this setting, the semiconductor device 30 can still form a virtual capacitor by setting the bottom electrode layer 352, the capacitor dielectric layer 354 and / or the top electrode layer 156 that are in physical contact with each other in the peripheral area 102, and use the setting of the virtual capacitor to balance the component density difference between the storage area 104 and the peripheral area 102, improve the structural defects that may be derived from the continuous increase in the setting density of the storage array of the semiconductor device 30 of this embodiment, and thus have a more stable and reliable structure, and achieve relatively optimized device performance.

[0075] Please refer to Figure 6 , which is a schematic diagram of a semiconductor device 40 in a fourth embodiment of the utility model. The semiconductor device 40 in this embodiment is substantially the same as the semiconductor device 10 in the aforementioned first embodiment, and the similarities will not be repeated. The main difference between the semiconductor device 40 in this embodiment and the semiconductor device 10 in the aforementioned first embodiment is that the capacitor structure 450 includes a bottom electrode layer 452, a capacitor dielectric layer 454 and a top electrode layer 156 stacked in sequence, forming a plurality of capacitors 142, 444 respectively arranged in the storage area 104 and the peripheral area 102, and the bottom end of the bottom electrode layer 452a of at least one capacitor 444a arranged in the peripheral area 102 has a curved end portion that is gradually curved toward another capacitor 144b.

[0076] Specifically, the bottom electrode layer 452a of the capacitor 444a has a bent end portion that gradually bends from the vertical direction D3 toward the adjacent capacitor 144b on one side, and the bottom electrode layer 152b of the capacitor 144b also has a bent end portion that gradually bends from the vertical direction D3 toward the capacitor 444a. In other words, the bent end portions of the bottom electrode layer 452a of the capacitor 444a and the bottom electrode layer 152b of the capacitor 144b are disposed opposite to each other and gradually approach each other. Among them, the bent end portion of the bottom electrode layer 452a of the capacitor 444a is located between the surface of the substrate 100 and the first supporting layer 162, and the bent end portion of the bottom electrode layer 152b of the capacitor 144b is located between the first supporting layer 162 and the second supporting layer 164, as shown in FIG. Figure 6As shown. Moreover, since the bent ends of the bottom electrode layers 152b of the capacitors 444a and 144b gradually approach each other, the capacitor dielectric layer 454 covering the bottom electrode layer 452a of the capacitor 444a and the bottom electrode layer 152b of the capacitor 144b can be connected and contacted with each other, but not limited to this. However, in another embodiment, the bottom electrode layers of the capacitors 444a and 144b gradually approaching each other can also be selected to be connected and contacted with each other (not shown). Under this setting, the semiconductor device 40 can still form a virtual capacitor by setting the bottom electrode layer 452, the capacitor dielectric layer 454 or the top electrode layer 156 that are in physical contact with each other in the peripheral area 102, and use the setting of the virtual capacitor to balance the component density difference between the storage area 104 and the peripheral area 102, improve the structural defects that may be derived from the continuous increase in the setting density of the storage array of the semiconductor device 40 of this embodiment, and thus have a more stable and reliable structure, and achieve relatively optimized device performance.

[0077] Please refer to Figure 7 , which is a schematic diagram of a semiconductor device 50 in the fifth embodiment of the utility model. The semiconductor device 50 in this embodiment is substantially the same as the semiconductor device 10 in the first embodiment, and the similarities will not be repeated. The main difference between the semiconductor device 500 in this embodiment and the semiconductor device 10 in the first embodiment is that the capacitor structure 550 includes a bottom electrode layer 552, a capacitor dielectric layer 554 and a top electrode layer 156 stacked in sequence, forming a plurality of capacitors 142, 544 respectively arranged in the storage area 104 and the peripheral area 102, and the bottom end of the bottom electrode layer 152a of at least one capacitor 144a arranged in the peripheral area 102 has a curved end portion that is gradually curved toward another capacitor 544a.

[0078] Specifically, capacitor 544a extends in the vertical direction D3 and is disposed on substrate 100, and its bottom electrode layer 552a has a continuously extending U-shaped cross-section, and bottom electrode layer 152a of capacitor 144a and bottom electrode layer 552b of capacitor 544b both have bent ends that gradually bend from the vertical direction D3 toward capacitor 544a, so that capacitor 544a is sandwiched between capacitor 144a and capacitor 544b. In addition, because bottom electrode layer 552a of capacitor 544a has a relatively small width W2, unlike other capacitors 544, the bent ends of bottom electrode layer 152a of capacitor 144a and bottom electrode layer 552b of capacitor 544b gradually approach and physically contact bottom electrode layer 552a of capacitor 544a, and sandwich bottom electrode layer 552a of capacitor 544a between the two, as shown in FIG. Figure 7As shown. However, in another embodiment, the bent end portions of the bottom electrode layer 152a of the capacitor 144a and the bottom electrode layer 552b of the capacitor 544b may also be selected to be close to but not physically contact the bottom electrode layer 552b of the capacitor 544a, so that the capacitor dielectric layer 554 covering the bottom electrode layer 152a of the capacitor 144a, the bottom electrode layer 552b of the capacitor 444b and the bottom electrode layer 552a of the capacitor 544a are connected and contacted with each other, but not limited thereto. Under this setting, the semiconductor device 50 can still form a virtual capacitor by setting the bottom electrode layer 552, the capacitor dielectric layer 554 or the top electrode layer 156 that are in physical contact with each other in the peripheral area 102, and use the setting of the virtual capacitor to balance the component density difference between the storage area 104 and the peripheral area 102, thereby improving the structural defects that may be derived from the continuous increase in the setting density of the storage array of the semiconductor device 50 of this embodiment, thereby having a more stable and reliable structure and achieving relatively optimized device performance.

[0079] Please refer to Figure 8 , which is a schematic diagram of a semiconductor device 60 in a sixth embodiment of the present invention. The semiconductor device 60 in this embodiment is substantially the same as the semiconductor device 10 in the first embodiment, and the similarities will not be repeated. The main difference between the semiconductor device 60 in this embodiment and the semiconductor device 10 in the first embodiment is that the capacitor structure 650 includes a bottom electrode layer 652, a capacitor dielectric layer 654 and a top electrode layer 156 stacked in sequence, forming a plurality of capacitors 642, 644 respectively arranged in the storage area 104 and the peripheral area 102, and the bottom electrode layer 652a of at least one capacitor 644a arranged in the peripheral area 102 has a curved portion gradually curved toward another capacitor 644b, and the bottom electrode layer 652c of at least one capacitor 644c arranged in the storage area 104 also has a curved portion gradually curved toward the capacitor 644b, and the bottoms of the bottom electrode layers 652a, 652c still physically contact the insulating layer 138 or the plug 130 arranged thereunder.

[0080] Specifically, the capacitors 642 and 644a respectively disposed in the storage area 104 and the peripheral area 102 extend in the vertical direction D3 and are disposed on the substrate 100, and the bending portion of the bottom electrode layer 652c and 652a of each capacitor 642 and 644a is between the surface of the substrate 100 and the first support layer 162, and generally has a continuously extending U-shaped cross section, such as Figure 8As shown. Among them, the bent portion of the bottom electrode layer 652a of the capacitor 644a is preferably close to but not physically in contact with the bottom electrode layer 652b of the adjacent capacitor 644b, so that the capacitor dielectric layer 654 covering the bottom electrode layers 652a, 652b of the capacitors 644a, 644b is connected and in contact with each other, but not limited to this. However, in another embodiment, the bottom electrode layers 652a, 652b of the capacitors 644a, 644b can also choose to directly contact each other. Under this setting, the capacitor 642 set in the storage area 104 can still roughly correspond to the plug 130 set below to form the storage array, while the capacitors 644a, 644b, 144b set in the peripheral area 102 contact the insulating layer 138 below to form the virtual capacitor.

[0081] Under this setting, the semiconductor device 60 can still form the virtual capacitor by setting the bottom electrode layer 652, the capacitor dielectric layer 654 or the top electrode layer 156 that are in physical contact with each other in the peripheral area 102, and use the setting of the virtual capacitor to balance the difference in component density between the storage area 104 and the peripheral area 102, thereby improving the structural defects that may be derived from the continuous increase in the setting density of the storage array of the semiconductor device 60 of this embodiment, thereby having a more stable and reliable structure and achieving relatively optimized device performance. In addition, those skilled in the art should easily understand that although the semiconductor device 60 of this embodiment chooses to set capacitors 644a, 644b, and 144b in the peripheral area 102 to form the virtual capacitor, the specific structure of the virtual capacitor is not based on Figure 8 The examples shown are limited to the examples shown above, and may also include the examples shown in the previous embodiments according to actual device requirements. Figure 7 The capacitors 544a and 544b shown constitute the dummy capacitors. Figure 6 The capacitor 444a shown constitutes the dummy capacitor, Figure 5 The capacitors 344a, 344, 344c shown constitute the dummy capacitors, and selectively make their bottom electrode layers physically contact or not contact the bottom electrode layer 652c of the adjacent capacitor 642, so as to have a more stable and reliable structure.

[0082] In general, according to the semiconductor device of the present invention, a bottom electrode layer, a capacitor dielectric layer, and / or a virtual capacitor with physical contact between the top electrode layer and the top electrode layer are arranged around the memory array, thereby improving the structural defects of the semiconductor device that may be derived from the continuous increase in the density of memory cells. In this way, the semiconductor device can have a more stable and reliable structure and achieve relatively optimized device performance.

[0083] The above description is only the preferred embodiment of the utility model, and is not intended to limit the utility model. For those skilled in the art, the utility model can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A semiconductor device, characterized in that: include: substrate; as well as The capacitor structure is disposed on the substrate and includes a plurality of capacitors arranged in an array, wherein at least two capacitors are in physical contact in a horizontal direction parallel to the substrate.

2. The semiconductor device according to claim 1, wherein: Each of the capacitors includes a bottom electrode layer, a capacitor dielectric layer and a top electrode layer which are sequentially arranged in the horizontal direction.

3. The semiconductor device according to claim 2, characterized in that The bottom electrode layers of the at least two capacitors are in physical contact with each other.

4. The semiconductor device according to claim 2, characterized in that The top electrode layers of the at least two capacitors are in physical contact with each other.

5. The semiconductor device according to claim 2, wherein: The capacitor dielectric layers of the at least two capacitors are in physical contact with each other.

6. The semiconductor device according to claim 1, wherein: The widths of the at least two capacitors in the horizontal direction are different.

7. A semiconductor device, characterized in that: include: substrate; A capacitor structure, arranged on the substrate, wherein the capacitor comprises at least one first capacitor and at least one second capacitor, the bottommost surface of the bottom electrode layer of the at least one first capacitor is lower than the bottommost surface of the bottom electrode layer of the at least one second capacitor, and at least one of the bottom electrode layer of the at least one first capacitor and the bottom electrode layer of the at least one second capacitor has a bent end; as well as The support structure is arranged on the substrate and located between the capacitors. The support structure includes a first support layer and a second support layer which are arranged in sequence from bottom to top.

8. The semiconductor device according to claim 7, characterized in that The bottom electrode layer of the at least one first capacitor is bent toward one side of the at least one second capacitor.

9. The semiconductor device according to claim 7, characterized in that The bottom electrode layer of the at least one second capacitor is bent toward one side of the at least one first capacitor.

10. The semiconductor device according to claim 7, wherein: The bottommost surface of the bent end portion of the bottom electrode layer of the at least one second capacitor is located between the first supporting layer and the second supporting layer.

11. The semiconductor device according to claim 7, wherein: The bottommost surface of the bent end portion of the bottom electrode layer of the at least one second capacitor is located between the first supporting layer and the substrate.

12. The semiconductor device according to claim 7, wherein: The bottom of the bottom electrode layer of the at least one second capacitor is discontinuous.

13. The semiconductor device according to claim 7, characterized in that The capacitors each include a cylindrical cross-sectional structure.

14. The semiconductor device according to claim 7, wherein: The bent end portion of the bottom electrode layer of the at least one second capacitor has no physical contact with the bottom electrode layer of the at least one first capacitor.

15. The semiconductor device according to claim 14, characterized in that The capacitor dielectric layer covering the bottom electrode layer of the at least one first capacitor physically contacts the capacitor dielectric layer covering the bottom electrode layer of the at least one second capacitor.

16. The semiconductor device according to claim 14, characterized in that The capacitor dielectric layer covering the bottom electrode layer of the at least one first capacitor does not physically contact the capacitor dielectric layer covering the bottom electrode layer of the at least one second capacitor.

17. The semiconductor device according to claim 7, characterized in that The bottom electrode layer of the at least one second capacitor physically contacts the bottom electrode layer of the at least one first capacitor.

18. The semiconductor device according to claim 7, characterized in that A width of the bottom electrode layer of the at least one first capacitor is different from a width of the bottom electrode layer of the at least one second capacitor.

19. The semiconductor device according to claim 7, characterized in that The bottom electrode layer of at least one of the first capacitors has the bent end portion and the bottom electrode layer of at least one of the second capacitors is vertically disposed on the substrate.

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