Transient voltage suppression device

Abstract

The utility model discloses a transient voltage suppression device. The device includes a substrate, a base layer, and an inner layer. The inner layer is formed between the substrate and the base layer. A first junction is formed between the base layer and the inner layer, and a second layer is formed between the inner layer and the substrate.

Description

Technical Field

[0001] The present disclosure relates generally to the field of circuit protection devices, and in particular, to bidirectional transient voltage suppressor devices having low clamping voltage. Background Art

[0002] Modern electronic devices rely on semiconductor device diodes to achieve various functions, including, for example, circuit protection during transient overvoltage events. Such devices are manufactured using n-type and p-type semiconductor materials joined together by a junction. Such a junction is called a PN junction. A PN junction is an interface formed between a region of a semiconductor device having a first conductivity type (P or N) and a second region having a second conductivity type (N or P) opposite to the first conductivity type.

[0003] Semiconductor devices such as transient voltage suppressors (TVS) devices can be manufactured as unidirectional devices or bidirectional devices. In many applications, TVS diodes can be used to protect sensitive circuit nodes from one-time and time-limited overvoltage faults. Such TVS diodes are also used in modern high-power IGBT circuits to prevent overloads in collector circuits. Requirements for such TVS diodes can include high breakdown voltages with low deviation and low temperature coefficient, and high surge current capabilities with low clamping voltages. In addition, in many applications, TVS devices can be designed to prevent repetitive surge events, making TVS devices susceptible to damage after repetitive surge events. However, existing transient voltage suppression devices are insufficient in maintaining low clamping voltages and bidirectional capabilities. Utility Model Content

[0004] This Summary is provided to introduce in a simplified form selected concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to assist in determining the scope of the claimed subject matter.

[0005] In some embodiments, the present subject matter relates to a transient voltage suppression device. The device may include a substrate, a base layer, and an inner layer. The inner layer may be formed between the substrate and the base layer. A first junction may be formed between the base layer and the inner layer, and a second junction may be formed between the inner layer and the substrate.

[0006] In some embodiments, the current subject matter can include one or more of the following optional features: The substrate can be a P+ type substrate. The first base layer can be a P+ type base layer and the inner layer can be an N type layer.

[0007] In some embodiments, the first junction and the second junction may be PN junctions.

[0008] In some embodiments, at least one of the base layer and the inner layer can be formed using one or more first dopants deposited and / or injected into the substrate. The one or more first dopants can be deposited and / or injected using epitaxial deposition. The one or more first dopants can be N-type dopants. The one or more first dopants can include at least one of the following: phosphorus, boron, arsenic, gallium, and any combination thereof. The inner layer can have a predetermined thickness. The predetermined thickness can be determined based on the deposition and / or injection of the one or more first dopants. The transient voltage suppression device is characterized by a clamping voltage. The clamping voltage of the transient voltage suppression device can be determined as a function of at least one of the following: a predetermined concentration of one or more first dopants in the inner layer, a predetermined thickness of the inner layer, and any combination thereof.

[0009] In some embodiments, the base layer can be formed using one or more second dopants that are deposited and / or implanted into the inner layer. The one or more second dopants can be P+ type dopants.

[0010] In some embodiments, the device may include one or more isolation regions. The one or more isolation regions may include one or more isolation trenches. The one or more isolation regions may be formed through at least a portion of the base layer, the inner layer, and the substrate. The one or more isolation regions may include one or more passivation layers covering the one or more isolation regions.

[0011] In some embodiments, at least one of the substrate, the base layer, and the inner layer includes at least one of the following: silicon, silicon carbide, silicon germanium, and any combination thereof.

[0012] In some embodiments, the transient voltage suppression device may be a bidirectional transient voltage suppression device.

[0013] In some embodiments, the present subject matter relates to a method for manufacturing a transient voltage suppressor device. The method may include providing a substrate having a first polarity, forming an inner layer of a second polarity in the substrate, forming a base layer of the first polarity on top of the inner layer, and forming at least one isolation region passing through at least a portion of the base layer, the inner layer, and the substrate. A first junction may be formed between the base layer and the inner layer, and a second junction may be formed between the inner layer and the substrate. At least one of the base layer and the inner layer may be formed using one or more first dopants deposited and / or injected into the substrate.

[0014] The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the description, help explain some principles associated with the disclosed embodiments.

[0016] Figure 1 An exemplary semiconductor device is shown;

[0017] Figure 2 An exemplary transient voltage suppressor device according to some embodiments of the current subject matter is shown;

[0018] Figure 3 Another exemplary transient voltage suppressor device according to some embodiments of the current subject matter is shown;

[0019] Figure 4a to Figure 4b An example current-voltage graph is shown;

[0020] Figure 5 An exemplary process according to some implementations of the current subject matter is shown.

[0021] The drawings are not necessarily drawn to scale. The drawings are merely representations and are not intended to depict specific parameters of the present disclosure. The drawings are intended to depict exemplary embodiments of the subject matter and are therefore not to be considered limiting of the scope. In the drawings, the same numerals represent the same elements.

[0022] In addition, for the sake of clarity, some elements in some of the figures may be omitted and / or not shown to scale. The cross-sectional views may be in the form of "slices", or in the form of "close-up" cross-sectional views, omitting certain background lines that would otherwise be visible in a "true" cross-sectional view for the sake of clarity. In addition, for the sake of clarity, some reference numerals may be omitted in some of the figures. DETAILED DESCRIPTION

[0023] Various methods according to the present disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments of systems and methods are shown. Devices, (one or more) systems, (one or more) components, etc. may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the current subject matter to those skilled in the art.

[0024] To address these and potential other deficiencies of currently available solutions, one or more embodiments of the present subject matter are directed to methods, systems, articles of manufacture, etc., that can provide bidirectional transient voltage suppressor devices with low clamping voltages that can provide improved surge performance, among other possible advantages.

[0025] Transient voltage suppressor (TVS) semiconductor devices can be used to protect electronic components from transient voltages, overvoltages, etc. TVS chips are often used as the core of TVS semiconductor devices. As can be appreciated, any other type of semiconductor chip and / or device can be used. As described above, such TVS devices can be used to prevent voltage transients that may be detrimental to the operation of various electronic components.

[0026] Voltage transients are defined as short-duration surges of electrical energy and are the result of a sudden release of previously stored energy and / or caused by other means such as, for example, heavy inductive loads, lightning, etc. Voltage transients can be classified as predictable or repeatable transients and random transients. In electrical or electronic circuits, this energy can be released in a predictable manner via controlled switching actions, or randomly introduced into the circuit from an external source. Repeatable transients are usually caused by the operation of motors, generators, and / or the switching of reactive circuit components. On the other hand, random transients are often caused by electrostatic discharge (ESD) and lightning, which usually occur unpredictably.

[0027] ESD is characterized by very fast rise times and very high peak voltages and currents, which can be the result of an imbalance of positive and negative charges between objects. ESD generated by everyday activities can exceed the vulnerability threshold of standard semiconductor technology. In the case of lightning, even if a direct lightning strike is destructive, the voltage transients caused by lightning are not the result of a direct lightning strike. When a lightning strike occurs, the event generates a magnetic field, which in turn can cause large voltage transients in nearby power cables. For example, a cloud-to-cloud strike will affect not only overhead cables, but also buried cables. Even a lightning strike 1 mile (1.6km) away can generate 50 volts in power cables. In a cloud-to-ground lightning strike, the voltage transients generated are significantly greater.

[0028] Semiconductor devices may include various layers, including mesa layers or regions, which may be regions on a semiconductor wafer that have not been etched away. Typically, the mesa region may have a flat surface and may rise above the surrounding semi-insulating substrate(s). The height of this rise is typically very small (e.g., less than one (1) micron). Glass passivation layers may be added to various portions of semiconductor devices (e.g., ends) as a means of protecting the device.

[0029] Figure 1An exemplary semiconductor device 100 is shown. Semiconductor device 100 includes p-type base layer 102, n-type substrate 104, and p-type base layer 106. Substrate 104 can be a p-type layer and / or an n-type layer. Pn junction 105 can be formed between base layer 102 and substrate 104, and pn junction 107 can be formed between substrate 104 and base layer 106. In some cases, substrate 104 can include most electrons and few charge carrier holes, and base layer 102 and / or base layer 106 can include most charge carrier holes and few electrons.

[0030] In the case of an n-type substrate 104, free electrons from the substrate 104 may diffuse into the base layer 102, generating immovable positive ions in the substrate 104 and immovable negative ions in the base layer 102 and / or the base layer 106. The immovable positive ions and negative ions from both sides may be concentrated at the pn junctions 105, 107 formed between the base layer 102 and the substrate 104 and / or the substrate 104 and the base layer 106. The pn junctions 105, 107 may also be referred to as depletion regions. An electrostatic field may be generated at the pn junction, thereby preventing further migration of electrons across the junction.

[0031] Figure 2 An exemplary TVS device 200 according to some embodiments of the current subject matter is shown. The TVS device 200 can be formed in a monolithic semiconductor substrate, such as silicon. In particular, the TVS device 200 can include a substrate 202, an inner layer 204, and a base layer 206. The substrate 202 can be formed to have a first type of polarity. For example, the polarity of the substrate can be a P+ type. The inner layer 204 can be formed between the base layer 206 and the substrate 202. The base layer 206 can have a first type of polarity, for example, a P+ type. The inner layer 204 can have a second type of polarity. For example, the polarity of the inner layer 204 can be an N-type.

[0032] Base layer 206 may form a PN junction 205 with inner layer 204. Substrate 202 may form a PN junction 207 with inner layer 204. The structure of device 200 allows it to be a bidirectional TVS device.

[0033] As can be understood, although Figure 2 The device 200 is shown based on a P-type substrate, but the TVS device 200 may have an N-type substrate with a P-type base layer and an N-type inner layer. In addition, although the TVS device 200 is a bidirectional device, the device 200 may be a unidirectional device.

[0034] In some embodiments, the TVS device 200 may further include one or more isolation trenches 214 (a, b), which may be formed and / or etched in one or more layers of the TVS device 200. Figure 2 As shown, the isolation trench 214a can be disposed at the upper left corner of the TVS device 200 and, in particular, protrudes through the entire depth of at least a portion of the base layer 206, the inner layer 204, and the substrate 202. The isolation trench 214b can be disposed at the upper right corner of the TVS device 200 and also protrudes through the entire depth of at least a portion of the base layer 206, the inner layer 204, and the substrate 202.

[0035] The isolation trench 214 may be covered by a first passivation layer 216a and a second passivation layer 216b. For example, the isolation trench 214a may be covered by the passivation layer 216a, and the isolation trench 214b may be covered by the passivation layer 216b. The passivation layers 216 (a, b) may be glass passivation layers, thin film glass passivation layers, and / or any other type of material. The passivation layer 216 may be configured to protect the trench 214 and, in particular, to protect the terminals of the TVS device 200. In addition, the passivation layer may also be designed to reduce and / or prevent current leakage at the terminal edges of the TVS device 200.

[0036] In some embodiments, the inner layer 204 can be formed in the substrate 202 by depositing (e.g., using epitaxial (EPI) deposition) and / or implanting dopants (e.g., N-type dopants) in the substrate 202. The dopant can include at least one of phosphorus, boron, arsenic, gallium, and any combination thereof. In addition, the deposition of N-type dopants into the substrate 202 can also be configured to form a PN junction 207. The PN junction 207 can also be referred to as a backside PN junction.

[0037] The deposition / injection of dopants into the substrate 202 may also be configured to form a PN junction 205 with the base layer 206. The PN junction 205 may be referred to as a frontside PN junction. The base layer 206 may be formed after the deposition / injection of N-type dopants into the substrate 202. Alternatively or in addition, to form the base layer 206, one or more P+ type dopants may be deposited and / or injected into the inner layer 204 to form the frontside PN junction 205. Once the multi-layer structure of the TVS device is formed, the isolation trench 214 may be formed or etched through some of the layers 202-206 and / or into some of the layers 202-206.

[0038] In some embodiments, N-type dopants may be deposited / implanted into the substrate 202 at various depths, resulting in different thicknesses of the inner layer 204. This may allow tuning of the current gain of the TVS device 200, thereby controlling the voltage foldback characteristics, which in turn may control the clamping voltage of the TVS device 200. The clamping voltage may be referred to as the voltage at which the TVS device 200 may be configured to conduct its full rated current (e.g., hundreds of amperes, thousands of amperes, etc.). For example, a higher concentration of P+ type dopants in the substrate 202 may further reduce the series resistance and reduce the clamping voltage of the TVS device 200 during high surge current events.

[0039] The corresponding doping concentration (s) in the inner layer 204 and / or the substrate 202 and / or the base layer 206 may be uniform. Alternatively or in addition, such concentration (s) may be non-uniform. The specific concentration may allow for specific configuration (s) of the TVS device 200, which may enable configuration of a specific clamping voltage of the TVS device 200. As described above, the inner layer 204 may have a predetermined thickness. The thickness of the inner layer 204 may be less than the thickness of the substrate 202 and / or the base layer 206. Alternatively or in addition, the thickness of the inner layer 204 may be greater than and / or equal to the thickness of the base layer 206. In some embodiments, the thickness of each of the inner layers 204 may be greater than, less than and / or equal to the thickness of the base layer 206.

[0040] As may be appreciated, other types of doping of the substrate 202 , base layer 204 , and / or inner layer 204 (and / or any other component of the TVS device 200 ) may be possible.

[0041] In some embodiments, all layers 202-206 can be made of the same material, for example, silicon. Alternatively or in addition, at least one of the layers 202-206 can be made of a different material. The layers 202-206 can be configured to have the same and / or different dopant materials and / or corresponding concentrations.

[0042] Figure 3 Another exemplary TVS device 300 according to some embodiments of the current subject matter is shown. Figure 2 , TVS device 300 may be formed in a monolithic semiconductor substrate, such as, for example, silicon. TVS device 300 may include substrate 302, inner layer 304, and base layer 306. Substrate 302 may be formed to have a first type of polarity, for example, P+ type. Inner layer 304 may be formed between base layer 306 and substrate 302. Base layer 306 may have a first type of polarity, for example, P+ type, and inner layer 304 may have a second type of polarity, for example, N type.

[0043] Similar to TVS device 200, in TVS device 300, base layer 306 can form PN junction 305 with inner layer 304. Substrate 302 can form PN junction 307 with inner layer 304. TVS device 300 can also be a bidirectional TVS device. Alternatively or in addition, TVS device 300 can be a unidirectional device. TVS device 300 can be based on a P-type substrate, an N-type substrate, and / or any other type of substrate, wherein layers 304 and / or 306 have corresponding polarities.

[0044] The TVS device 300 may also include one or more isolation regions 314(a, b), which may be similar to the isolation trenches 214(a, b) of the TVS device 200. The isolation regions 314 may be formed and / or etched in one or more layers of the TVS device 300. For example, the isolation region 314a may be formed in the upper left corner of the TVS device 300, spanning the entire depth of the base layer 306, the inner layer 304, and at least a portion of the substrate 302. Similarly, the isolation region 314b may be formed in the upper right corner of the TVS device 300, spanning the entire depth of the base layer 306, the inner layer 304, and at least a portion of the substrate 302.

[0045] The isolation regions 314 may be covered by respective passivation layers 316 (a, b), for example, the passivation layer 316a may cover the isolation region 314a and the passivation layer 316b may cover the isolation region 314b. The passivation layer 316 may be a glass passivation layer, a thin film glass passivation layer, and / or any other type of material. The passivation layer 316 may be configured to protect the terminals of the TVS device 300 and reduce and / or prevent current leakage at the terminal edges of the TVS device 300.

[0046] Similar to the inner layer 204 in the TVS device 200, the inner layer 304 can be formed in the substrate 302 by depositing / implanting (e.g., using epitaxial (EPI) deposition) dopants (e.g., N-type dopants) in the substrate 302. The dopant may include at least one of phosphorus, boron, arsenic, gallium, and any combination thereof. Such deposition may form a backside PN junction 307. The deposition / implantation of the dopant into the substrate 302 may form a frontside PN junction 305 with the base layer 306. The base layer 306 may be formed after the deposition / implantation of the N-type dopant into the substrate 302. Alternatively or in addition, to form the base layer 306, one or more P+ type dopants may be deposited and / or implanted into the inner layer 304, thereby forming the frontside PN junction 305. Once the multi-layer structure of the TVS device is formed, the isolation region 314 may be formed or etched through some of the layers 302-206 and / or into some of the layers 302-206.

[0047] Similar to TVS device 200, dopants forming inner layer 304 may be deposited / implanted into substrate 302 at various depths, which may allow inner layer 304 to have different thicknesses, thereby allowing tuning of the current gain of TVS device 300. This may ultimately control the clamping voltage of TVS device 300 as described above.

[0048] As mentioned above about Figure 2 As described, the respective doping concentrations in the inner layer 304 and / or the substrate 302 and / or the base layer 306 may be uniform and / or non-uniform. A particular concentration and / or thickness of the inner layer 304 may allow for a particular configuration of the TVS device 300, thereby enabling it to have a desired clamping voltage. As may be appreciated, other types of doping of the substrate 302, the base layer 304, and / or the inner layer 304 (and / or any other component of the TVS device 300) may be possible.

[0049] In some embodiments, all layers 302-206 can be made of the same material, for example, silicon. Alternatively or in addition, at least one of the layers 302-206 can be made of a different material. The layers 302-206 can be configured to have the same and / or different dopant materials and / or corresponding concentrations.

[0050] Figure 4a to Figure 4b An example current-voltage graph is shown. Figure 4a A graph 402 showing the clamping voltage of a conventional TVS device is shown. Figure 4b The TVS device (eg Figures 2 to 3 FIG. 4 is a graph 404 showing the clamping voltage of the TVS device 200, 300). Figure 4b As shown, the TVS device 200 of the present subject matter has a significantly reduced clamping voltage.

[0051] Figure 5 An exemplary process 500 for manufacturing a transient voltage suppressor device according to some embodiments of the current subject matter is shown. The process 500 can be used to manufacture, for example, Figure 2 The TVS device 200 and / or Figure 3 The TVS device 300 is shown.

[0052] At 502, a substrate having a first polarity may be provided. For example, the substrate may be substrate 202 and / or 302. The substrate may be a P+ type substrate. As may be appreciated, the substrate may have any other desired polarity.

[0053] At 504, an inner layer may be formed in the substrate. For example, the inner layer may be inner layer 204 and / or 304, respectively. Figures 2 to 3As shown. Various methods can be used to form the inner layer in the substrate. For example, one or more dopants can be deposited and / or implanted (e.g., using epitaxial (EPI) deposition) into the substrate. The dopant can be an N-type dopant. By way of non-limiting example, the dopant can include at least one of: phosphorus, boron, arsenic, gallium, and any combination thereof. The deposition / implantation of the dopant can be configured to form a backside PN junction between the substrate and the inner layer (e.g., below the inner layer).

[0054] At 506, a base layer may be formed on top of the inner layer. For example, the base layer may be base layer 206 and / or 306, respectively. Figures 2 to 3 As shown. In some embodiments, the deposition / injection of dopants to form the inner layer into the substrate can also be configured to form a front-side PN junction between the base layer and the inner layer (e.g., above the inner layer). The base layer can be formed after the deposition / injection of the inner layer to form the dopant into the substrate. Alternatively or in addition, to form the base layer, one or more dopants (e.g., P+ type) can be deposited and / or injected into the inner layer to form a front-side PN junction and a base layer.

[0055] At 508, one or more isolation regions may be formed through at least the base layer, the inner layer, and at least a portion of the substrate. The isolation regions may include Figure 2 One or more isolation trenches 214 (a, b) and / or Figure 3 Isolation regions 314(a, b) are shown. The isolation regions may be covered by a passivation layer, such as passivation layer 216(a, b) covering trenches 214(a, b), respectively, and passivation layer 316(a, b) covering regions 314(a, b), respectively.

[0056] The components and features of the above-mentioned devices can be implemented using any combination of discrete circuits, application specific integrated circuits (ASICs), logic gates, and / or single chip architectures. In addition, the features of the devices can be implemented using microcontrollers, programmable logic arrays, and / or microprocessors, or any combination of the foregoing, where appropriate. It should be noted that hardware, firmware, and / or software elements may be collectively or individually referred to herein as "logic" or "circuitry."

[0057] It will be understood that the exemplary devices shown in the above block diagrams may represent a functional descriptive example of many potential implementations. Therefore, the division, omission or inclusion of block functions depicted in the accompanying drawings does not mean that the hardware components, circuits, software and / or elements used to implement these functions must be divided, omitted or included in the embodiments.

[0058] Some embodiments may be described using the expression "one embodiment" or "an embodiment" and its derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The phrase "in one embodiment" (or its derivatives) appearing in different places in the specification does not necessarily refer to the same embodiment. In addition, unless otherwise stated, the above-mentioned features are considered to be usable together in any combination. Therefore, any features discussed separately can be adopted in combination with each other, unless it is noted that these features are incompatible with each other.

[0059] It is emphasized that the abstract of the present disclosure is provided to allow the reader to quickly determine the nature of the present technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of simplifying the present disclosure. The disclosure method should not be interpreted as reflecting the intention that the claimed embodiment requires more features than those explicitly stated in each claim. On the contrary, as reflected in the following claims, the creative subject lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are incorporated into the detailed description, wherein each claim exists independently as a separate embodiment. In the appended claims, the terms "including" and "wherein" are used as the plain English equivalents of the corresponding terms "including" and "wherein", respectively. In addition, the terms "first", "second", "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects. In addition, the use of "including", "comprising" or "having" and its variants herein is intended to cover the items listed thereafter and their equivalents and additional items. Therefore, the terms "including", "comprising" or "having" and their variants are open expressions and can be used interchangeably herein.

[0060] For convenience and clarity, terms such as "top," "bottom," "upper," "lower," "vertical," "horizontal," "lateral," "cross," "radial," "inner," "outer," "left," and "right" may be used herein to describe the relative placement and orientation of features and components, each relative to the geometry and orientation of other features and components appearing in the perspective, exploded perspective, and cross-sectional views provided herein. The terminology is not intended to be limiting and includes the words specifically mentioned, derivatives thereof, and words of similar meaning.

[0061] What has been described above includes examples of the disclosed architecture. Of course, it is not possible to describe every conceivable combination of components and / or methods, but one of ordinary skill in the art may recognize that many further combinations and permutations are possible. Therefore, the novel architecture is intended to embrace all such changes, modifications, and variations that fall within the spirit and scope of the appended claims.

[0062] The foregoing description of example embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the disclosure. It is intended that the scope of the disclosure is not limited by this specific embodiment, but rather by the claims appended hereto. Future applications claiming priority to the present application may claim the disclosed subject matter in different ways, and may generally include any set of one or more limitations as variously disclosed or otherwise presented herein.

[0063] All directional references (e.g., proximal, distal, up, down, upward, downward, left, right, lateral, longitudinal, front, back, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are used for identification purposes only to assist the reader in understanding the present disclosure and do not create limitations, particularly with respect to the position, orientation, or use of the present disclosure. Connection references (e.g., attach, couple, connect, and engage) should be interpreted broadly and may include intermediate members between a collection of elements and relative movement between elements, unless otherwise specified. Therefore, a connection reference does not necessarily mean that two elements are directly connected and are in a fixed relationship to each other.

[0064] Additionally, identifying references (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to imply importance or priority, but are used to distinguish one feature from another. The drawings are for illustrative purposes only, and the dimensions, positions, order, and relative sizes reflected in the drawings attached hereto may vary.

[0065] The present disclosure is not limited in scope by the specific embodiments described herein. In fact, various other embodiments of the present disclosure and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and the accompanying drawings. Therefore, such other embodiments and modifications are intended to fall within the scope of the present disclosure. In addition, the present disclosure has been described herein in the context of specific embodiments in specific environments for specific purposes. Those of ordinary skill in the art will recognize that usefulness is not limited thereto, and the present disclosure can be beneficially implemented in any number of environments for any number of purposes. Therefore, the claims set forth below should be interpreted according to the full breadth and spirit of the present disclosure as described herein.

Claims

1. A transient voltage suppression device, characterized in that: include: substrate; Basal layer; as well as An inner layer is formed between the substrate and the base layer, wherein a first junction is formed between the base layer and the inner layer, and a second junction is formed between the inner layer and the substrate.

2. The transient voltage suppression device according to claim 1, characterized in that: The substrate is a P+ type substrate.

3. The transient voltage suppression device according to claim 2, characterized in that: The first base layer is a P+ type base layer, and the inner layer is an N type layer.

4. The transient voltage suppression device according to claim 1, characterized in that: The first junction and the second junction are PN junctions.

5. The transient voltage suppression device according to claim 1, characterized in that: Also included is one or more isolation zones.

6. The transient voltage suppression device according to claim 5, characterized in that: The one or more isolation regions include one or more isolation trenches.

7. The transient voltage suppression device according to claim 5, characterized in that: The one or more isolation regions are formed through at least a portion of the base layer, the inner layer, and the substrate.

8. The transient voltage suppression device according to claim 5, characterized in that: The one or more isolation regions include one or more passivation layers covering the one or more isolation regions.

9. The transient voltage suppression device according to claim 1, characterized in that: The transient voltage suppression device is a bidirectional transient voltage suppression device.

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