Arbitrary waveform generator

Abstract

The utility model discloses an arbitrary waveform generator which comprises an input connector, an output connector, a first waveform generation module, a second waveform generation module, a 40M crystal oscillator, an 8M crystal oscillator, a digital-to-analog conversion module, a first operational amplifier module, a second operational amplifier module, a first gain amplifier module and a second gain amplifier module. The input ports SCLK, SDIO and CS of the first waveform generation module and the second waveform generation module are in communication connection with the SPI; the 40M crystal oscillator and the 8M crystal oscillator are connected between CLKP ports of the first waveform generation module and the second waveform generation module; an SCL input port and an SDA input port of the digital-to-analog conversion module are respectively connected with an I2CSCL1 and an I2CSDA1 on the input connector; according to the utility model, SPI communication is built in, an on-chip mode memory is integrated, complex waveforms can be directly generated, the frequency and the degree of symmetry can be adjusted, and different waveforms, except for common sine waves, square waves and sawtooth waves, can alternately appear.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic equipment or instruments, in particular to an arbitrary waveform generator. Background Art

[0002] Waveform generators are used in testing, calibration, simulation and research in various fields. Existing waveform generators in professional fields are expensive, and low-end waveform generators are cheap, but have poor scalability, single functional modes, and are not easy to integrate. In the experimental process, the programming function of arbitrary function waveforms cannot be perfectly displayed, and the resource utilization rate is not high. There is an urgent need for a low-cost, high-performance, and multi-functional arbitrary waveform generator to meet daily needs. Utility Model Content

[0003] In order to solve the defects of the prior art that the basket is large in size, occupies a large space when not in use, and is inconvenient to store the basket, the utility model provides an arbitrary waveform generator.

[0004] In order to solve the above technical problems, the utility model provides the following technical solutions:

[0005] The utility model discloses an arbitrary waveform generator, comprising an input connector, an output connector, a first waveform generating module, a second waveform generating module, a 40M crystal oscillator, an 8M crystal oscillator, a digital-to-analog conversion module, a first operational amplifier module, a second operational amplifier module, a first gain amplifier module, and a second gain amplifier module;

[0006] The input ports SCLK, SDIO, and CS of the first waveform generating module and the second waveform generating module are connected to the SPI communication; the 40M crystal oscillator and the 8M crystal oscillator are connected between the CLKP ports of the first waveform generating module and the second waveform generating module;

[0007] The SCL and SDA input ports of the digital-to-analog conversion module are respectively connected to I2C_SCL1 and I2C_SDA1 on the input connector, and its VoutA and VoutB are respectively connected to the positive input terminals of the first operational amplifier module and the second operational amplifier module;

[0008] The IOUTN and IOUTP ports of the first waveform generating module are connected to the V+ and V- input terminals of the first gain amplifier module, and the IOUTN and IOUTP ports of the second waveform generating module are connected to the V+ and V- input terminals of the second gain amplifier module; the output terminal of the first operational amplifier module is connected to the first gain amplifier module; and the output terminal of the second operational amplifier module is connected to the second gain amplifier module.

[0009] As a preferred technical solution of the utility model, the VREF terminal of the digital-to-analog conversion module is connected to a reference source, and the reference source is connected to the voltage follower input terminals of the first operational amplifier module and the second operational amplifier module.

[0010] As a preferred technical solution of the present utility model, both the first waveform generating module and the second waveform generating module adopt AD9102BCPZ chip.

[0011] As a preferred technical solution of the present utility model, both the first operational amplifier module and the second operational amplifier module adopt the TXEAPLSANF chip.

[0012] As a preferred technical solution of the present invention, the digital-to-analog conversion module adopts the AD5667RBRMZ-1 chip.

[0013] As a preferred technical solution of the present utility model, the first gain amplifier module and the second gain amplifier module both adopt the AD5667RBRMZ-1 chip.

[0014] The beneficial effects of the utility model are:

[0015] This arbitrary waveform generator has built-in SPI communication and integrated on-chip pattern memory. It can directly generate complex waveforms, adjust frequency and symmetry, and make different waveforms appear alternately. In addition to common sine waves, square waves and sawtooth waves, the utility model can synthesize other waveforms by modifying different frequencies on the basis of sine waves; I2C outputs analog voltage and internal reference voltage through the digital-to-analog conversion module, and outputs gain control voltage to adjust the gain amplifier through the operational amplifier circuit, thereby adjusting the bias voltage of the waveform and outputting an arbitrary waveform signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0017] Figure 1 This is a principle block diagram of an arbitrary waveform generator of the utility model;

[0018] Figure 2 It is an adjustable bias voltage diagram of an arbitrary waveform generator of the utility model;

[0019] Figure 3 The utility model discloses an arbitrary waveform generating circuit diagram generated by an arbitrary waveform generator.

[0020] In the figure: 1. Input connector; 2. Output connector; 3. First waveform generating module; 4. Second waveform generating module; 5. 40M crystal oscillator; 6. 8M crystal oscillator; 7. Digital-to-analog conversion module; 8. First operational amplifier module; 9. Second operational amplifier module; 10. First gain amplifier module; 11. Second gain amplifier module; 12. Reference source. DETAILED DESCRIPTION

[0021] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0022] Example: Figure 1 , Figure 2 and Figure 3 As shown, the utility model is an arbitrary waveform generator, comprising an input connector 1, an output connector 2, a first waveform generating module 3, a second waveform generating module 4, a 40M crystal oscillator 5, an 8M crystal oscillator 6, a digital-to-analog conversion module 7, a first operational amplifier module 8, a second operational amplifier module 9, a first gain amplifier module 10 and a second gain amplifier module 11;

[0023] The input ports SCLK, SDIO, and CS of the first waveform generating module 3 and the second waveform generating module 4 are connected to the SPI communication; the interface allows read / write access to all registers and on-chip SRAM configured with AD9102BCPZ. The first waveform generating module 3 and the second waveform generating module 4 have no clock signal inside, and two clock signals need to be provided externally. The FPGA enables a 40M crystal oscillator or an 8M crystal oscillator to provide a reference signal. The 40M crystal oscillator and the 8M crystal oscillator are connected between the CLKP ports of the first waveform generating module 3 and the second waveform generating module 4; a stable frequency is generated by the crystal oscillator to form a low-voltage differential signal to the waveform generator.

[0024] The SCL and SDA input ports of the digital-to-analog conversion module are respectively connected to I2C_SCL1 and I2C_SDA1 on the input connector 1, and its VoutA and VoutB are respectively connected to the positive input terminals of the first operational amplifier module 8 and the second operational amplifier module 9. The VREFIN port of the AD5667RBRMZ-1 is used as a reference voltage and is connected to the negative input port of the operational amplifier module.

[0025] The operational amplifier (ADA4522-2ARZ) contains two parts, a voltage follower and an op amp subtractor. The voltage follower input is connected to the reference source, namely the VREF end of the digital-to-analog conversion module, as an internal output reference and an external reference source. The analog output voltage of the DAC is used as the positive input of the subtractor, and the follower output is used as the negative input of the subtractor. The subtractor output voltage is used as the gain control voltage of the gain amplifier to adjust its bias voltage.

[0026] The IOUTN and IOUTP ports of the first waveform generating module 3 are connected to the V+ and V- input terminals of the first gain amplifier module 10, and the IOUTN and IOUTP ports of the second waveform generating module 4 are connected to the V+ and V- input terminals of the second gain amplifier module 11; the output terminal of the first operational amplifier module 8 is connected to the first gain amplifier module 10; the output terminal of the second operational amplifier module 9 is connected to the second gain amplifier module 11. The VREF terminal of the digital-to-analog conversion module 7 is connected to a reference source 12, and the reference source is connected to the voltage follower input terminals in the first operational amplifier module 8 and the second operational amplifier module 9.

[0027] Step 1: The V+ and V- input terminals of the gain amplifier module (VCA824IDGST) are connected to the IOUTN and IOUTP ports of the waveform generation module. The bias voltage amplitude modulation is related to the positive and negative power supply of the gain amplifier (VCA824IDGST) and the waveform amplitude. The gain control voltage can adjust the gain linearly from 1V to -1V, and finally output the DDS waveform after filtering. Figure 2 Take the sine wave as an example. Its bipolar input is on a ±8 V power supply. Assuming the output amplitude is 5 V and the phase is 0 degrees, the maximum bias voltage for the output to produce a complete waveform is ±2.5 V due to the power supply limitation of the gain amplifier (VCA824IDGST). When this value is exceeded, clipping will occur. Other output waveforms are based on this standard.

[0028] The utility model has built-in SPI communication and integrated on-chip mode memory. It can directly generate complex waveforms, adjust frequency and symmetry, and make different waveforms appear alternately. In addition to the common sine wave, square wave and sawtooth wave, the utility model can synthesize other waveforms by modifying different frequencies on the basis of the sine wave. I2C outputs analog voltage and internal reference voltage through the digital-to-analog conversion module, and outputs gain control voltage to adjust the gain amplifier through the operational amplifier circuit, and then adjusts the bias voltage of the waveform to output arbitrary waveform signals. The maximum bias voltage is related to the chip bipolar input power supply. The maximum gain design meets the requirements of ±2.5V and above. The maximum bias corresponding to the 5V amplitude is 2.5V, and the amplitude bias below 5V is greater than 2.5V. The ±8V input voltage is used in this design, considering reducing power consumption while meeting the bias requirements of arbitrary waveforms.

[0029] Finally, it should be noted that the above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. Although the utility model is described in detail with reference to the above embodiments, those skilled in the art can still modify the technical solutions recorded in the above embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. An arbitrary waveform generator, characterized in that: It comprises an input connector (1), an output connector (2), a first waveform generating module (3), a second waveform generating module (4), a 40M crystal oscillator (5), an 8M crystal oscillator (6), a digital-to-analog conversion module (7), a first operational amplifier module (8), a second operational amplifier module (9), a first gain amplifier module (10) and a second gain amplifier module (11); The input ports SCLK, SDIO and CS of the first waveform generating module (3) and the second waveform generating module (4) are connected to the SPI communication; the 40M crystal oscillator and the 8M crystal oscillator are connected between the CLKP ports of the first waveform generating module (3) and the second waveform generating module (4); The SCL and SDA input ports of the digital-to-analog conversion module are respectively connected to I2C_SCL1 and I2C_SDA1 on the input connector (1), and its VoutA and VoutB are respectively connected to the positive input terminals of the first operational amplifier module (8) and the second operational amplifier module (9); The IOUTN and IOUTP ports of the first waveform generating module (3) are connected to the V+ and V- input terminals of the first gain amplifier module (10), and the IOUTN and IOUTP ports of the second waveform generating module (4) are connected to the V+ and V- input terminals of the second gain amplifier module (11); the output terminal of the first operational amplifier module (8) is connected to the first gain amplifier module (10); and the output terminal of the second operational amplifier module (9) is connected to the second gain amplifier module (11).

2. An arbitrary waveform generator according to claim 1, characterized in that: The VREF terminal of the digital-to-analog conversion module (7) is connected to a reference source (12), and the reference source is connected to the voltage follower input terminals of the first operational amplifier module (8) and the second operational amplifier module (9).

3. An arbitrary waveform generator according to claim 1, characterized in that: The first waveform generating module (3) and the second waveform generating module (4) both use an AD9102BCPZ chip.

4. An arbitrary waveform generator according to claim 2, characterized in that: The first operational amplifier module (8) and the second operational amplifier module (9) both use a TXEAPLSANF chip.

5. The arbitrary waveform generator according to claim 1, characterized in that: The digital-to-analog conversion module (7) uses the AD5667RBRMZ-1 chip.

6. An arbitrary waveform generator according to claim 5, characterized in that: The first gain amplifier module (10) and the second gain amplifier module (11) both use the AD5667RBRMZ-1 chip.

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