Multi-stage trench semi-buried shielding SGTMOSFET device

Abstract

The utility model discloses a multi-stage groove semi-buried shielding SGTMOSFET device, which comprises a substrate, a silicon epitaxial layer is prepared on the substrate, a P-type body region and an active region N-type ion layer are propelled on the surface of the silicon epitaxial layer, and the depth of the active region N-type ion layer is greater than that of the P-type body region; the active region groove is formed in the silicon epitaxial layer, and the depth of the active region groove is between that of the P-type body region and that of the active region N-type ion layer; the first-stage groove is formed in the silicon epitaxial layer; the second-stage groove is formed in the silicon epitaxial layer, the second-stage groove is formed along the side wall of the first-stage groove, the width of the second-stage groove is larger than that of the first-stage groove, and the depth of the second-stage groove is smaller than that of the first-stage groove. According to the invention, the multi-level trench is realized by using a multi-time grooving etching technology, the deep-injected half-wrapped shielding isolated ion injection layer is realized at the bottom of the trench, and excellent on-resistance and through-current capability are realized while the chip area is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a multi-level trench semi-buried shielded SGTMOSFET device. Background Art

[0002] Split Gate Trench MOSFET (separate gate trench metal oxide semiconductor field effect transistor, hereinafter referred to as SGTMOSFET) is a type of MOS structure, such as Figure 6 As shown in Figure 1, its key features are the trench design and split gate design, which help reduce the size of the device and improve device performance. Existing SGTMOSFET devices still have room for improvement in terms of on-resistance, current flow capacity and device stability. Utility Model Content

[0003] The purpose of this section is to summarize some aspects of the embodiments of the present application and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the abstract of the specification and the application name of the present application to avoid blurring the purpose of this section, the abstract of the specification and the application name, and such simplifications or omissions cannot be used to limit the scope of the present application.

[0004] In view of the above problems and / or problems existing in the prior art, this application is proposed.

[0005] Therefore, the technical problem to be solved by this application is: how to improve the performance and stability of SGTMOSFET devices.

[0006] To solve the above technical problems, the present application provides the following technical solutions: a multi-level trench semi-buried shielded SGTMOSFET device, comprising: a substrate, a silicon epitaxial layer is prepared on the substrate, a surface of the silicon epitaxial layer is advanced with a P-type body region and an active area N-type ion layer, the depth of the active area N-type ion layer is greater than the P-type body region; an active area groove, the active area groove is opened on the silicon epitaxial layer, and the depth is between the P-type body region and the active area N-type ion layer; a primary groove, the primary groove is opened on the silicon epitaxial layer; a secondary groove, the secondary groove is opened on the silicon epitaxial layer, the secondary groove is opened along the side wall of the primary groove, and the width of the secondary groove is greater than that of the primary groove and the depth is less than that of the primary groove.

[0007] As a preferred solution of the multi-level trench semi-buried shielded SGTMOSFET device described in the present application, wherein: the width of the first-level trench is 1-5 μm, and the depth is 2-6 μm.

[0008] As a preferred solution of the multi-level trench semi-buried shielded SGTMOSFET device described in the present application, a P+ type electric field shielding buried layer is implanted into the sidewall and bottom of the first-level trench.

[0009] As a preferred solution of a multi-level groove semi-buried shielded SGTMOSFET device described in the present application, the sidewalls and bottom of the first-level groove are filled and etched with a silicon oxide layer, the first-level groove is filled and etched with a POLY layer, and the thickness of the silicon oxide layer is greater than that of the POLY layer.

[0010] As a preferred solution of a multi-level groove semi-buried shielded SGTMOSFET device described in the present application, the bottom and sidewalls of the secondary groove are also filled with a silicon oxide layer, the secondary groove is filled and etched with a POLY layer, and an IPO layer with a thickness of 4000-8000 angstroms is left between the primary groove and the secondary groove.

[0011] A BPSG phosphorus-silicon glass insulating dielectric layer is also prepared as the surface layer of the silicon epitaxial layer described in the present application.

[0012] Beneficial effects of the present application: Based on the existing SGTMOSFET structure, the present application uses multiple trenching and etching technologies to achieve multi-level trenches, and realizes a deep-implanted, semi-shielded, isolated ion implantation layer at the bottom of the trench, thereby reducing the chip area while achieving excellent on-resistance and current-carrying capacity, and can improve the over-current stability and voltage-resistant aging reliability in medium-voltage 200V to 300V products. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0014] Figure 1 A partial structural schematic diagram of a multi-level trench semi-buried shielded SGTMOSFET device described in an embodiment provided in the present application.

[0015] Figure 2 A partial structural schematic diagram of a multi-level trench semi-buried shielded SGTMOSFET device described in an embodiment provided in the present application.

[0016] Figure 3 A partial structural schematic diagram of a multi-level trench semi-buried shielded SGTMOSFET device described in an embodiment provided in the present application.

[0017] Figure 4 A partial structural schematic diagram of a multi-level trench semi-buried shielded SGTMOSFET device described in an embodiment provided in the present application.

[0018] Figure 5 A schematic diagram of the overall structure of a multi-level trench semi-buried shielded SGTMOSFET device described in an embodiment provided in the present application.

[0019] Figure 6 It is a schematic diagram of the overall structure of an existing SGTMOSFET device in the background technology. DETAILED DESCRIPTION

[0020] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the drawings in the specification.

[0021] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0022] Secondly, the present application is described in detail with reference to the schematic diagram. When describing the embodiments of the present application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0023] Secondly, the "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that can be included in at least one implementation of the present application. The "in one embodiment" that appears in different places in this specification does not refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments.

[0024] Example 1

[0025] Reference Figure 1-5 An embodiment of the present application provides a multi-level trench semi-buried shielded SGTMOSFET device, including a silicon substrate, a silicon epitaxial layer prepared on the silicon substrate, and P-type ions and N-type ions on the surface of the silicon epitaxial layer, forming a P-type body region and an active region N-type ion layer, respectively.

[0026] A primary groove and a secondary groove are also opened on the silicon epitaxial layer. It should be noted that the secondary groove is opened based on the primary groove, that is, it is opened on the side wall of the primary groove, and the width of the primary groove is 1-5μm and the depth is 2-6μm. The width of the secondary groove is larger than that of the primary groove and the depth is smaller than that of the primary groove.

[0027] The side walls and bottom of the primary groove and the secondary groove are filled and etched with a silicon oxide layer, the centers of the primary groove and the secondary groove are filled and etched with a POLY layer, and the thickness of the silicon oxide layer in the primary groove is greater than the thickness of the POLY layer. An IPO layer with a thickness of 4000-8000 angstroms is left between the primary groove and the secondary groove.

[0028] The above structure divides the original grooves of equal width into multiple grooves of unequal widths, and there is a dummy structure between the upper grooves, which has the effect of improving the electric field distribution and regional current density. In addition, the design of multi-level grooves can bring about layout optimization, the cell spacing can be made smaller, and the on-resistance of the device can be optimized by increasing the number of cells under the same area.

[0029] A P+ type electric field shielding buried layer is also implanted at the bottom of the primary trench. The shielding buried layer can also improve the electric field distribution and regional current density, thereby improving device performance.

[0030] In addition, an active area trench is opened on the silicon epitaxial layer, and the depth of the active area trench is between the P-type body region and the active area N-type ion layer. A contact hole is photoetched in the active area trench, and P++ type ions are injected into the P-type body region, and the injection concentration is greater than the ion concentration of the P-type body region, and the injection depth is between the active area contact hole and the P-type body region.

[0031] A BPSG phosphorus silicon glass dielectric layer is also deposited and etched on the surface of the silicon epitaxial layer, and a metal matching with the contact hole of the active area is also deposited, photolithographically and etched on the surface of the silicon epitaxial layer.

[0032] In summary, the multi-level trench design and shielding buried layer design in the multi-level trench semi-buried shielded SGTMOSFET device provided by the present application can optimize the layout design, reduce the device area, improve the electric field distribution, optimize the regional current density, and enhance the device performance. It can also improve the overcurrent stability and the reliability of voltage aging in medium voltage 200V~300V products.

[0033] Importantly, it should be noted that the construction and arrangement of the present application shown in a plurality of different exemplary embodiments are only exemplary. Although only a few embodiments are described in detail in this disclosure, it should be readily understood by those who refer to this disclosure that many modifications are possible (e.g., the size, scale, structure, shape and ratio of various elements, and parameter values ​​(e.g., temperature, pressure, etc.), installation arrangement, use of materials, color, directional changes, etc.) without substantially departing from the novel teachings and advantages of the subject matter described in the application. For example, the element shown as integrally formed can be composed of multiple parts or elements, the position of the element can be inverted or otherwise changed, and the nature or number or position of the discrete element can be changed or changed. Therefore, all such modifications are intended to be included in the scope of the present application. The order or sequence of any process or method steps can be changed or reordered according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure of performing the function described herein, and is not only structurally equivalent but also equivalent structure. Without departing from the scope of the present application, other replacements, modifications, changes and omissions can be made in the design, operating conditions and arrangement of the exemplary embodiments. Therefore, the present application is not limited to the specific embodiments, but extends to various modifications that still fall within the scope of the appended claims.

[0034] Additionally, in order to provide a concise description of exemplary embodiments, all features of an actual embodiment (ie, those features that are not relevant to the best mode presently contemplated for carrying out the application or those that are not relevant to implementing the application) may not be described.

[0035] It will be appreciated that in the development of any actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort may be complex and time-consuming, but will be a routine task of design, fabrication, and production for those of ordinary skill having the benefit of this disclosure without undue experimentation.

[0036] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application, which should be included in the scope of the claims of the present application.

Claims

1. A multi-level trench semi-buried shielded SGTMOSFET device, characterized in that: include, A substrate, on which a silicon epitaxial layer is prepared, wherein a P-type body region and an active-area N-type ion layer are formed on the surface of the silicon epitaxial layer, and the depth of the active-area N-type ion layer is greater than that of the P-type body region; An active area trench, wherein the active area trench is opened on the silicon epitaxial layer and has a depth between the P-type body region and the active area N-type ion layer; A primary trench, wherein the primary trench is opened on the silicon epitaxial layer; A secondary trench is opened on the silicon epitaxial layer, the secondary trench is opened along the side wall of the primary trench, and the width of the secondary trench is greater than that of the primary trench and the depth is less than that of the primary trench.

2. The multi-level trench semi-buried shielded SGTMOSFET device according to claim 1, characterized in that: The primary groove has a width of 1-5 μm and a depth of 2-6 μm.

3. The multi-level trench semi-buried shielded SGTMOSFET device according to claim 2, characterized in that: A P+ type electric field shielding buried layer is implanted into the sidewall and bottom of the primary trench.

4. The multi-level trench semi-buried shielded SGTMOSFET device according to claim 2 or 3, characterized in that: The sidewall and the bottom of the primary trench are filled with or etched with a silicon oxide layer, the first-level trench is filled with or etched with a POLY layer, and the thickness of the silicon oxide layer is greater than that of the POLY layer.

5. The multi-level trench semi-buried shielded SGTMOSFET device according to claim 4, characterized in that: The bottom and sidewalls of the secondary trench are also filled with a silicon oxide layer, a POLY layer is filled and etched in the secondary trench, and an IPO layer with a thickness of 4000-8000 angstroms is left between the primary trench and the secondary trench.

6. The multi-level trench semi-buried shielded SGTMOSFET device according to claim 5, characterized in that: A BPSG phosphorus silicon glass insulating dielectric layer is also prepared on the surface of the silicon epitaxial layer.

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