Quartz integrated ring for semiconductor etching

By designing a quartz integrated ring with outer bevel angle and inner bevel angle, the friction at the top of the needle is reduced, and particles are avoided by designing the outer arc angle and inner arc angle, the problem of powder friction during semiconductor etching is solved, achieving more efficient etching accuracy and quality.

CN222673017UActive Publication Date: 2025-03-25SUZHOU JINLINXIN SEMICON TECH CO LTD
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Patent Information

Application Number
CN202421429690.8
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-06-21
Publication Date
2025-03-25
Estimated Expiration
2034-06-21

AI Technical Summary

Technical Problem

During semiconductor etching, powder friction when the needle is pushed can affect the etching accuracy and effect and may damage the wafer surface quality.

Method used

A quartz integrated ring for semiconductor etching is designed to reduce friction on the top of the needle through the outer oblique angle of the quartz outer wall and the inner oblique angle of the quartz inner wall, and avoid fine particles through the outer arc angle and inner arc angle design to ensure the stable position of the wafer during processing.

Benefits of technology

The friction resistance during the etching process is significantly reduced, the accuracy and efficiency of etching are improved, the particle interference is avoided, the surface quality of the wafer is improved, and the quality and yield of semiconductor etching are improved.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model relates to the technical field of quartz rings, and discloses a quartz integrated ring for semiconductor etching, which comprises a quartz protection ring, a wafer bearing disc is movably inserted in the bottom side of the quartz protection ring, the bottom end of the wafer bearing disc is movably connected with a grounding bearing disc, the bottom side of the quartz protection ring is provided with a supporting groove, and the bottom end of the supporting groove is provided with a grounding bearing disc. The top end of the wafer bearing disc is inserted into the supporting groove, and a fixing hole is formed in the side wall of the grounding bearing disc. Through the outer bevel angle of the quartz outer wall and the inner bevel angle of the quartz inner wall, friction with the top of a needle head can be remarkably reduced, so that resistance is greatly reduced, etching operation is smoother and more efficient, and through the unique design of the outer arc angle and the inner arc angle, sufficient space is provided for avoiding extremely fine particles in the etching process; interference and obstruction of the particles to the etching process are effectively avoided, and the existence of the convex gear ring powerfully ensures that the wafer body is always in a stable position in the whole processing process.
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Description

Technical Field

[0001] The utility model relates to the technical field of quartz rings, in particular to an integrated quartz ring for semiconductor etching. Background Art

[0002] In the production of semiconductor memory devices, the accuracy of the etching process is ensured to improve storage capacity and data reading and writing speed. In the production process of optoelectronic semiconductor devices, the uniformity and consistency of etching are guaranteed, the optical and electrical properties of the devices are optimized, and the high quality and high performance of the products are guaranteed. In short, quartz integrated rings for semiconductor etching have wide and important applications in the manufacture of various semiconductor devices, and are an important support for improving the quality and performance of semiconductor products.

[0003] During the specific etching process, the etching needle methodically carries out fine processing operations on the side wall of the wafer along the side wall of the quartz ring. During this process, the wafer powder ground off between the needle and the side wall of the quartz ring will inevitably be squeezed in the narrow space between the quartz ring and the wafer. Moreover, as the needle continues to push forward, this squeezing situation is very likely to cause mutual friction between the wafer powders, which will not only affect the accuracy and effect of etching, but also may cause a certain degree of damage to the surface quality of the wafer, thereby bringing potential adverse effects to the entire semiconductor etching process. Utility Model Content

[0004] The utility model aims to solve the problem that powder friction may be caused by needle pushing, which affects the etching accuracy and effect as well as the surface quality of the wafer body. The utility model provides a quartz integrated ring for semiconductor etching.

[0005] In order to achieve the above-mentioned purpose, the utility model specifically adopts the following technical solutions:

[0006] A quartz integrated ring for semiconductor etching, comprising a quartz protection ring, a wafer carrier plate movably inserted into the bottom side of the quartz protection ring, a ground carrier plate movably connected to the bottom end of the wafer carrier plate, a support groove is arranged on the bottom side of the quartz protection ring, the top end of the wafer carrier plate is inserted into the support groove, a fixing hole is arranged on the side wall of the ground carrier plate, the quartz protection ring comprises a quartz outer wall and a quartz inner wall, the support groove is arranged at the bottom of the quartz outer wall, and the quartz inner wall is arranged On the inner side of the quartz outer wall, the quartz outer wall includes an outer bevel angle and an outer arc angle, the outer bevel angle is located at the upper half angle of the outer side of the quartz protection ring, and the outer arc angle is located at the lower end of the outer side of the quartz protection ring, the quartz inner wall includes an inner bevel angle and an inner arc angle, the inner bevel angle is located at the upper end of the inner ring of the quartz protection ring, and the inner arc angle is located at the lower end of the inner ring of the quartz protection ring, the grounding carrier plate includes a convex gear ring, and the convex gear ring is located on the top side of the grounding carrier plate and is arranged in multiple layers from outside to inside.

[0007] Furthermore, the quartz outer wall also includes an outer ring wall, the outer bevel is located at the upper end of the outer ring wall, the outer arc angle is located at the lower end of the outer ring wall, and the needle head can etch the wafer body along the side walls of the outer ring wall and the inner ring wall respectively;

[0008] Furthermore, the quartz inner wall also includes an inner ring wall, the inner bevel is located at the upper end of the inner ring wall, the inner arc angle is located at the lower end of the inner ring wall, the outer bevel and the inner bevel are located at the upper end of the etching needle, and offsetting the angles of the outer ring wall and the inner ring wall can reduce the friction between the top of the needle.

[0009] Furthermore, the wafer carrier plate includes a supporting plate and a positioning column, the top side of the supporting plate is movably connected to the bottom side of the quartz protection ring, the top end of the positioning column is inserted into the supporting groove, the bottom of the positioning column is movably connected to the top side of the grounded carrier plate, and the supporting groove set on the bottom side of the quartz protection ring can be sleeved on the top of the wafer carrier plate, that is, the supporting groove is sleeved on the positioning column.

[0010] Furthermore, the middle part of the side wall of the positioning column is connected to the middle part of the side wall of the supporting plate, and the supporting groove arranged on the bottom side of the quartz protection ring can be sleeved on the top of the wafer supporting plate, that is, the supporting groove is sleeved on the positioning column.

[0011] Furthermore, the grounded carrier plate also includes a carrier and a connecting plate. The bottom end of the wafer carrier plate is movably connected to the top side of the carrier. The fixing hole is arranged on the side wall of the carrier. Wafers of different sizes placed on the top side of the carrier will be restricted by the outer convex gear ring and will not be pushed out of the carrier during processing.

[0012] Furthermore, the top of the connecting plate is fixedly connected to the bottom of the carrier, and the convex gear ring is arranged on the top side of the carrier. The fixing hole can assist the carrier and the connecting plate to realize the grounding connection of the entire integrated ring and the etching equipment, which is used to eliminate static electricity and stabilize the electric field.

[0013] Compared with the prior art, the utility model provides a quartz integrated ring for semiconductor etching, which has the following beneficial effects:

[0014] The integrated quartz ring for semiconductor etching can significantly reduce the friction with the top of the needle through the outer bevel of the quartz outer wall and the inner bevel of the quartz inner wall, thereby greatly reducing the resistance and making the etching operation smoother and more efficient. The unique design of the outer arc angle and the inner arc angle provides sufficient space for avoiding extremely fine particles during the etching process, effectively avoiding the interference and obstruction of the particles to the etching process. Furthermore, the presence of the convex gear ring effectively ensures that the wafer body is always in a stable position during the entire processing process and will not be pushed out or displaced, thereby ensuring the precision and accuracy of the etching process and greatly improving the quality and yield of semiconductor etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the overall structural connection of this utility;

[0016] Figure 2 This is a schematic diagram of the overall structure of this utility model;

[0017] Figure 3 This is a diagram showing the structure of the practical quartz protection ring;

[0018] Figure 4 The structure cross-section diagram of the quartz outer wall and the quartz inner wall of the practical quartz protection ring;

[0019] Figure 5 This is a structural diagram of the wafer carrier of the present invention;

[0020] Figure 6 This is a structural diagram of the practical grounding bearing plate.

[0021] In the figure: 1. quartz protection ring; 11. quartz outer wall; 1101. outer bevel; 1102. outer ring wall; 1103. outer arc angle; 12. quartz inner wall; 1201. inner bevel; 1202. inner ring wall; 1203. inner arc angle; 2. wafer carrier plate; 21. support plate; 22. positioning column; 3. grounding carrier plate; 31. carrier body; 32. connecting plate; 33. convex gear ring; 4. support groove; 5. fixing hole. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model. Embodiment 1:

[0023] like Figure 1-Figure 6 As shown, a quartz integrated ring for semiconductor etching includes a quartz protection ring 1, a wafer carrier plate 2 is movably inserted into the bottom side of the quartz protection ring 1, a grounding carrier plate 3 is movably connected to the bottom end of the wafer carrier plate 2, a supporting groove 4 is arranged on the bottom side of the quartz protection ring 1, the top end of the wafer carrier plate 2 is inserted into the supporting groove 4, a fixing hole 5 is arranged on the side wall of the grounding carrier plate 3, the quartz protection ring 1 includes a quartz outer wall 11 and a quartz inner wall 12, the supporting groove 4 is arranged at the bottom of the quartz outer wall 11, and the quartz inner wall 12 is arranged at the bottom of the quartz outer wall 11 On the inside, the quartz outer wall 11 includes an outer bevel angle 1101 and an outer arc angle 1103, the outer bevel angle 1101 is located at the upper half of the outer side of the quartz protection ring 1, and the outer arc angle 1103 is located at the lower end of the outer side of the quartz protection ring 1, the quartz inner wall 12 includes an inner bevel angle 1201 and an inner arc angle 1203, the inner bevel angle 1201 is located at the upper end of the inner ring of the quartz protection ring 1, and the inner arc angle 1203 is located at the lower end of the inner ring of the quartz protection ring 1, the grounding support plate 3 includes a convex gear ring 33, and the convex gear ring 33 is located on the top side of the grounding support plate 3 and is arranged in multiple layers from the outside to the inside.

[0024] like Figure 1-Figure 3 As shown, the quartz outer wall 11 also includes an outer ring wall 1102, an outer bevel 1101 is located at the upper end of the outer ring wall 1102, and an outer arc angle 1103 is located at the lower end of the outer ring wall 1102. The quartz inner wall 12 also includes an inner ring wall 1202, an inner bevel 1201 is located at the upper end of the inner ring wall 1202, and an inner arc angle 1203 is located at the lower end of the inner ring wall 1202. During the etching process, the outer bevel 1101 and the inner bevel 1201 are located at the upper end of the etching needle. The angles of the outer ring wall 1102 and the inner ring wall 1202 are offset to reduce the friction between the top of the needle and reduce the resistance.

[0025] like Figure 1 and Figure 5As shown, the wafer carrier plate 2 includes a support plate 21 and a positioning column 22. The top side of the support plate 21 is movably connected to the bottom side of the quartz protection ring 1, the top of the positioning column 22 is inserted into the support groove 4, and the bottom of the positioning column 22 is movably connected to the top side of the grounded carrier plate 3. The middle part of the side wall of the positioning column 22 is connected to the middle part of the side wall of the support plate 21. The part of the needle can be used to etch the wafer body along the side walls of the outer ring wall 1102 and the inner ring wall 1202 respectively. During the etching process, the outer bevel angle 1101 and the inner bevel angle 1201 are located at the upper end of the etching needle. The angles of the outer ring wall 1102 and the inner ring wall 1202 are offset to reduce the friction between the top of the needle. Embodiment 2:

[0026] like Figure 1 and Figure 6 As shown, the grounding carrier plate 3 also includes a carrier body 31 and a connecting plate 32, the bottom end of the wafer carrier plate 2 is movably connected to the top side of the carrier body 31, the fixing hole 5 is arranged at the side wall of the carrier body 31, the top of the connecting plate 32 is fixedly connected to the bottom of the carrier body 31, and the convex gear ring 33 is arranged on the top side of the carrier body 31. The convex gear rings 33 arranged on the top side of the carrier body 31 are arranged in sequence, and the convex gear rings 33 arranged from the outside to the inside, the height of the convex gear ring 33 of the outer circle is higher than the height of the convex gear ring 33 of the inner circle, so the height of the convex gear ring 33 of the innermost circle is lower than the height of the convex gear ring 33 of the outermost circle.

[0027] Working principle: Figure 1-Figure 6 As shown, the support groove 4 arranged on the bottom side of the quartz protection ring 1 can be sleeved on the top of the wafer carrier 2, that is, the support groove 4 is sleeved on the positioning column 22, and the wafer to be processed is placed on the top side of the grounded carrier 3. According to the size of the wafer to be processed, the convex gear rings 33 are arranged in sequence on the top side of the carrier 31. The convex gear rings 33 arranged from the outside to the inside, the height of the convex gear rings 33 of the outer ring is higher than the height of the convex gear rings 33 of the inner ring, so the height of the convex gear rings 33 of the innermost ring is lower than the height of the convex gear rings 33 of the outermost ring, so wafers of different sizes placed on the top side of the carrier 31 will be restricted by the convex gear rings 33 on the outer side, and will not be pushed out of the carrier 31 during processing;

[0028] The fixing hole 5 can assist the carrier 31 and the connecting plate 32 to realize the grounding connection between the entire integrated ring and the etching equipment, which is used to eliminate static electricity and stabilize the electric field. The bottom end of the positioning column 22 is supported on the top side of the wafer body, which can support the quartz protection ring 1 to be located above the wafer body. When the needle of the etching equipment operates along the outer side of the quartz outer wall 11 and the inner side of the quartz inner wall 12, the part of the needle can respectively etch the wafer body along the side walls of the outer ring wall 1102 and the inner ring wall 1202. During the etching process, the outer bevel angle 1101 and the inner bevel angle 1201 are located at the upper end of the etching needle. The angles of the offset outer ring wall 1102 and the inner ring wall 1202 can reduce the friction between the top of the needle and reduce the resistance. The outer arc angle 1103 and the inner arc angle 1203 set at the bottom of the inner and outer circles can facilitate the avoidance of etching fine particles during the etching process.

Claims

1. A quartz integrated ring for semiconductor etching, comprising a quartz protection ring (1), characterized in that: The bottom side of the quartz protection ring (1) is movably plugged with a wafer carrier plate (2), the bottom end of the wafer carrier plate (2) is movably connected with a ground carrier plate (3), the bottom side of the quartz protection ring (1) is provided with a support groove (4), the top end of the wafer carrier plate (2) is plugged into the support groove (4), the side wall of the ground carrier plate (3) is provided with a fixing hole (5), the quartz protection ring (1) comprises a quartz outer wall (11) and a quartz inner wall (12), the support groove (4) is provided at the bottom of the quartz outer wall (11), the quartz inner wall (12) is provided on the inner side of the quartz outer wall (11), and the quartz outer wall (11) comprises an outer The quartz protective ring (1) comprises an outer bevel angle (1101) and an outer arc angle (1103), wherein the outer bevel angle (1101) is located at the upper half of the outer side of the quartz protective ring (1), and the outer arc angle (1103) is located at the lower end of the outer side of the quartz protective ring (1); the quartz inner wall (12) comprises an inner bevel angle (1201) and an inner arc angle (1203), wherein the inner bevel angle (1201) is located at the upper end of the inner ring of the quartz protective ring (1), and the inner arc angle (1203) is located at the lower end of the inner ring of the quartz protective ring (1); and the grounding carrier plate (3) comprises a convex tooth ring (33), and the convex tooth ring (33) is located on the top side of the grounding carrier plate (3) and is arranged in multiple layers from the outside to the inside.

2. The quartz integrated ring for semiconductor etching according to claim 1, characterized in that: The quartz outer wall (11) further comprises an outer annular wall (1102), the outer bevel angle (1101) is located at the upper end of the outer annular wall (1102), and the outer arc angle (1103) is located at the lower end of the outer annular wall (1102).

3. The quartz integrated ring for semiconductor etching according to claim 1, characterized in that: The quartz inner wall (12) further comprises an inner annular wall (1202), the inner bevel angle (1201) is located at the upper end of the inner annular wall (1202), and the inner arc angle (1203) is located at the lower end of the inner annular wall (1202).

4. The quartz integrated ring for semiconductor etching according to claim 1, characterized in that: The wafer carrier plate (2) comprises a support plate (21) and a positioning column (22), the top side of the support plate (21) is movably connected to the bottom side of the quartz protection ring (1), the top end of the positioning column (22) is inserted into the support groove (4), and the bottom of the positioning column (22) is movably connected to the top side of the grounded carrier plate (3).

5. The one-piece quartz ring for semiconductor etching according to claim 4, characterized in that: The middle portion of the side wall of the positioning column (22) penetrates and is connected to the middle portion of the side wall of the supporting plate (21).

6. The one-piece quartz ring for semiconductor etching according to claim 1, characterized in that: The grounded carrier plate (3) further comprises a carrier body (31) and a connecting plate (32); the bottom end of the wafer carrier plate (2) is movably connected to the top side of the carrier body (31); and the fixing hole (5) is arranged on the side wall of the carrier body (31).

7. The one-piece quartz ring for semiconductor etching according to claim 6, characterized in that: The top of the connection plate (32) is fixedly connected to the bottom of the carrier (31), and the protruding gear ring (33) is arranged on the top side of the carrier (31).