Gallium nitride power device

Abstract

The utility model provides a gallium nitride power device, which comprises a substrate, an epitaxial layer, a cap layer, a source electrode, a drain electrode and a passivation layer, and is characterized in that the source electrode and the drain electrode are arranged on the epitaxial layer at an interval; the passivation layer comprises a first passivation layer arranged on the side, away from the substrate, of the epitaxial layer and a second passivation layer arranged on the side, away from the epitaxial layer, of the first passivation layer, openings are formed in the areas, corresponding to the source electrode and the drain electrode, of the passivation layer, and the source electrode and the drain electrode are arranged in the openings respectively and make contact with the epitaxial layer; partial region of the passivation layer also serves as a cap layer, and the cap layer is separated from the source electrode and the drain electrode; wherein the stress parameter of the first passivation layer is smaller than that of the second passivation layer. Specifically, a first passivation layer with a low stress parameter is arranged between an epitaxial layer and a second passivation layer with a high stress parameter, and the first passivation layer can slowly release high stress brought by the second passivation layer to directly act on the epitaxial layer, so that the problems that the piezoelectric effect of a device is enhanced and the warping of a wafer is increased are solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a gallium nitride power device. Background Art

[0002] Gallium nitride HEMT (High Electron Mobility Transistor) devices have attracted widespread attention due to their high breakdown voltage and high turn-on speed. Compared with PGaN HEMT devices, the MIS-HEMT structure of depletion-mode GaNHEMT devices has the advantages of high gate voltage swing and low gate leakage due to the presence of the metal-semiconductor inter-insulator dielectric (gate dielectric / gate insulating dielectric layer).

[0003] High-quality gate dielectric materials are the key to achieving the above advantages. However, in existing devices, the passivation layer on the barrier layer is generally made of the same material as the high-quality gate dielectric material. The high stress problem caused by the high-quality passivation layer will lead to enhanced piezoelectric effect of the device and excessive wafer warping. Utility Model Content

[0004] The gallium nitride power device provided in the present application can solve the problems of enhanced piezoelectric effect and increased wafer warpage in existing devices using a high-stress passivation layer.

[0005] In order to solve the above technical problems, the technical solution provided by the present application is: to provide a gallium nitride power device, comprising:

[0006] substrate;

[0007] Epitaxial layer;

[0008] A source electrode and a drain electrode are spaced apart and arranged on the epitaxial layer;

[0009] A passivation layer, comprising a first passivation layer disposed on a side of the epitaxial layer away from the substrate, and a second passivation layer disposed on a side of the first passivation layer away from the epitaxial layer, wherein the passivation layer has openings in regions corresponding to the source electrode and the drain electrode, the source electrode and the drain electrode are respectively disposed in the openings and in contact with the epitaxial layer; a portion of the passivation layer also serves as a cap layer, and the cap layer is spaced from the source electrode and the drain electrode;

[0010] Wherein, the stress parameter of the second passivation layer is greater than the stress parameter of the first passivation layer.

[0011] Beneficial effects of the present application: Different from the prior art, the gallium nitride power device provided by the present application includes a substrate, an epitaxial layer, a cap layer, a source, a drain and a passivation layer, wherein the source and the drain are spaced apart and arranged on the epitaxial layer; the passivation layer includes a first passivation layer arranged on the side of the epitaxial layer away from the substrate, and a second passivation layer arranged on the side of the first passivation layer away from the epitaxial layer, wherein the passivation layer has an opening in the region corresponding to the source and the drain, and the source and the drain are respectively arranged in the opening and in contact with the epitaxial layer; a part of the passivation layer also serves as a cap layer, and the cap layer is spaced apart from the source and the drain; wherein the stress parameter of the first passivation layer is less than the stress parameter of the second passivation layer. Specifically, the present application arranges a first passivation layer with a low stress parameter between the epitaxial layer and the second passivation layer with a high stress parameter, and the first passivation layer can relieve the high stress brought by the second passivation layer and directly act on the epitaxial layer, thereby improving the problem of enhanced piezoelectric effect of the device and increased wafer warpage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1 It is a partial structural schematic diagram of a gallium nitride power device provided in the first embodiment of the present application;

[0014] Figure 2 It is a partial structural schematic diagram of a gallium nitride power device provided in the second embodiment of the present application;

[0015] Figure 3 It is a schematic flow chart of a method for preparing a gallium nitride power device provided in an embodiment of the present application;

[0016] Figure 4 for Figure 3 Schematic diagram of an intermediate product of a gallium nitride power device after step S1;

[0017] Figure 5 for Figure 3 A schematic diagram of an intermediate product of a gallium nitride power device after step S2;

[0018] Figure 6 for Figure 3 A schematic diagram of an intermediate product of a gallium nitride power device after step S3;

[0019] Figure 7 for Figure 3 A schematic diagram of an intermediate product of a gallium nitride power device after step S4;

[0020] Figure 8 for Figure 3 A schematic diagram of an intermediate product of a gallium nitride power device after step S5;

[0021] Fig. 9 for Figure 3 A schematic diagram of an intermediate product of a gallium nitride power device after step S6;

[0022] Fig.10 for Figure 3 FIG. 4 is a schematic diagram of the structure of the GaN power device after step S7.

[0023] Figure Number:

[0024] Substrate-10; base-11; transition layer-12; epitaxial layer-20; first semiconductor layer-21; second semiconductor layer-22; cap layer-30; first dielectric layer-31; second dielectric layer-32; source-40; drain-50; passivation layer-60; first passivation layer-61; second passivation layer-62; third passivation layer-63; gate-70;

[0025] Source region-B1; Drain region-B2; Cap layer region-B3;

[0026] The first intermediate dielectric layer 81; the second intermediate dielectric layer 82; and the third intermediate dielectric layer 83. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0029] The terms "first", "second" and "third" in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include at least one of the features. All directional indications (such as up, down, left, right, front, back...) in the embodiments of the present application are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. The terms "including" and "having" in the embodiments of the present application and any of their variations are intended to cover non-exclusive inclusions.

[0030] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0032] At present, high-quality SiN / SiO passivation layer dielectric materials grown by MOCVD / LPCVD on the barrier layer are usually used as gate dielectrics (capping layers). However, the high-quality SiN / SiO passivation layer grown by MOCVD / LPCVD usually has high stress. The presence of a high-stress passivation layer on the barrier layer usually leads to:

[0033] 1) The piezoelectric effect is enhanced and the 2DEG concentration in the channel increases, which requires a more negative gate voltage to turn off the channel, resulting in the Vth of the depletion-mode GaN HEMT device being less than -20V, which does not meet the cascode standard (usually the Vth of the depletion-mode GaN HEMT device is -5V to -20V);

[0034] 2) The wafer warpage increases, and the epitaxial layer may experience strain relaxation or even splitting.

[0035] To address this problem, a new gallium nitride power device is proposed. A passivation layer with low stress is provided between the epitaxial layer and the passivation layer with high stress. The passivation layer with low stress can relieve the high stress brought by the passivation layer with high stress and directly act on the epitaxial layer. In addition, the passivation layer with low stress has openings in the regions corresponding to the cap layer, the source and the drain, thereby isolating the leakage channel caused by the defects of the passivation layer with low stress, thereby achieving high gate voltage swing and low leakage while reducing the high stress problem brought by the passivation layer with high stress, thereby improving the problems of enhanced piezoelectric effect of the device and increased wafer warping.

[0036] See also Figure 1 and Figure 2 , Figure 1 It is a partial structural schematic diagram of a gallium nitride power device provided in the first embodiment of the present application; Figure 2 It is a partial structural schematic diagram of a gallium nitride power device provided in the second embodiment of the present application.

[0037] Specifically, the gallium nitride power device provided in the present application includes a substrate 10 , an epitaxial layer 20 , a cap layer 30 , a source 40 , a drain 50 , and a passivation layer 60 .

[0038] In one embodiment, the substrate 10 includes a base 11 and a transition layer 12. Silicon (Si) material or sapphire (Al) material can be used. 2 O 3 ) material is used as the substrate 11; AlGaN material is used as the transition layer 12.

[0039] In other embodiments, the substrate 10 may also only include the base 11 .

[0040] The epitaxial layer 20 includes a first semiconductor layer 21 and a second semiconductor layer 22. The first semiconductor layer 21 is disposed on one side of the substrate 10 as a buffer layer of the device, and the second semiconductor layer 22 is disposed on the side of the first semiconductor layer 21 away from the substrate 10 as a barrier layer of the device. Specifically, a heterojunction structure is formed between the first semiconductor layer 21 and the second semiconductor layer 22, and a two-dimensional electron gas (2DEG) is also formed between the first semiconductor layer 21 and the second semiconductor layer 22.

[0041] In the embodiment of the present application, the material of the first semiconductor layer 21 includes GaN; the material of the second semiconductor layer 22 includes AlGaN.

[0042] The source electrode 40 and the drain electrode 50 are disposed on the epitaxial layer 20 at intervals, and are specifically disposed on the surface of the second semiconductor layer 22 away from the first semiconductor layer 21 .

[0043] Among them, see Figure 1In the first embodiment of the gallium nitride power device provided in the present application, the passivation layer 60 includes a first passivation layer 61 arranged on the side of the epitaxial layer 20 away from the substrate 10, and a second passivation layer 62 arranged on the side of the first passivation layer 61 away from the epitaxial layer 20, wherein the passivation layer 60 has openings in the regions corresponding to the source 40 and the drain 50, and the source 40 and the drain 50 are respectively arranged in the openings and in contact with the epitaxial layer 20.

[0044] Part of the passivation layer 60 is also used as the cap layer 30 , and the cap layer 30 is spaced apart from the source electrode 40 and the drain electrode 50 .

[0045] In one embodiment, the source 40 and the drain 50 are located on opposite sides of the cap layer 30 .

[0046] Among them, the capping layer 30 serves as a gate dielectric layer, and the material of the capping layer 30 includes high-quality materials, for example, at least one of high-quality silicon oxide (SiNx) and silicon nitride (SiOx), so that the gallium nitride power device has the advantages of high gate voltage swing and low gate leakage.

[0047] The surface of the cap layer 30 facing away from the epitaxial layer 20 is also provided with a gate 70, which is spaced apart from the source 40 and the drain 50. Specifically, the gate 70, the source 40 and the drain 50 are conductive metal structures for electrical connection with an external circuit.

[0048] The stress parameter of the first passivation layer 61 is smaller than the stress parameter of the second passivation layer 62 .

[0049] Specifically, when the existing capping layer includes high-quality SiNx / SiOx material, generally, a high-quality SiNx / SiOx dielectric material is grown on the entire surface of the barrier layer, and then patterned to form the capping layer and the passivation layer, that is, the materials of the capping layer and the passivation layer include the same high-quality SiNx / SiOx dielectric material, and the high-quality SiNx / SiOx passivation layer usually has higher stress. The presence of the high-stress passivation layer on the barrier layer will lead to enhanced piezoelectric effect of the device and excessive wafer warping.

[0050] The present application sets a passivation layer 60 including a first passivation layer 61 and a second passivation layer 62, and the second passivation layer 62 is a high-quality SiNx / SiOx dielectric material, so that the device has the advantages of high gate voltage swing and low gate leakage. In order to avoid the problem of enhanced piezoelectric effect of the device and excessive wafer warping caused by the second passivation layer 62 with high stress parameters, the present application further sets a first passivation layer 61 with low stress parameters between the epitaxial layer 20 and the second passivation layer 62 with high stress parameters. The first passivation layer 61 can relieve the high stress brought by the second passivation layer 62 directly acting on the epitaxial layer 20, thereby improving the problem of enhanced piezoelectric effect of the device and increased wafer warping.

[0051] Specifically, the materials of the first passivation layer 61 and the second passivation layer 62 include at least one of silicon oxide and silicon nitride. The high-stress SiNx / SiOx medium and the low-stress SiNx / SiOx medium are specifically achieved by changing the ratio of dielectric elements or the looseness of the dielectric, etc., which is a prior art and will not be described in detail here.

[0052] In the present application, high stress refers to a stress parameter greater than 500 MPa, and low stress refers to a stress parameter of 0-500 MPa.

[0053] In the present application, factors such as refractive index and breakdown field strength also need to be considered for the high-quality second passivation layer 62 and the low-quality first passivation layer 61 .

[0054] The refractive index parameter of the first passivation layer 61 is greater than the refractive index parameter of the second passivation layer 62 ; the breakdown field strength parameter of the first passivation layer 61 is less than the breakdown field strength parameter of the second passivation layer 62 .

[0055] The refractive index parameter of the first passivation layer 61 may be greater than 2.1, and the refractive index parameter of the second passivation layer 62 may be 2.0-2.1.

[0056] The breakdown field strength parameter of the first passivation layer 61 may be 5-7 MV / cm, and the breakdown field strength parameter of the second passivation layer 62 may be greater than 7 MV / cm.

[0057] Among them, the above-mentioned refractive index parameters and breakdown field strength parameters are specifically achieved by changing the proportion of dielectric elements or the looseness of the dielectric, etc., which is the existing technology and will not be elaborated here.

[0058] In one embodiment, the openings on the passivation layer 60 include a first opening (not marked in the figure) corresponding to the source 40 and a second opening (not marked in the figure) corresponding to the drain 50; the second passivation layer 62 also wraps the side of the first passivation layer 61 at the positions corresponding to the first opening and the second opening.

[0059] Specifically, by arranging the second passivation layer 62 to cover the side surface of the first passivation layer 61 at the positions corresponding to the first opening and the second opening, lateral leakage can be reduced and metal diffusion to the low-stress first passivation layer 61 can be prevented.

[0060] In one embodiment, a portion of the second passivation layer 62 serves as the cap layer 30 , and the first passivation layer 61 has an opening (not marked) in the region corresponding to the cap layer 30 . The cap layer 30 is located in the opening and in contact with the epitaxial layer 20 .

[0061] Specifically, in the method for preparing a gallium nitride power device, after a dielectric layer with a low stress parameter is formed on the entire surface, first, openings corresponding to the source 40 region, the drain 50 region and the cap layer 30 region are etched on the dielectric layer with the low stress parameter to form a first passivation layer 61, and then a dielectric layer with a high stress parameter is formed on the entire surface by high-temperature deposition, and then, openings corresponding to the source 40 region and the drain 50 region are etched on the dielectric layer with the high stress parameter to form a second passivation layer 62, and a part of the second passivation layer 62 is used as the cap layer 30. Therefore, in the present application, the material of the cap layer 30 is the same as that of the second passivation layer 62, and since there is no low-stress dielectric material (the material forming the first passivation layer 61) between the subsequently formed source 40 and the barrier layer, between the drain 50 and the barrier layer, and between the cap layer 30 and the barrier layer, the leakage channel generated by the low-stress dielectric material can be cut off to avoid TDDB (Time dependent transient ... The depletion-mode GaN HEMT device can maintain the advantages of high voltage resistance, large gate voltage swing and low leakage.

[0062] In one embodiment, the thickness W1 of the second passivation layer 62 located on the side of the first passivation layer 61 is 0.25-1um. For example, the thickness W1 of the second passivation layer 62 located on the side of the first passivation layer 61 is 0.25um, or the thickness W1 of the second passivation layer 62 located on the side of the first passivation layer 61 is 0.5um, or the thickness W1 of the second passivation layer 62 located on the side of the first passivation layer 61 is 0.75um, or the thickness W1 of the second passivation layer 62 located on the side of the first passivation layer 61 is 1um, etc., which is not limited here, and can be specifically designed according to the thickness of the first passivation layer 61 and the thickness of the second passivation layer 62, as long as the above-mentioned effect can be achieved.

[0063] It can be understood that if the thickness W1 of the second passivation layer 62 located on the side of the first passivation layer 61 is too thin, the effect of lateral leakage and preventing metal from diffusing into the low-stress first passivation layer 61 is poor. If the thickness W1 of the second passivation layer 62 located on the side of the first passivation layer 61 is too thick, it affects the size of the ohmic contact opening of the device, and further affects the size of the device.

[0064] In one embodiment, the first passivation layer 61 has a first thickness H1, and the second passivation layer 62 has a second thickness H2; wherein the second thickness H2 refers to the thickness of the second passivation layer 62 located above the first passivation layer 61. The ratio of the first thickness H1 to the second thickness H2 is 1.2:1-5:1. For example, the ratio of the first thickness H1 to the second thickness H2 is 1.2:1; or the ratio of the first thickness H1 to the second thickness H2 is 2:1; or the ratio of the first thickness H1 to the second thickness H2 is 3:1; or the ratio of the first thickness H1 to the second thickness H2 is 4:1; or the ratio of the first thickness H1 to the second thickness H2 is 5:1, etc., which is not limited here and is designed according to actual conditions.

[0065] It can be understood that the thickness of the first passivation layer 61 cannot be too thick or too thin. If it is too thick, it will affect the device size and is not conducive to the miniaturization of the device. If it is too thin, it will lead to poor effect in slowly releasing the high stress brought by the second passivation layer 62, and it will not be able to improve the problem of enhanced piezoelectric effect of the device and increased wafer warping.

[0066] The thickness of the second passivation layer 62 cannot be too thick or too thin. If it is too thick, it will affect the device size and is not conducive to the miniaturization of the device. If it is too thin, the cap layer 30 formed simultaneously will also be too thin, affecting the advantages of high gate voltage swing and low gate leakage of the device.

[0067] In some specific embodiments, the first thickness H1 of the first passivation layer 61 is 500-1200A. For example, the first thickness H1 of the first passivation layer 61 is 500A; or the first thickness H1 of the first passivation layer 61 is 800A; or the first thickness H1 of the first passivation layer 61 is 1200A, etc.

[0068] In some specific embodiments, the second thickness H2 of the second passivation layer 62 is 100-1000A. For example, the second thickness H2 of the second passivation layer 62 is 100A; or the second thickness H2 of the second passivation layer 62 is 500A; or the second thickness H2 of the second passivation layer 62 is 1000A, etc.

[0069] Different from the prior art, the gallium nitride power device provided in the first embodiment of the present application has a first passivation layer 61 with low stress parameters arranged between the epitaxial layer 20 and the second passivation layer 62 with high stress parameters. The first passivation layer 61 can relieve the high stress brought by the second passivation layer 62 directly acting on the epitaxial layer 20, thereby improving the problems of enhanced piezoelectric effect of the device and increased wafer warping.

[0070] See also Figure 2In the second embodiment of the gallium nitride power device provided in the present application, the passivation layer 60 includes the first passivation layer 61 and the second passivation layer 62, and further includes a third passivation layer 63, and the third passivation layer 63 is arranged on the surface of the second passivation layer 62 close to the epitaxial layer 20.

[0071] It can be understood that at least a portion of the third passivation layer 63 is located between the first passivation layer 61 and the second passivation layer 62 .

[0072] The material of the third passivation layer 63 includes at least one of aluminum nitride (AlN), aluminum oxide (AlOx) and aluminum oxynitride (AlON).

[0073] Specifically, by forming the third passivation layer 63 on the surface of the second passivation layer 62 close to the epitaxial layer 20, when the first passivation layer 61 is formed and openings corresponding to the source 40 region, the drain 50 region and the gate 70 region are etched on the first passivation layer 61, the third passivation layer 63 can repair the damage caused by etching to the epitaxial layer 20, and prevent the AlGaN element in the barrier layer from diffusing outward during the subsequent high-temperature deposition of the second passivation layer 62, and at the same time alleviate the film peeling phenomenon easily caused by the large difference in stress parameters between the first passivation layer 61 and the second passivation layer 62.

[0074] In one embodiment, since the second passivation layer 62 wraps around the side of the third passivation layer 63 at the positions corresponding to the first opening and the second opening, and at least a portion of the third passivation layer 63 is disposed between the second passivation layer 62 and the first passivation layer 61, the third passivation layer 63 also wraps around the side of the first passivation layer 61 at the positions corresponding to the first opening and the second opening, so as to alleviate the stress parameter difference between the side of the first passivation layer 61 and the side of the second passivation layer 62, and avoid peeling of the side of the second passivation layer 62 from the side of the first passivation layer 61 at the first opening and the second opening.

[0075] In this embodiment, the total thickness W2 of the second passivation layer 62 and the third passivation layer located on the side of the first passivation layer 61 is 0.25-1 um.

[0076] In another embodiment, the third passivation layer 63 may also be disposed only between the upper surface of the first passivation layer 61 and the lower surface of the second passivation layer 62 , which is not limited here.

[0077] In one embodiment, the cap layer 30 includes a first dielectric layer 31 and a second dielectric layer 32, wherein the first dielectric layer 31 is disposed on a side of the epitaxial layer 20 away from the substrate 10, and the second dielectric layer 32 is located on a side of the first dielectric layer 31 away from the epitaxial layer 20; wherein the first dielectric layer 31 is made of the same material as the third passivation layer 63, and the second dielectric layer 32 is made of the same material as the second passivation layer 62.

[0078] Specifically, in the method for preparing a gallium nitride power device, after a dielectric layer with a low stress parameter is formed on the entire surface, openings corresponding to the source 40 region, the drain 50 region and the cap layer 30 region are first etched on the dielectric layer with the low stress parameter to form a first passivation layer 61, and then a low-temperature deposition is performed to form an aluminum nitride / aluminum oxide / aluminum oxynitride dielectric layer on the entire surface, and then a high-temperature deposition is performed to form a dielectric layer with a high stress parameter on the entire surface, and then openings corresponding to the source 40 region and the drain 50 region are etched on the entire surface of the aluminum nitride / aluminum oxide / aluminum oxynitride dielectric layer and on the dielectric layer with a high stress parameter, thereby forming a second passivation layer 62 and a third passivation layer 63, wherein parts of the second passivation layer 62 and the third passivation layer 63 are also used as the cap layer 30. Therefore, the second dielectric layer 32 in the cap layer 30 is made of the same material as the second passivation layer 62, the first dielectric layer 31 in the cap layer 30 is made of the same material as the third passivation layer 63, and since there is no low-stress dielectric material between the subsequently formed source 40 and the barrier layer, between the drain 50 and the barrier layer, and between the cap layer 30 and the barrier layer, the leakage channel generated by the low-stress dielectric material can be isolated.

[0079] Of course, in the second embodiment of the present application, the cap layer 30 may also only include the second dielectric layer 32 , which is not limited here.

[0080] In one embodiment, the third passivation layer 63 has a third thickness H3, and the ratio of the first thickness H1 of the first passivation layer 61, the second thickness H2 of the second passivation layer 62, and the third thickness H3 of the third passivation layer 63 is 12:10:1-50:10:1. For example, the first thickness H1: the second thickness H2: the third thickness H3 is 12:10:1; or the first thickness H1: the second thickness H2: the third thickness H3 is 20:10:1; or the first thickness H1: the second thickness H2: the third thickness H3 is 30:10:1; or the first thickness H1: the second thickness H2: the third thickness H3 is 40:10:1; or the first thickness H1: the second thickness H2: the third thickness H3 is 50:10:1, etc., which is not limited here, and the size relationship is based on the film function and the size design of the device.

[0081] Among them, the thickness of the first passivation layer 61 in the second embodiment of the present application may be the same as the thickness of the first passivation layer 61 in the first embodiment of the present application; the thickness of the second passivation layer 62 in the second embodiment of the present application may be the same as the thickness of the second passivation layer 62 in the first embodiment of the present application.

[0082] In the second embodiment of the present application, the third thickness H3 of the third passivation layer 63 is 10-100A. For example, the third thickness H3 of the third passivation layer 63 is 10A; or the third thickness H3 of the third passivation layer 63 is 40A; or the third thickness H3 of the third passivation layer 63 is 70A; or the third thickness H3 of the third passivation layer 63 is 100A, etc.

[0083] Different from the prior art, the gallium nitride power device provided in the second embodiment of the present application has a first passivation layer 61 with low stress parameters between the epitaxial layer 20 and the second passivation layer 62 with high stress parameters. The first passivation layer 61 can relieve the high stress brought by the second passivation layer 62 directly acting on the epitaxial layer 20, thereby improving the problem of enhanced piezoelectric effect of the device and increased wafer warpage. Furthermore, a third passivation layer 63 is provided between the second passivation layer 62 with high stress parameters and the first passivation layer 61 with low stress parameters. The third passivation layer 63 can repair the damage to the epitaxial layer 20 when etching the first passivation layer 61, and prevent the AlGaN element in the barrier layer from diffusing outwards when the second passivation layer 62 is subsequently deposited at high temperature, and at the same time alleviate the film peeling phenomenon easily caused by the large difference in stress parameters between the first passivation layer 61 and the second passivation layer 62.

[0084] See also Figure 3-Figure 10 , Figure 3 It is a schematic flow chart of a method for preparing a gallium nitride power device provided in an embodiment of the present application; Figure 4 for Figure 3 Schematic diagram of an intermediate product of a gallium nitride power device after step S1; Figure 5 for Figure 3 A schematic diagram of an intermediate product of a gallium nitride power device after step S2; Figure 6 for Figure 3 A schematic diagram of an intermediate product of a gallium nitride power device after step S3; Figure 7 for Figure 3 A schematic diagram of an intermediate product of a gallium nitride power device after step S4; Figure 8 for Figure 3 A schematic diagram of an intermediate product of a gallium nitride power device after step S5; Fig. 9 for Figure 3 A schematic diagram of an intermediate product of a gallium nitride power device after step S6; Fig.10 for Figure 3 FIG. 4 is a schematic diagram of the structure of the GaN power device after step S7.

[0085] The present application also provides a method for preparing a gallium nitride power device, comprising:

[0086] Step S1: providing a substrate 10 and an epitaxial layer 20 .

[0087] See Figure 4 In one embodiment, the substrate 10 includes a base 11 and a transition layer 12. Silicon (Si) material or sapphire (Al 2 O 3 ) material is used as the substrate 11; AlGaN material is used as the transition layer 12.

[0088] In other embodiments, the substrate 10 may also only include the base 11 .

[0089] The epitaxial layer 20 includes a first semiconductor layer 21 and a second semiconductor layer 22. The first semiconductor layer 21 is disposed on one side of the substrate 10 as a buffer layer of the device, and the second semiconductor layer 22 is disposed on the side of the first semiconductor layer 21 away from the substrate 10 as a barrier layer of the device. Specifically, a heterojunction structure is formed between the first semiconductor layer 21 and the second semiconductor layer 22, and a two-dimensional electron gas (2DEG) is also formed between the first semiconductor layer 21 and the second semiconductor layer 22.

[0090] In the embodiment of the present application, the material of the first semiconductor layer 21 includes GaN; the material of the second semiconductor layer 22 includes AlGaN.

[0091] The epitaxial layer 20 is also preset with a source region B1 , a drain region B2 and a cap layer region B3 .

[0092] Step S2 : depositing a first intermediate dielectric layer 81 having a low stress parameter on the surface of the epitaxial layer 20 facing away from the substrate 10 .

[0093] See Figure 5 , wherein the first intermediate dielectric layer 81 can be formed by MOCVD / LPCVD / PECVD or other methods.

[0094] The material of the first intermediate dielectric layer 81 includes at least one of silicon oxide and silicon nitride.

[0095] The stress parameter of the first intermediate dielectric layer 81 is 0-500 MPa, the refractive index parameter of the first intermediate dielectric layer 81 may be greater than 2.1, and the through field strength parameter of the first intermediate dielectric layer 81 may be 5-7 MV / cm.

[0096] The thickness of the first intermediate dielectric layer 81 may be 500-1200 Å.

[0097] Step S3 : patterning the first intermediate dielectric layer 81 by using a photoresist to form openings corresponding to the source region B1 , the drain region B2 , and the cap layer region B3 on the first intermediate dielectric layer 81 to form a first passivation layer 61 .

[0098] See Figure 6Specifically, the remaining area of ​​the first intermediate dielectric layer 81 serves as the first passivation layer 61 .

[0099] Step S4: After removing the remaining photoresist, a second intermediate dielectric layer 82 is formed on the entire surface.

[0100] See Figure 7 , wherein after step S3 , a second intermediate dielectric layer 82 may be formed by low temperature deposition using a PEALD method.

[0101] The material of the second intermediate dielectric layer 82 includes at least one of aluminum nitride (AlN), aluminum oxide (AlOx) and aluminum oxynitride (AlON).

[0102] The thickness of the second intermediate dielectric layer 82 may be 10-100 Å.

[0103] Step S5 : depositing a third intermediate dielectric layer 83 having a high stress parameter on the surface of the second intermediate dielectric layer 82 facing away from the substrate 10 .

[0104] See Figure 8 , wherein the third intermediate dielectric layer 83 can be formed by MOCVD / LPCVD / PECVD or other methods.

[0105] The material of the third intermediate dielectric layer 83 includes at least one of silicon oxide and silicon nitride.

[0106] The stress parameter of the third intermediate dielectric layer 83 is greater than 500 MPa, the refractive index parameter of the third intermediate dielectric layer 83 may be 2.0-2.1, and the through field strength parameter of the third intermediate dielectric layer 83 may be greater than 7 MV / cm.

[0107] The thickness of the third intermediate dielectric layer 83 may be 10-100 Å.

[0108] Step S6: patterning the second intermediate dielectric layer 82 and the third intermediate dielectric layer 83 using photoresist to form openings corresponding to the source region B1 and the drain region B2 on the second intermediate dielectric layer 82 and the third intermediate dielectric layer 83 to form the second passivation layer 62 and the third passivation layer 63 .

[0109] See Fig. 9 , a portion of the third passivation layer 63 corresponding to the cap layer region B3 serves as the first dielectric layer 31 in the cap layer 30 .

[0110] The portion of the second passivation layer 62 corresponding to the cap layer region B3 serves as the second dielectric layer 32 in the cap layer 30 .

[0111] Specifically, in the preparation method provided by the present application, by forming a first passivation layer 61 with low stress parameters between the epitaxial layer 20 and the second passivation layer 62 with high stress parameters, the first passivation layer 61 can release the high stress brought by the second passivation layer 62 directly on the epitaxial layer 20, thereby improving the problem of enhanced piezoelectric effect of the device and increased wafer warpage. Furthermore, a third passivation layer 63 is formed between the second passivation layer 62 with high stress parameters and the first passivation layer 61 with low stress parameters. The third passivation layer 63 can repair the damage to the epitaxial layer 20 when etching the first passivation layer 61, and prevent the AlGaN element in the barrier layer from diffusing outward when the third intermediate dielectric layer 83 is deposited at high temperature, and at the same time alleviate the film peeling phenomenon that is easily caused by the large difference in stress parameters between the first passivation layer 61 and the second passivation layer 62. In addition, the first intermediate dielectric layer 81 with low stress has openings in the regions corresponding to the cap layer 30, the source 40 and the drain 50, thereby isolating the leakage channel caused by the defects of the first intermediate dielectric layer 81 with low stress, thereby achieving high gate voltage swing and low leakage while reducing the high stress problem caused by the passivation layer 60 with high stress, thereby improving the problems of enhanced piezoelectric effect of the device and increased wafer warping.

[0112] In one embodiment, when the second intermediate dielectric layer 82 and the third intermediate dielectric layer 83 are patterned using photoresist, the opening size of the source region B1 and the drain region B2 is smaller than the opening size of the source region B1 and the drain region B2 when the first intermediate dielectric layer 81 is patterned using photoresist.

[0113] In this way, at the openings corresponding to the source 40 area and the drain 50 area, the third passivation layer 63 is formed to wrap the side of the first passivation layer 61, and the second passivation layer 62 is formed to wrap the side of the third passivation layer 63, so as to alleviate the stress parameter difference between the side of the first passivation layer 61 and the side of the second passivation layer 62 at the openings corresponding to the source area B1 and the drain area B2, and avoid the side of the second passivation layer 62 peeling on the side of the first passivation layer 61.

[0114] Step S7 : forming a source 40 , a drain 50 and a gate 70 on the source region B1 , the drain region B2 and the cap layer 30 , respectively.

[0115] See Fig.10 The gate 70, the source 40 and the drain 50 are conductive metal structures for electrically connecting to an external circuit.

[0116] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gallium nitride power device, characterized in that: include: substrate; Epitaxial layer; A source electrode and a drain electrode are spaced apart and arranged on the epitaxial layer; A passivation layer, comprising a first passivation layer disposed on a side of the epitaxial layer away from the substrate, and a second passivation layer disposed on a side of the first passivation layer away from the epitaxial layer, wherein the passivation layer has openings in regions corresponding to the source electrode and the drain electrode, the source electrode and the drain electrode are respectively disposed in the openings and in contact with the epitaxial layer; a portion of the passivation layer also serves as a cap layer, and the cap layer is spaced from the source electrode and the drain electrode; Wherein, the stress parameter of the first passivation layer is smaller than the stress parameter of the second passivation layer.

2. The gallium nitride power device according to claim 1, characterized in that: The openings include a first opening corresponding to the source electrode and a second opening corresponding to the drain electrode; the second passivation layer also wraps around the side surfaces of the first passivation layer at positions corresponding to the first opening and the second opening.

3. The gallium nitride power device according to claim 2, characterized in that: The thickness of the second passivation layer located on the side of the first passivation layer is 0.25-1 um.

4. The gallium nitride power device according to claim 1, characterized in that: A partial area of ​​the second passivation layer serves as the cap layer, and the first passivation layer has an opening in an area corresponding to the cap layer. The cap layer is located in the opening and in contact with the epitaxial layer.

5. The gallium nitride power device according to any one of claims 1 to 4, characterized in that: The first passivation layer has a first thickness, and the second passivation layer has a second thickness; Wherein, the ratio of the first thickness to the second thickness is 1.2:1-5:1; Among them, the first thickness is 500-1200A; the second thickness is 100-1000A.

6. The gallium nitride power device according to any one of claims 1 to 4, characterized in that: The passivation layer further includes a third passivation layer, and the third passivation layer is disposed on a surface of the second passivation layer close to the epitaxial layer.

7. The gallium nitride power device according to claim 2 or 3, characterized in that: The passivation layer further includes a third passivation layer, and the third passivation layer is arranged on a surface of the second passivation layer close to the epitaxial layer; The third passivation layer also wraps around the side surfaces of the first passivation layer at positions corresponding to the first opening and the second opening; and the second passivation layer also wraps around the side surfaces of the third passivation layer at positions corresponding to the first opening and the second opening.

8. The gallium nitride power device according to claim 6, characterized in that: The cap layer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is arranged on a side of the epitaxial layer away from the substrate, and the second dielectric layer is arranged on a side of the first dielectric layer away from the epitaxial layer; The first dielectric layer is made of the same material as the third passivation layer, and the second dielectric layer is made of the same material as the second passivation layer.

9. The gallium nitride power device according to claim 6, characterized in that: The first passivation layer has a first thickness, the second passivation layer has a second thickness, and the third passivation layer has a third thickness; Wherein, the ratio of the first thickness, the second thickness and the third thickness is 12:10:1-50:10:1; Among them, the first thickness is 500-1200A; the second thickness is 100-1000A; and the third thickness is 10-100A.

10. The gallium nitride power device according to claim 1, characterized in that: The material of the first passivation layer and the second passivation layer includes at least one of silicon oxide and silicon nitride.

11. The gallium nitride power device according to claim 1, characterized in that: The refractive index parameter of the first passivation layer is greater than the refractive index parameter of the second passivation layer; and the breakdown field strength parameter of the first passivation layer is less than the breakdown field strength parameter of the second passivation layer.

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