Electronic device

Abstract

The utility model relates to an electronic device. An apparatus comprising: a substrate comprising a first surface opposite a second surface and a plurality of sidewalls extending from the first surface to the second surface; a through silicon via extending from the second surface of the substrate to the first surface of the substrate; a transparent layer on the first surface of the substrate, the transparent layer including an exposed surface and a plurality of sidewalls extending from the exposed surface to the first surface of the substrate; a solder resist layer on each of the plurality of sidewalls of the substrate and the second surface, and coupled to a first portion of each of the plurality of sidewalls of the transparent layer; a molding material layer covering the solder resist layer and a second portion of each of the plurality of sidewalls of the transparent layer; a first plurality of solder balls coupled to the substrate; and a second plurality of solder balls coupled to respective ones of the first plurality of solder balls.

Description

Technical Field

[0001] The present disclosure relates to a device having a light shielding material, and more particularly, to a light shielding package for an optical sensing device. Background Art

[0002] An optical sensor package is a device that can convert light into an electronic signal. Typically, an optical sensor package is a cavity-type package having a glass layer on a bismaleimide triazine (BT) substrate and a cavity or space between the glass layer and the semiconductor chip on the BT substrate. In operation, light entering the optical sensor package through the glass layer is detected by the semiconductor chip, while light directed toward the BT substrate on the side of the cavity is prevented from entering the cavity and being detected by the semiconductor chip. This reduces light interference, thereby optimizing the performance of the optical sensor.

[0003] However, known optical sensor packages have key disadvantages. For example, the presence of a cavity in the package results in the package having a larger size, which is contrary to the general market trend towards smaller electronic devices. In other words, in modern electronic devices, space is at a premium, which makes larger packages significantly less preferred. In some products, a low profile optical sensor package has the form factor of the electronic device, so a larger package may not be available. Utility Model Content

[0004] The present disclosure relates to an optical sensor package having a light-shielding material covering five surfaces. More specifically, the optical sensor package includes a transparent layer on a substrate layer, wherein a sensor element is located between the transparent layer and the substrate layer. Although the outer surface of the transparent layer remains uncovered, each of the other five surfaces of the optical sensor package is covered with a layer of light-shielding material. The transparent layer can be glass. The light-shielding material can include a solder mask and a molding material. The present disclosure also includes a first plurality of solder balls located on the substrate layer and a second plurality of solder balls coupled to the first plurality of solder balls.

[0005] According to one aspect of the present disclosure, a device is provided, comprising: a substrate, the substrate comprising a first surface opposite to a second surface and a plurality of sidewalls extending from the first surface to the second surface; a through-silicon via, the through-silicon via extending from the second surface of the substrate to the first surface of the substrate; a transparent layer, located on the first surface of the substrate, the transparent layer comprising an exposed surface and a plurality of sidewalls extending from the exposed surface to the first surface of the substrate; a solder resist layer, located on each of the plurality of sidewalls of the substrate and on the second surface, and coupled to a first portion of each of the plurality of sidewalls of the transparent layer; a molding material layer, the molding material layer covering the solder resist layer and a second portion of each of the plurality of sidewalls of the transparent layer; a first plurality of solder balls coupled to the substrate; and a second plurality of solder balls coupled to respective solder balls of the first plurality of solder balls.

[0006] According to another aspect of the present disclosure, a device is provided, comprising: a substrate, the substrate comprising a first surface opposite to a second surface; a transparent layer, the transparent layer coupled to the first surface of the substrate; a first plurality of solder balls, the first plurality of solder balls coupled to the second surface of the substrate, each of the first plurality of solder balls having a flat surface; a molding material layer, the molding material layer coupled to the second surface of the substrate, the molding material layer having an outer side surface coplanar with the flat surface of each of the first plurality of solder balls; and a second plurality of solder balls, each of the second plurality of solder balls coupled to the molding material layer and one of the first plurality of solder balls.

[0007] In some embodiments, the device may be an optical sensor package.

[0008] The light shielding material layer on the side wall of the optical sensor package prevents light from entering the optical sensor package through the side wall of the transparent layer and preventing the light from being detected by the sensor element. In addition, the light shielding material layer on the surface of the optical sensor package opposite to the uncovered surface prevents light from passing through the substrate layer and reflecting toward the sensor element. When the sensor element detects light from the side wall or light reflected through the substrate layer, unnecessary signal noise will be generated, which will affect the performance of the optical sensor package.

[0009] The present disclosure overcomes the defects of the prior art. Since the sidewalls of the transparent layer or glass layer are covered by the light shielding material layer, the cavity within the package can be eliminated. Therefore, the optical sensor package of the present disclosure can maintain a small size while preventing light from entering through the sidewalls and substrate layer of the optical sensor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to better understand the present disclosure, one or more embodiments will now be described by way of example only with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals identify similar elements or operations. In some figures, the structures are drawn completely to scale. In other figures, the sizes and relative positions of the elements in the accompanying drawings are not necessarily drawn to scale. For example, the sizes, shapes and angles of the various elements may be enlarged and positioned in the drawings to improve the readability of the accompanying drawings.

[0011] Figure 1 is a cross-sectional view of an optical sensor package having molding material layers covering five sides.

[0012] Figure 2A-2G Yes Assembly Figure 1 A cross-sectional view of an embodiment of a method for optical sensor packaging. DETAILED DESCRIPTION

[0013] Figure 1 An electronic device 100 is shown, which may be an optical sensor package, including a substrate layer 102 having a first surface 102a and a second surface 102b. A transparent layer 104 having a first surface 104a and a second surface 104b is attached to the substrate layer 102 by a bonding layer 108. A sensor element 106 may extend into the bonding layer 108 or may be within the substrate layer 102. In some embodiments, a portion of the sensor element 106 is located between the second surface 102b of the substrate layer 102 and the first surface 104a of the transparent layer 104.

[0014] A plurality of through silicon vias (TSVs) 110 extend from a first surface 102a of the substrate layer 102 to a second surface 102b. A solder resist layer 112 covers the first surface 102a of the substrate layer 102 and a portion of a first sidewall 100L and a second sidewall 100R of the electronic device 100. A molding material layer 114 covers the solder resist layer 112 on the first surface 102a of the substrate layer 102. The molding material layer 114 also covers the first sidewall 100L and the second sidewall 100R of the electronic device 100. Although not shown in the cross-sectional view, all four lateral sidewalls of the electronic device 100 are covered by the molding material layer 114. The four lateral sidewalls include the first sidewall 100L and the second sidewall 100R.

[0015] The substrate layer 102 extends from the first surface 102a to the second surface 102b in a first direction. The substrate layer 102 extends from the first sidewall 102L to the second sidewall 102R in a second direction, the second direction being transverse to the first direction. The substrate layer 102 may be silicon.

[0016] The transparent layer 104 extends from the first surface 104a to the second surface 104b in the first direction. The transparent layer 104 extends from the first side wall 104L to the second side wall 104R in the second direction. The first side wall 104L includes a first portion 104La and a second portion 104Lb that are not coplanar. The second side wall 104R includes a first portion 104Ra and a second portion 104Rb that are not coplanar. The distance between the first portion 104La of the first side wall 104L and the first portion 104Ra of the second side wall 104R is less than the distance between the second portion 104Lb of the first side wall 104L and the second portion 104Rb of the second side wall 104R. The transparent layer 104 may be glass.

[0017] In some embodiments, the sensor element 106 may be used for light sensing or image sensing.

[0018] TSV 110 extends through substrate layer 102. Figure 1 Only two TSVs 110 are shown in the figure, but embodiments may include more or fewer TSVs 110. According to an embodiment, each TSV 110 includes a first inner sidewall 110L and a second inner sidewall 110R. The first inner sidewall 110L and the second inner sidewall 110R may be the same surface, for example, when the shape of each TSV is cylindrical. Each TSV 110 includes an end surface 110b that is closest to or located at the second surface 102b of the substrate layer.

[0019] The dielectric layer 116 (which may be an oxide layer) covers the first inner sidewall 110L and the second inner sidewall 110R of each TSV 110. The dielectric layer 116 covers the first surface 102a of the substrate layer 102. The dielectric layer 116 may extend between the plurality of TSVs 110. According to an embodiment, the dielectric layer 116 completely covers the first surface 102a of the substrate layer 102 and the inner sidewalls 110R and 110L of each TSV 110. The dielectric layer 116 may not cover the end surface 110b of each TSV 110.

[0020] A redistribution layer 118 (which includes conductive and dielectric components) lines the inner sidewalls 110L and 110R of each TSV 110. The redistribution layer 118 also covers the end surface 110b of each TSV 110. In some embodiments, the redistribution layer 118 completely covers the end surface 110b. The redistribution layer 118 extends onto the dielectric layer 116 covering the first surface 102a of the substrate layer 102, but only partially covers the dielectric layer 116. That is, the redistribution layer 118 does not extend between adjacent TSVs 110. Multiple portions of the dielectric layer 116 between adjacent TSVs 110 remain uncovered by the redistribution layer 118, thereby forming a plurality of gaps 120 in the redistribution layer 118. Although Figure 1 10 , two gaps 120 are shown, but embodiments may include more or fewer gaps 120. The redistribution layer 118 includes a contact region 118c that covers the first surface 102a of the substrate layer 102. The contact region 118c may belong to a portion of the redistribution layer 116 that also lines the inner sidewalls 110L and 110R of the TSV 110. Alternatively, the contact region 118c may not belong to a portion of the redistribution layer 118 that lines the inner sidewalls 110L and 110R of the TSV 110. That is, in the redistribution layer 118, the contact region 118c may be surrounded by the gap 120 so that the contact region 118c is not in physical contact with the TSV 110.

[0021] The redistribution layer 118 does not extend to the sidewalls 100L and 100R of the electronic device 100. That is, the first sidewall 118L and the second sidewall 118R of the redistribution layer 118 are not coplanar with the first sidewall 102L and the second sidewall 102R of the substrate layer 102, respectively.

[0022] A first plurality of solder balls 124 are coupled to the contact region 118c. Each solder ball in the first plurality of solder balls 124 includes a planar surface 124a that may be parallel to the contact region 118c.

[0023] A plurality of contacts 122, which include conductive features, are embedded or otherwise formed in the bonding layer 108 and are coplanar with the second surface 102b of the substrate layer 102. The contacts 122 are coupled to the redistribution layer 118 on the inner surface of the TSVs 110. The contacts 122 may be wider than each TSV 110 in the second direction.

[0024] The solder resist layer 112 may completely cover the first surface 102a of the substrate layer 102. The solder resist layer 112 prevents light from passing through the substrate layer 102 and reflecting toward the sensor element 106 to generate signal noise. The solder resist layer 112 may partially fill the TSVs 110. Each TSV 110 is at least partially filled with air or includes an unfilled gap.

[0025] The solder resist layer 112 includes a first side wall 112L having an inner surface 112La and an outer surface 112Lb. The inner surface 112La is coplanar with a first portion 104La of the first side wall 104L of the transparent layer 104. The outer surface 112Lb is coplanar with a second portion 104Lb of the first side wall 104L of the transparent layer 104. The solder resist layer 112 includes a second side wall 112R having an inner surface 112Ra and an outer surface 112Rb. The inner surface 112Ra is coplanar with a first portion 104Ra of the second side wall 104R of the transparent layer 104. The outer surface 112Rb is coplanar with a second portion 104Rb of the second side wall 104R of the transparent layer 104. The first side wall 112L covers the entire first side wall 102L of the substrate layer 102 and a portion of the first side wall 104L of the transparent layer 104. The second sidewall 112R covers the entire second sidewall 102R of the substrate layer 102 and a portion of the second sidewall 104R of the transparent layer 104 .

[0026] The molding material layer 114 covers five surfaces of the electronic device 100. That is, the molding material layer 114 covers each side wall of the electronic device 100, including the first side wall 100L and the second side wall 100R. The first side wall 114L of the molding material layer 114 covers the first side wall 112L of the solder resist layer 112 and the second portion 104Lb of the first side wall 104L of the transparent layer 104. The second side wall 114R of the molding material layer 114 covers the second side wall 112R of the solder resist layer 112 and the second portion 104Rb of the second side wall 104R of the transparent layer 104. The thickness of the first side wall 114L of the molding material layer 114 may be about 200 microns.

[0027] The first region 114c of the molding material layer 114 covers the solder resist layer 112. The first outer surface 114a of the first region 114c of the molding material layer 114 is coplanar with the planar surfaces 124a of the first plurality of solder balls 124. The thickness of the first region 114c of the molding material layer 114 may be about 100 microns.

[0028] The second plurality of solder balls 126 are coupled to the first plurality of solder balls 124. The second plurality of solder balls 126 include a first rounded surface 126a and a second flat surface 126b. The second surface 126b of the second plurality of solder balls 126 is coupled to the flat surface 124a of the first plurality of solder balls 124. The second surface 126b of the second plurality of solder balls 126 has a circumference greater than the circumference of the flat surface 124a of the first plurality of solder balls 124. Portions of the second surface 126b of the second plurality of solder balls 126 are located on the first surface 114a of the first region 114c of the molding material layer 114.

[0029] Figure 2 is the assembly Figure 1 The method of the electronic device 100. Figure 2AThe electronic device 100 is started from the electronic device 100. The electronic device 100 includes: a substrate layer 102 having a first surface 102a and a second surface 102b and a first side wall 102L and a second side wall 102R; a transparent layer 104 having a first surface 104a and a second surface 104b and a first side wall 104L and a second side wall 104R; a bonding layer 108 located between the second surface 102b of the substrate layer 102 and the first surface 104a of the transparent layer 104; a plurality of sensor elements 106 formed in the bonding layer 108, the plurality of sensor elements 106 is adjacent to the second surface 102b of the substrate layer 102; a plurality of contacts 122, which include conductive components and are formed in the bonding layer 108, the contacts 122 are adjacent to the second surface 102b of the substrate layer 102 and are coplanar with the plurality of sensor elements 106; and a first carrier layer 128 located on the second surface 104b of the transparent layer 104, the first carrier layer 128 may include glass and may provide support for the electronic device 100 during the manufacturing process and reduce the possibility of warping of the transparent layer 104.

[0030] The first sidewall 102L of the substrate layer 102 is coplanar with the first sidewall 104L of the transparent layer 104 . The second sidewall 102R of the substrate layer 102 is coplanar with the second sidewall 104R of the transparent layer 104 .

[0031] The substrate layer 102 may be silicon and may have a thickness in the range of 50 to 200 microns. The transparent layer 104 may be glass and may have a thickness in the range of 100 to 500 microns.

[0032] The separation line 130 demarcates the distinction between two dies (a first die 132 and a second die 134) that will be separated in a subsequent singulation step. The separation line 130 extends through the substrate layer 102, the adhesive layer 108, the transparent layer 104, and the first carrier layer 128 in a first direction.

[0033] The first die 132 includes at least two contacts 122, although Figure 2A Only a portion of the first die 132 and a portion of the second die 134 are included in Figure 2A The second die 134 includes at least two contacts 122. Each contact 122 is coplanar with each of the other contacts 122, and each contact 122 is coplanar with the sensor element 106 along a second direction transverse to the first direction. Two contacts 122 are located between each group of adjacent sensor elements 106. Although Figure 2A Two dies are included, namely a first die 132 and a second die 134 , but embodiments may include more dies.

[0034] refer to Figure 2B, a plurality of TSVs 110 are formed in the substrate layer 102 by a process such as etching. Each TSV 110 extends from the first surface 102a of the substrate layer 102 to the second surface 102b along the first direction. Each TSV 110 is formed to be in a straight line with each contact 122 along the first direction, and an end surface 110b of each TSV 110 contacts the corresponding contact 122. Although Figure 2B Two TSVs 110 are included, but embodiments may include more TSVs 110 .

[0035] A dielectric layer 116 (which may be an oxide layer) is formed on the first inner sidewall 110L and the second inner sidewall 110R of each TSV 110. For example, if the shape of each TSV 110 is cylindrical, the first inner sidewall 110L and the second inner sidewall 110R may be the same surface. The dielectric layer 116 does not cover the end surface 110b of each TSV 110. The dielectric layer 116 is further formed on the first surface 102a of the substrate layer 102. The dielectric layer 116 may extend between adjacent TSVs 110. According to an embodiment, the dielectric layer 116 completely covers the first surface 102a of the substrate layer 102 and the first inner sidewall 110R and the second inner sidewall 110L of each TSV 110.

[0036] A redistribution layer 118 (which includes a conductive component and a dielectric component) is formed on each first inner sidewall 110R and second inner sidewall 110L of each TSV 110. The redistribution layer 118 is formed on the dielectric layer 116 inside each TSV 110. According to some embodiments, the redistribution layer 118 completely covers the dielectric layer 116 on each first inner sidewall 110R and second inner sidewall 110L of each TSV 110. The redistribution layer 118 is also formed on each end surface 110b of each TSV 110. In some embodiments, the redistribution layer 118 completely covers each end surface 110b. The redistribution layer 118 on the end surface 110b is coupled to the contact 122. The redistribution layer 118 formed on the dielectric layer 116 on the first surface 102a of the substrate layer 102 only partially covers the dielectric layer 116. That is, the redistribution layer 118 does not completely extend between adjacent TSVs 110. Instead, a plurality of gaps 120 are formed between adjacent TSVs 110, where a portion of dielectric layer 116 remains uncovered by redistribution layer 118. The plurality of gaps 120 may be formed by etching or by other processes. Portions of redistribution layer 118 on either side of gap 120 form a plurality of contact regions 118c.

[0037] The redistribution layer 114 may be metal, and may be formed by a process such as photolithography or plating.

[0038] A first cavity 136 is formed between two of the plurality of TSVs 110 along the dividing line 130. The first cavity 136 is formed in one of the plurality of gaps 120 in the redistribution layer 118. The first cavity 136 extends through the entire dielectric layer 116, the entire substrate layer 102, the entire bonding layer, and a portion of the transparent layer 104 along the first direction. That is, the first cavity 136 extends through the first surface 104a of the transparent layer 104 along the first direction but does not reach the second surface 104b of the transparent layer 104. The first cavity 136 includes an end surface 136b that may be parallel to the first surface 102a of the substrate layer 102.

[0039] The first cavity 136 includes a first sidewall 136L and a second sidewall 136R. The first sidewall 136L of the first cavity 136 includes a first central sidewall 102CL of the substrate layer 102, a first central sidewall 108CL of the bonding layer 108, and a first central sidewall 104CL of the transparent layer 104. Each of the first central sidewalls 102CL, 108CL, and 104CL is coplanar. The second sidewall 136L of the first cavity 136 includes a second central sidewall 102CR of the substrate layer 102, a second central sidewall 108CR of the bonding layer 108, and a second central sidewall 104CR of the transparent layer 104. Each of the second central sidewalls 102CR, 108CR, and 104CR is coplanar. The first sidewall 136L and the second sidewall 136R of the first cavity 136 may be perpendicular to the end surface 136b.

[0040] The first cavity 136 may be formed using a saw or by other cutting methods.

[0041] refer to Figure 2C , a solder resist layer 112 is formed on the first surface 102a of the substrate layer 102 and in the first cavity 136. According to some embodiments, the first cavity 136 is completely filled with the solder resist layer 112. The solder resist layer 112 on the first surface 102a of the substrate layer 102 also covers the redistribution layer 118 and the dielectric layer 116 on the first surface 102a. A portion of each TSV 110 is filled with the solder resist layer 112. Each TSV 110 may include a portion that is at least partially filled with air or includes an unfilled gap 138.

[0042] Portions of the solder resist layer 112 covering the contact regions 118c are removed to expose the contact regions 118c of the redistribution layer 118. The removal of portions of the solder resist layer 112 may be performed by etching or by other processes.

[0043] A first plurality of solder balls 124 are formed on the exposed contact regions 118c of the redistribution layer 118. The first plurality of solder balls 124 include conductive features.

[0044] The first plurality of solder balls 124 may be metal.

[0045] The first carrier layer 128 is removed from the transparent layer 104 by a process such as lift-off.

[0046] The second cavity 140 is formed in the solder resist layer 112 in the first cavity 136. The second cavity 140 extends from the first outer surface 112a of the solder resist layer 112 to the end surface 136b of the first cavity along the first direction. The second cavity 140 is narrower than the first cavity 136 in the second direction. That is, the second cavity does not extend from the first sidewall 136L of the first cavity 136 to the second sidewall 136R. During the formation of the second cavity 140, the portion of the solder resist layer 112 covering the first sidewall 136L and the second sidewall 136R of the first cavity 136 is not removed. The portion of the solder resist layer 112 covering the second sidewall 136R of the first cavity 136 forms the first sidewall 112L of the solder resist layer 112. The first sidewall 112L of the solder resist layer 112 covers the first central sidewall 102CL of the substrate layer 102, the first central sidewall 108CL of the adhesive layer 108, and the first central sidewall 104CL of the transparent layer 104, as shown in FIG. Figure 2B The portion of the solder resist layer 112 covering the first side wall 136L of the first cavity 136 forms a second side wall 112R of the solder resist layer 112. The second side wall 112R of the solder resist layer 112 covers the second central side wall 102CR of the substrate layer 102, the second central side wall 108CR of the bonding layer 108, and the second central side wall 104CR of the transparent layer 104, as shown in FIG. Figure 2B as shown in .

[0047] The second cavity 140 may be formed by laser. The second cavity 140 may reduce warpage and / or wattage of the electronic device 100.

[0048] refer to Figure 2D , the first die 132 is separated from the second die 134 along the dividing line 130 in the first direction. Figure 2D A first die 132 is shown. Separation of the first die 132 from the second die 134 may be performed using a saw or by other cutting processes.

[0049] The first tube core 132 includes a first side wall 132L and a second side wall 132R. The first side wall 112L of the solder resist layer 112 partially covers the first side wall 132L of the first tube core 132. The inner surface 112La of the first side wall 112L of the solder resist layer 112 covers the first side wall 102L of the substrate layer 102 and the first portion 104La of the first side wall 104L of the transparent layer 104. The first side wall 102L of the substrate layer 102 is coplanar with the first portion 104La of the first side wall 104L of the transparent layer 104. The first side wall 112L of the solder resist layer 112 does not cover the second portion 104Lb of the first side wall 104L of the transparent layer 104. The second portion 104Lb of the first side wall 104L of the transparent layer 104 is coplanar with the outer surface 112Lb of the first side wall 112L of the solder resist layer 112. The first sidewall 132L of the first die 132 includes the second portion 104Lb of the first sidewall 104L of the transparent layer 104 and the outer surface 112Lb of the first sidewall 112L of the solder resist layer 112 .

[0050] The second side wall 112R of the solder resist layer 112 partially covers the second side wall 132R of the first tube core 132. The inner surface 112Ra of the second side wall 112R of the solder resist layer 112 covers the second side wall 102R of the substrate layer 102 and the first portion 104Ra of the second side wall 104R of the transparent layer 104. The second side wall 102R of the substrate layer 102 is coplanar with the first portion 104Ra of the second side wall 104R of the transparent layer 104. The second side wall 112R of the solder resist layer 112 does not cover the second portion 104Rb of the second side wall 104R of the transparent layer 104. The second portion 104Rb of the second side wall 104R of the transparent layer 104 is coplanar with the outer surface 112Rb of the second side wall 112R of the solder resist layer 112. The second sidewall 132R of the first die 132 includes the second portion 104Rb of the second sidewall 104R of the transparent layer 104 and the outer surface 112Rb of the second sidewall 112R of the solder resist layer 112 .

[0051] refer to Figure 2E , the separated first tube die 132 and the second tube die 134 are both mounted on the second carrier layer 142. The second carrier layer 142 is in contact with the second surface 104b of the transparent layer 104. Figure 2E Only the first die 132 and the second die 134 are shown in FIG. 1 , but embodiments may include more dies mounted to the second carrier layer 142 .

[0052] The molding material layer 114 is formed on five sides of both the first die 132 and the second die 134. The molding material layer 114 includes a first region 114c covering a portion of the outer surface 112a of the solder resist layer 112 located on the first surface 102a of the substrate layer 102. The first region 114c of the molding material layer 114 also covers the first plurality of solder balls 124.

[0053] The molding material layer 114 also completely covers the first sidewall 132L and the second sidewall 132R of the first die 132. The molding material layer 114 also completely covers the first sidewall 134L and the second sidewall 134R of the second die 134. The molding material layer 114 contacts the second carrier layer 142 on each side of both the first die 132 and the second die 134.

[0054] The molding material layer 114 may include plastic, epoxy, or other substances.

[0055] refer to Figure 2F The first region 114c of the molding material layer 114 and a portion of the first plurality of solder balls 124 are removed by a process that may include grinding. When a portion of the first plurality of solder balls 124 is removed, each of the first plurality of solder balls 124 leaves a flat surface 124a that is coplanar with the first outer surface 114a of the molding material layer 114.

[0056] A second plurality of solder balls 126 are formed on the first plurality of solder balls 124. The second plurality of solder balls 126 each have a circular outer surface 126a and a flat surface 126b. The flat surface 126b of each solder ball in the second plurality of solder balls 126 is coupled to the flat surface 124a of each solder ball in the first plurality of solder balls 124. The flat surface 126b of each solder ball in the second plurality of solder balls 126 may be circular and may have a circumference greater than the circumference of the flat surface 124a of each solder ball in the first plurality of solder balls 124. That is, the flat surface 126b may be coupled to the flat surface 124a of each solder ball in the first plurality of solder balls 124 and the first surface 114a of the molding material layer 114.

[0057] refer to Figure 2G, a plurality of singulation cavities 144 are formed in the molding material layer 114. The plurality of singulation cavities 144 extend from the first surface 114a of the molding material layer 114 to the second carrier layer 142 in a first direction. One of the plurality of singulation cavities 144 is formed between the first tube core 132 and the second tube core 134. The singulation cavity 144 between the first tube core 132 and the second tube core 134 is narrower than the distance between the first tube core 132 and the second tube core 134 in the second direction. That is, the singulation cavity 144 does not extend from the second side wall 132R of the first tube core 132 to the first side wall 134L of the second tube core 134. The portion of the molding material layer 114 between the first tube core 132 and the second tube core 134 is not removed during the formation of the singulation cavity 144. The portion of the molding material layer 114 covering the first side wall 134L of the second tube core 134 forms the first side wall 114L of the molding material layer 114. The first sidewall 114L of the molding material layer 114 covers the outer surface 112Rb of the first sidewall 112L of the solder resist layer 112 on the second die 134. The first sidewall 114L of the molding material layer 114 further covers the second portion 104Lb of the first sidewall 104L of the transparent layer 104 in the second die 134.

[0058] The portion of the molding material layer 114 covering the second sidewall 132R of the first die 132 forms the second sidewall 114R of the molding material layer 114. The second sidewall 114R of the molding material layer 114 covers the outer surface 112Rb of the second sidewall 112R of the solder resist layer 112 on the first die 132. The second sidewall 114R of the molding material layer 114 additionally covers the second portion 104Rb of the second sidewall 104R of the transparent layer 104 in the first die 132.

[0059] The thickness of the first sidewall 114L and the second sidewall 114R of the molding material layer 114 may be about 200 micrometers.

[0060] The thickness of the first region 114 c of the molding material layer 114 may be about 100 micrometers.

[0061] Singulation cavities 144 are also formed in the molding material layer 114 closest to the first sidewall 132L of the first die 132 and in the molding material layer 114 closest to the second sidewall 134R of the second die 134. A portion of the molding material layer 114 remains on the first sidewall 132L of the first die 132, thereby forming the first sidewall 114L of the molding material layer 114 on the first die 132. A portion of the molding material layer 114 remains on the second sidewall 134R of the second die 134, thereby forming the second sidewall 114R of the molding material layer 114 on the second die 134. A plurality of outer portions 146 of the molding material layer 114 remain attached to the second carrier layer 142 and are separated from the first sidewall 114L and the second sidewall 114R of the molding material layer 114 by the singulation cavities 144 extending along the first direction from the first surface 114a of the molding material layer to the second carrier layer 142.

[0062] The second carrier layer 142 and the plurality of outer portions 146 of the molding material layer 114 are removed from the first die 132 and the second die 134 . Figure 1 The embodiment in FIG. 4 shows the final product of the method after removal of the second carrier layer 142 and the plurality of outer portions 146 of the molding material layer 114 .

[0063] The present disclosure relates to a device, which includes: a substrate, which includes a first surface opposite to a second surface and a plurality of sidewalls extending from the first surface to the second surface; and a through-silicon via extending from the second surface of the substrate to the first surface of the substrate. A transparent layer is provided on the first surface of the substrate, and the transparent layer includes an exposed surface and a plurality of sidewalls extending from the exposed surface to the first surface of the substrate. A solder resist layer is located on the second surface of the substrate and each of the plurality of sidewalls and is coupled to a first portion of each of the plurality of sidewalls of the transparent layer, and a molding material layer covers the solder resist layer and a second portion of each of the plurality of sidewalls of the transparent layer. A first plurality of solder balls are coupled to the substrate, and a second plurality of solder balls are coupled to respective solder balls in the first plurality of solder balls.

[0064] The device includes, each of the first plurality of solder balls having a flat surface. Each of the second plurality of solder balls is coupled to the flat surface of each solder ball in the first plurality of solder balls. A second through-silicon via extends from the second surface of the substrate to the first surface of the substrate. A plurality of sensor elements are coupled between the first surface of the substrate and the transparent layer, and the plurality of sensor elements are located between the first through-silicon via and the second through-silicon via. A dielectric layer is coupled to the second surface of the substrate and covers the inner surface of the first through-silicon via. A redistribution layer partially covers the second surface of the substrate and covers the inner surface of the first through-silicon via. A contact is located on the first surface of the substrate and coupled to the redistribution layer in the first through-silicon via. An air gap exists between the solder resist layer and the contact on the first surface of the substrate in the first through-silicon via. An outer surface of the molding material layer is coplanar with the flat surface of each of the first plurality of solder balls.

[0065] The present disclosure also relates to a device, which includes a substrate, the substrate including a first surface opposite to a second surface. A transparent layer is coupled to the first surface of the substrate. A first plurality of solder balls are coupled to the second surface of the substrate, each of the first plurality of solder balls having a flat surface, and a molding material layer is coupled to the second surface of the substrate, the molding material layer having an outer side surface coplanar with the flat surface of each of the first plurality of solder balls. A second plurality of solder balls, each of the second plurality of solder balls is coupled to the molding material layer and one of the first plurality of solder balls. A solder resist layer is located between the second surface of the substrate and the molding material layer. The molding material layer completely covers the solder resist layer and completely covers the multiple sidewalls of the transparent layer. A through-silicon via extends from the second surface of the substrate to the first surface of the substrate. There is an unfilled gap between the solder resist layer and the first surface of the substrate in the through-silicon via.

[0066] The present disclosure relates to a method, the method comprising: forming a first through-silicon via from a first surface of a substrate layer to a second surface of the substrate layer, the second surface being opposite to the first surface, and forming a first opening that passes completely through the substrate layer and partially through a transparent layer coupled to the second surface of the substrate layer. The method comprises: forming a solder resist layer on the first surface of the substrate layer and in the first opening, and forming a second opening through the solder resist layer in the first opening, the second opening extending completely through the substrate layer and completely through the transparent layer. The method comprises: forming a redistribution layer on an inner surface of the first through-silicon via and on the first surface of the substrate layer, and forming a first plurality of solder balls coupled to the redistribution layer. The method comprises: forming a molding material layer on the solder resist layer and in the second opening; forming a flat surface on each of the first plurality of solder balls; and forming a second plurality of solder balls, each of the second plurality of solder balls being coupled to one of the first plurality of solder balls.

[0067] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified if necessary to employ concepts of the various patents, applications and publications to provide further embodiments.

[0068] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalent forms to which the claims are assigned. Therefore, the claims are not limited by the present disclosure.

Claims

1. An electronic device, characterized in that: include: a substrate including a first surface opposite to a second surface and a plurality of sidewalls extending from the first surface to the second surface; a first through silicon via extending from the second surface of the substrate to the first surface of the substrate; a transparent layer located on the first surface of the substrate, the transparent layer comprising an exposed surface and a plurality of side walls extending from the exposed surface to the first surface of the substrate; a solder resist layer located on each of the plurality of sidewalls and the second surface of the substrate and coupled to a first portion of each of the plurality of sidewalls of the transparent layer; a molding material layer, the molding material layer covering the solder resist layer and a second portion of each of the plurality of side walls of the transparent layer; a first plurality of solder balls coupled to the substrate; as well as A second plurality of solder balls are coupled to respective solder balls of the first plurality of solder balls.

2. The electronic device according to claim 1, wherein: Each solder ball in the first plurality of solder balls has a flat surface.

3. The electronic device according to claim 2, wherein: Wherein each solder ball of the second plurality of solder balls is coupled to the planar surface of a respective solder ball of the first plurality of solder balls.

4. The electronic device according to claim 1, wherein: A second through silicon via is included that extends from the second surface of the substrate to the first surface of the substrate.

5. The electronic device as claimed in claim 4, characterized in that: A plurality of sensor elements are coupled between the first surface of the substrate and the transparent layer, the plurality of sensor elements being located between the first through silicon via and the second through silicon via.

6. The electronic device as claimed in claim 1, wherein: A dielectric layer is included, the dielectric layer being coupled to the second surface of the substrate and covering an inner surface of the first through silicon via.

7. The electronic device according to claim 1, wherein: A redistribution layer is included, wherein the redistribution layer partially covers the second surface of the substrate and covers an inner surface of the first through-silicon via.

8. The electronic device as claimed in claim 7, characterized in that: A contact is included, the contact being located on the first surface of the substrate and coupled to the redistribution layer in the first through silicon via.

9. The electronic device as claimed in claim 8, characterized in that: An air gap is included in the first through silicon via between the solder resist layer and the contact on the first surface of the substrate.

10. The electronic device as claimed in claim 2, characterized in that: The outer surface of the molding material layer is coplanar with the planar surface of each solder ball in the first plurality of solder balls.

11. An electronic device, characterized in that: include: a substrate comprising a first surface opposite to a second surface; a transparent layer coupled to the first surface of the substrate; a first plurality of solder balls coupled to the second surface of the substrate, each solder ball in the first plurality of solder balls having a planar surface; a layer of molding material coupled to the second surface of the substrate, the layer of molding material having an outer side that is coplanar with the planar surface of each solder ball in the first plurality of solder balls; as well as A second plurality of solder balls, each solder ball in the second plurality of solder balls being coupled to the layer of molding material and to one solder ball in the first plurality of solder balls.

12. The electronic device according to claim 11, wherein: A solder resist layer is included between the second surface of the substrate and the molding material layer.

13. The electronic device according to claim 12, wherein: The molding material layer completely covers the solder resist layer and completely covers the plurality of side walls of the transparent layer.

14. The electronic device according to claim 11, wherein: A through silicon via is included that extends from the second surface of the substrate to the first surface of the substrate.

15. The electronic device according to claim 14, wherein: include: a solder resist layer between the second surface of the substrate and the molding material layer; as well as An unfilled gap between the solder resist layer and the first surface of the substrate is provided in the through silicon via.

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