Semiconductor packaging structure and display device

Abstract

The utility model relates to a semiconductor packaging structure and a display device. The semiconductor packaging structure comprises a packaging substrate, the packaging substrate comprises an accommodating groove and a first bonding pad, and the first bonding pad is arranged around the accommodating groove; the chip comprises a first substrate, the first substrate is arranged in the containing groove, and a connecting bonding pad is arranged on the surface, deviating from the bottom wall of the containing groove, of the first substrate; and the lead is electrically connected with the first bonding pad and the connection bonding pad. According to the semiconductor packaging structure and the display device, the high-speed signal transmission capability of the chip can be improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a display device. Background Art

[0002] LCOS (Lipuid Crystal On Silicon) technology is a product of the combination of LCD and semiconductor CMOS technology. It has the characteristics of high resolution and high brightness. In addition, the product structure is simple and the cost is low. It has gradually become one of the important development directions of display technology. In the related technology, in order to avoid being affected by water vapor, dust and the like in the environment, the LCOS chip needs to be packaged. Specifically, the LCOS chip can be fixed on the ceramic substrate by thermal conductive glue, and the pads on the chip can be electrically connected to the pads on the ceramic substrate by a gold wire bonding process. Subsequently, a sealing colloid can be used to cover the bonding position of the gold wire for sealing protection. However, in this packaging structure, there is a problem that the high-speed signal transmission capability of the chip is poor. Utility Model Content

[0003] Based on this, it is necessary to provide a semiconductor packaging structure and a display device that can improve the high-speed signal transmission capability of the chip.

[0004] A first aspect of an embodiment of the present application provides a semiconductor packaging structure, including:

[0005] A packaging substrate, the packaging substrate comprising a receiving groove and a first solder pad, wherein the first solder pad is arranged around the receiving groove;

[0006] The chip comprises a first substrate, the first substrate is arranged in the receiving groove, and a connection pad is arranged on a surface of the first substrate away from the groove bottom wall of the receiving groove;

[0007] The leads are electrically connected to the first pad and the connection pad respectively.

[0008] In one embodiment, a height of the connecting pad relative to the bottom wall of the receiving groove is greater than or equal to a height of the first pad relative to the bottom wall of the receiving groove.

[0009] In one embodiment, each side wall of the receiving groove is correspondingly fitted with each side surface of the first substrate.

[0010] In one embodiment, the first substrate is bonded to the bottom wall of the accommodating groove through a thermal conductive adhesive layer.

[0011] In one embodiment, a metal sheet is sandwiched in the thermal conductive adhesive layer.

[0012] In one embodiment, the package matrix further includes a package substrate and a circuit board stacked on each other;

[0013] The first pad is arranged on a surface of the circuit board away from the packaging substrate.

[0014] In one of the embodiments, the chip further includes a second substrate and a liquid crystal layer;

[0015] The second substrate is arranged opposite to the first substrate and partially staggered, and the liquid crystal layer is sandwiched between the second substrate and the first substrate;

[0016] The first substrate and the second substrate respectively have a first surface and a second surface arranged opposite to each other, and the connection pad is arranged on a partial area of ​​the first surface which is staggered from the second substrate;

[0017] A second pad is also provided on a partial area of ​​the second surface that is offset from the first substrate;

[0018] The second pad is suspended above the package substrate and is electrically connected to a portion of the first pad through a conductive adhesive.

[0019] In one of the embodiments, a surface of the package substrate facing away from the first solder pad is further provided with a heat dissipation fin;

[0020] The heat dissipation fins are formed integrally with the packaging substrate.

[0021] In one of the embodiments, a surface of the package substrate facing away from the first solder pad is further provided with a heat dissipation fin;

[0022] The heat dissipation fins are connected to the packaging base through fasteners.

[0023] In one embodiment, the semiconductor package structure further includes a sealing colloid, which covers the lead and the connecting pad and the first pad electrically connected through the lead.

[0024] A second aspect of an embodiment of the present application provides a display device, comprising the above-mentioned semiconductor packaging structure.

[0025] Beneficial effects of the semiconductor packaging structure and display device described above:

[0026] A receiving groove is provided on one surface of the packaging substrate, and the first substrate is arranged in the receiving groove. In this way, at least a part of the structure of the first substrate is located in the receiving groove. Compared with the first substrate being arranged as a whole on the surface of the packaging substrate, the height difference between the connecting pad and the first pad is reduced. In this way, the length of the lead connecting the connecting pad and the first pad can be reduced, so that the impedance of the lead is reduced, thereby improving the high-speed signal transmission capability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of a semiconductor packaging structure provided by an embodiment of the present application;

[0028] Figure 2A schematic diagram of the structure of a package substrate in a semiconductor package structure provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the structure of a chip in a semiconductor packaging structure provided in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of another structure of a semiconductor packaging structure provided in an embodiment of the present application.

[0031] Description of Figure Numbers:

[0032] 100. Semiconductor packaging structure;

[0033] 10. Package base; 11. Accommodating groove; 12. First solder pad; 13. Package substrate; 14. Circuit board;

[0034] 20. chip; 21. first substrate; 211. connection pad; 212. second pad; 22. second substrate; 23. liquid crystal layer;

[0035] 30. Lead wire;

[0036] 40. thermal conductive adhesive layer; 41. metal sheet; 50. conductive adhesive; 60. sealing colloid; 70. heat dissipation fins; 80. fasteners;

[0037] F, first surface; S, second surface. DETAILED DESCRIPTION

[0038] In order to make the above-mentioned purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the utility model. However, the utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the utility model, so the utility model is not limited by the specific embodiments disclosed below.

[0039] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0040] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0041] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0042] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0043] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0044] The semiconductor packaging structure and display device of the embodiment of the present application are described below with reference to the accompanying drawings. It should be noted that the semiconductor packaging structure in the present application is described by taking the packaging of LCOS (Lipuid Crystal On Silicon) chips as an example, and the case where the chips are of other types is similar and will not be described in detail here.

[0045] Figure 1 A schematic diagram of a semiconductor packaging structure provided in an embodiment of the present application, Figure 2A schematic diagram of the structure of a package substrate in a semiconductor package structure provided in an embodiment of the present application, Figure 3 A schematic diagram of the structure of a chip in a semiconductor packaging structure provided in an embodiment of the present application, Figure 4 A schematic diagram of another structure of a semiconductor packaging structure provided in an embodiment of the present application.

[0046] Reference Figure 1 The semiconductor package structure 100 provided in the embodiment of the present application includes a package base 10 , a chip 20 and a lead 30 .

[0047] The package base 10 includes a receiving groove 11 and a first pad 12, and the first pad 12 is arranged around the receiving groove 11. The chip 20 includes a first substrate 21, and the first substrate 21 is arranged in the receiving groove 11. The surface of the first substrate 21 away from the bottom wall of the receiving groove 11 is provided with a connecting pad 211. The lead 30 is electrically connected to the first pad 12 and the connecting pad 211 respectively.

[0048] A receiving groove 11 is provided on one surface of the packaging base 10, and the first substrate 21 is provided in the receiving groove 11. In this way, at least part of the structure of the first substrate 21 is located in the receiving groove 11. Compared with the first substrate 21 being entirely provided on the surface of the packaging base 10, the height difference between the connecting pad 211 and the first pad 12 is reduced, so that the length of the lead 30 connecting the connecting pad 211 and the first pad 12 can be reduced, so that the impedance of the lead 30 is reduced, thereby improving the high-speed signal transmission capability of the chip 20.

[0049] In the embodiment of the present application, the packaging base 10 also includes a packaging substrate 13 and a circuit board 14 stacked on each other, so that the first solder pad 12 is set on the circuit board 14, and the first solder pad 12 can be arranged around the notch of the accommodating groove 11.

[0050] The first substrate 21 is disposed in the receiving groove 11, which means that when the first substrate 21 is received in the receiving groove 11, the thickness direction of the first substrate 21 is substantially parallel to the depth direction of the receiving groove 11. Figure 1 As shown in FIG, a portion of the structure on the lower side of the first substrate 21 in the thickness direction is entirely accommodated inside the accommodation groove 11 , and a portion of the structure on the upper side of the first substrate 21 in the thickness direction is located outside the accommodation groove 11 .

[0051] The surface of the first substrate 21 away from the bottom wall of the accommodating groove 11 is provided with a connecting pad 211, which means that the upper surface of the first substrate 21 protruding from the notch of the accommodating groove 11 is provided with a connecting pad 211. The number of the connecting pads 211 can be set as needed, and they are respectively used to electrically connect with different pads of the chip 20.

[0052] In addition, the electrical connection between the lead 30 and the first pad 12 and the connection pad 211 can be achieved, for example, by wire bonding. The lead 30 can be, for example, an aluminum wire or a gold wire.

[0053] In the embodiment of the present application, the height of the connecting pad 211 relative to the bottom wall of the receiving groove 11 is greater than or equal to the height of the first pad 12 relative to the bottom wall of the receiving groove 11. In this way, the height difference between the connecting pad 211 and the first pad 12 can be reduced, so as to reduce the length of the lead 30 and reduce the impedance of the lead 30.

[0054] Furthermore, the side walls of the receiving groove 11 are correspondingly fitted with the side surfaces of the first substrate 21. In this way, the side walls of the receiving groove 11 support the side surfaces of the first substrate 21, and the first chip 20 can be relatively stably arranged in the receiving groove 11. Of course, the receiving groove 11 can also be slightly larger than the first substrate 21, as long as the first substrate 21 can be accommodated therein.

[0055] In the embodiment of the present application, the first substrate 21 is bonded to the bottom wall of the receiving groove 11 through the thermally conductive adhesive layer 40. Thus, the thermally conductive adhesive layer 40 can play a bonding role between the first substrate 21 and the receiving groove 11. In addition, the thermally conductive adhesive layer 40 can also play a heat conduction role, which is convenient for transferring the heat on the chip 20 to the packaging substrate 10. The thermally conductive adhesive layer 40 can be, for example, a highly thermally conductive double-sided adhesive or a highly thermally conductive glue.

[0056] In specific implementation, in order to further improve the heat dissipation of the semiconductor packaging structure 100, a metal sheet 41 is sandwiched in the thermal conductive adhesive layer 40. The thermal conductivity of the metal sheet 41 is higher than the thermal conductivity of the packaging substrate 13 described later. For example, a layer of high thermal conductive adhesive can be firstly arranged on the bottom wall of the accommodating groove 11, and the metal sheet 41, such as a copper sheet, can be adhered to the first layer of high thermal conductive adhesive. After curing, another layer of high thermal conductive adhesive is coated on the first layer of high thermal conductive adhesive, and the first chip 20 is adhered to the second layer of high thermal conductive adhesive. After curing, the thermal conductive adhesive layer 40 consisting of the first layer of high thermal conductive adhesive, the metal sheet 41, and the second layer of high thermal conductive adhesive can be obtained.

[0057] In the present application, continue to refer to Figure 2 As mentioned above, the package base 10 includes a package substrate 13 and a circuit board 14 stacked on each other, and the first pad 12 is arranged on the surface of the circuit board 14 away from the package substrate 13. Here, the circuit board 14 can be a flexible circuit board FPC, and the package substrate 13 can be a ceramic substrate or a metal substrate. The circuit board 14 is bonded to the package substrate 13 by adhesive or the like. When the package base 10 is grooved, the receiving groove 11 extends to the inner side of the package substrate 13. That is, the bottom wall of the receiving groove 11 is formed by the package substrate 13, a part of the groove side wall area of ​​the receiving groove 11 is formed by the package substrate 13, and another part of the area is formed by the circuit board 14.

[0058] Continue to refer to Figure 1 and Figure 3 The chip 20 further includes a second substrate 22 and a liquid crystal layer 23. The second substrate 22 and the first substrate 21 are arranged oppositely and partially staggered, and the liquid crystal layer 23 is sandwiched between the facing portions of the second substrate 22 and the first substrate 21. The first substrate 21 and the second substrate 22 respectively have a first surface F and a second surface S arranged oppositely, and the connection pad 211 is arranged on a partial area of ​​the first surface F staggered from the second substrate 22.

[0059] A second pad 212 is further disposed on a portion of the second surface S that is offset from the first substrate 21. The second pad 212 is suspended above the package substrate 10 and is electrically connected to a portion of the first pad 12 through a conductive adhesive 50. The conductive adhesive 50 may be disposed by a dispensing process.

[0060] In the embodiment of the present application, the semiconductor package structure 100 further includes a sealing colloid 60, which covers the lead 30, and the connecting pad 211 and the first pad 12 electrically connected through the lead 30. In this way, the lead 30 can be sealed and protected. The sealing colloid 60 here can be, for example, an organic silicon sealing colloid 60. The sealing colloid 60 can also cover the connection position between the second pad 212 and the first pad 12 to seal and protect the electrical connection between the second pad 212 and the first pad 12.

[0061] In the embodiment of the present application, in order to dissipate heat for the chip 20, a heat dissipation structure may be connected to the package substrate 10, for example, Figure 1 As shown, the surface of the package substrate 10 away from the first pad 12 is also provided with a heat dissipation fin 70. The heat dissipation fin 70 is formed integrally with the package substrate 10. This makes the heat conduction effect between the package substrate 10 and the heat dissipation fin 70 better.

[0062] Of course, you can also refer to Figure 4 , so that the heat dissipation fins 70 and the package base 10 are formed separately. In specific implementation, the heat dissipation fins 70 can be connected to the package base 10 through the fasteners 80. In this way, the package base 10 is more convenient to clamp during the packaging process.

[0063] Refer to the following Figure 1 The packaging process of the semiconductor packaging structure 100 according to the embodiment of the present application is described.

[0064] A layer of high thermal conductivity glue is arranged on the bottom wall of the receiving groove 11 of the package substrate 10, and a metal sheet 41, such as a copper sheet, is adhered to the first layer of high thermal conductivity glue. After curing, another layer of high thermal conductivity glue is coated on the first layer of high thermal conductivity glue, and the first chip 20 is adhered to the second layer of high thermal conductivity glue and cured. Through the wire (aluminum wire / gold wire) bonding process, the connecting pad 211 on the chip 20 is electrically connected to the first pad 12 on the package substrate 10. Then, through the dispensing process, the second pad 212 on the second substrate 22 is electrically connected to the first pad 12 on the package substrate 10 using the conductive glue 50. Finally, the connection position of the second pad 212 and the first pad 12 is covered and sealed using the sealing glue 60, and the connection position of the connecting pad 211 and the first pad 12 is covered and sealed.

[0065] The embodiment of the present application further provides a display device, including the above-mentioned semiconductor packaging structure 100. The structure, function, working principle, etc. of the semiconductor packaging structure 100 have been described in detail above and will not be repeated here.

[0066] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] The above-mentioned embodiments only express several implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the utility model patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, which all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: A packaging substrate, the packaging substrate comprising a receiving groove and a first pad, wherein the first pad is arranged around the receiving groove; A chip, the chip comprising a first substrate, the first substrate being arranged in the containing groove, and a surface of the first substrate facing away from the bottom wall of the containing groove being provided with a connection pad; Leads are electrically connected to the first pads and the connecting pads respectively.

2. The semiconductor package structure according to claim 1, wherein: A setting height of the connecting pad relative to the bottom wall of the accommodating groove is greater than or equal to a setting height of the first pad relative to the bottom wall of the accommodating groove.

3. The semiconductor package structure according to claim 2, characterized in that: The side walls of the containing groove are correspondingly fitted with the side surfaces of the first substrate.

4. The semiconductor package structure according to claim 1, wherein: The first substrate is bonded to the bottom wall of the accommodating groove through a heat-conducting adhesive layer.

5. The semiconductor package structure according to claim 4, characterized in that: A metal sheet is sandwiched in the thermal conductive adhesive layer.

6. The semiconductor packaging structure according to any one of claims 1 to 5, characterized in that: The packaging matrix also includes a packaging substrate and a circuit board stacked on each other; The first pad is disposed on a surface of the circuit board that is away from the packaging substrate.

7. The semiconductor packaging structure according to any one of claims 1 to 5, characterized in that: The chip also includes a second substrate and a liquid crystal layer; The second substrate and the first substrate are arranged opposite to each other and partially staggered, and the liquid crystal layer is sandwiched between the second substrate and the first substrate; The first substrate and the second substrate respectively have a first surface and a second surface arranged opposite to each other, and the connecting pad is arranged on a partial area of ​​the first surface which is staggered from the second substrate; A second pad is also provided on a partial area of ​​the second surface that is offset from the first substrate; The second pad is suspended above the packaging substrate and is electrically connected to a portion of the first pad through a conductive adhesive.

8. The semiconductor packaging structure according to any one of claims 1 to 5, characterized in that: The surface of the packaging substrate facing away from the first solder pad is also provided with heat dissipation fins; The heat dissipation fins are formed integrally with the packaging substrate; or The heat dissipation fins are connected to the packaging base through fasteners.

9. The semiconductor package structure according to any one of claims 1 to 5, characterized in that: The semiconductor package structure further includes a sealing colloid, wherein the sealing colloid covers the lead and the connection pad and the first pad electrically connected through the lead.

10. A display device, characterized in that: The invention comprises a semiconductor packaging structure as claimed in any one of claims 1 to 9.

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