Wireless charging synchronous phase-locked circuit

Abstract

The utility model aims to provide the wireless charging synchronous phase-locked circuit which is simple in structure, accurate in control and low in cost. The circuit comprises a sampling conditioning circuit (1), a frequency mixing multiplication circuit (2), a filter circuit (3), a biasing circuit (4) and a DSP processor (5). After the DSP processor (5) receives a signal output by the biasing circuit (4), the DSP processor (5) generates a PWM (Pulse Width Modulation) signal for driving a full-bridge converter of the wireless charging receiving end, the frequency mixing multiplication circuit (2) is provided with an address pin (SEL), and the PWM signal generated by the DSP processor (5) is output to the address pin (SEL) to control the output of frequency mixing. The wireless charging device can be applied to the technical field of wireless charging.

Description

Technical Field

[0001] The utility model relates to the technical field of wireless charging, in particular to a wireless charging synchronous phase-locked circuit. Background Art

[0002] In many power electronic systems or devices, it is necessary to measure the phase and frequency of the grid voltage in real time and control the output signal to keep it synchronized. Synchronous phase-locked technology is a basic and very critical technology in power electronic technology. Its control accuracy directly affects the operating performance of the power electronic system or device. In the early converter analog control system, some ready-made phase-locked loop chips were often used, such as 4046B phase-locked loop integrated chip, but the control accuracy of its phase lock was limited. In recent years, direct digital synthesis (DDS) chips, such as AD9851 chips, have been used in digital-analog hybrid control systems to achieve high-precision digital synchronous phase-locked technology, but its implementation cost is too high.

[0003] With the widespread application of wireless charging technology in new energy equipment, mobile electronic devices and other fields, the synchronous phase-locking circuit inside it plays a vital role. In actual application scenarios, the synchronous phase-locking mechanism is like a precise navigation system for energy transmission, ensuring the accurate interaction of high-frequency electromagnetic fields between the transmitter (i.e. the wireless charging base) and the receiver (such as a mobile phone or electric car battery).

[0004] When the wireless charging system is started, the synchronous phase-locked circuit is first responsible for achieving a high degree of match between the operating frequencies of the transmitter and the receiver. This circuit precisely locks and adjusts the operating frequencies of both parties so that the two independent electrical circuits can resonate efficiently at the same frequency, thereby improving the coupling efficiency of electrical energy from the transmitting coil to the receiving coil.

[0005] Currently, in the field of wireless charging, there are problems of insufficient control accuracy and high cost. Utility Model Content

[0006] The technical problem to be solved by the utility model is to overcome the deficiencies of the prior art and provide a wireless charging synchronous phase-locked circuit with simple structure, precise control and low cost.

[0007] The technical solution adopted by the utility model is that it comprises

[0008] A sampling and conditioning circuit for sampling and preprocessing the resonant current of the wireless charging receiving end;

[0009] A mixing and multiplication circuit for receiving the analog signal output by the sampling and conditioning circuit and mixing the received two-way common-phase and anti-phase analog signals;

[0010] A filter circuit for filtering the signal mixed by the mixing and multiplication circuit and outputting a valid signal;

[0011] A bias circuit for removing an offset from a valid signal output by the filter circuit and outputting the signal at a boosted voltage; and

[0012] A DSP processor for processing a signal output by the bias circuit;

[0013] After the DSP processor receives the signal output by the bias circuit, the DSP processor generates a PWM signal to drive the full-bridge converter of the wireless charging receiving end. The mixer multiplication circuit is provided with an address pin, and the PWM signal generated by the DSP processor is output to the address pin to control the output of the mixer.

[0014] Furthermore, the PWM signals generated by the DSP processor are two square wave signals with a 90° phase shift from each other and two duty cycles of 50%.

[0015] Furthermore, the sampling and conditioning circuit includes a current sensor and an inverting amplifier connected to the current sensor, the mixing and multiplication circuit includes two multiplexers, the negative input of the inverting amplifier is connected to the V0 input pins of the two multiplexers, and the output of the inverting amplifier is connected to the V1 input pins of the two multiplexers.

[0016] In addition, the filter circuit uses two Butterworth second-order voltage-controlled low-pass filters to filter the signal output by the mixing and multiplication circuit.

[0017] In addition, the bias circuit is composed of two bias amplifiers.

[0018] Finally, the DSP processor adopts a signal processor of model TMS320F28335.

[0019] The beneficial effects of the utility model are as follows: in the utility model, through the cooperation of the sampling and conditioning circuit, the frequency mixing and multiplication circuit, the filter circuit, the bias circuit and the DSP processor, a frequency synchronization module is loaded in the DSP processor, the current signal is collected by the sampling and conditioning circuit, the signal is mixed by the frequency mixing and multiplication circuit, and then filtered and biased to obtain a valid signal and input it into the DSP processor for processing, to obtain the PWM duty cycle and phase shift of the current signal, and then feed it back to the frequency mixing and multiplication circuit to correct the signal, and finally make the frequency of the receiving end and the transmitting end of the wireless charging keep synchronized; the circuit structure of the utility model is simple, the control is precise and the cost is low; specifically,

[0020] 1. High-precision frequency locking: The synchronous phase-locked circuit can detect and track the frequency changes of the target signal in real time, and automatically adjust the local oscillator signal to achieve precise frequency synchronization with the target signal, which is crucial for the stability and efficiency of high-frequency energy transmission in the wireless charging system;

[0021] 2. Phase stability: Through a closed-loop control mechanism, the circuit can accurately maintain the phase relationship between the transmitter and the receiver, ensuring that the two work at the optimal phase difference, thereby maximizing the power transmission efficiency and power coupling coefficient;

[0022] 3 Dynamic response capability: It has fast and accurate dynamic adjustment function, which can adapt to parameter fluctuations caused by load changes, environmental interference, etc., quickly adjust to the optimal working state, and maintain stable operation of the system;

[0023] 4 Strong robustness: Even in the presence of adverse conditions such as noise, temperature drift or power supply voltage fluctuations, the synchronous phase-locked circuit can still effectively suppress external interference and ensure stable system performance;

[0024] 5. High integration: With the support of modern integrated circuit technology, the synchronous phase-locked circuit can be highly integrated, reducing the number of components, reducing system volume and cost, while improving the reliability of the overall system;

[0025] 6. Wide applicability: It is not only suitable for wireless charging systems, but also widely used in communications, power electronics, motor control, signal processing and other fields. Its flexibility and versatility make it an important part of many complex circuit designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a principle block diagram of the utility model;

[0027] Figure 2 It is the circuit principle diagram of the utility model;

[0028] Figure 3 It is a coordinate diagram of the resonant current Euler angle; the ordinates of Ds and Qs represent the magnitude of the analog quantity, θ C and θ E The vertical axis represents the angle, and the unit is the angular unit; the horizontal axis is the time offset of the simulation run, which shows the changes of the circuit under different numerical values ​​during the simulation. DETAILED DESCRIPTION

[0029] like Figures 1 to 3 As shown, in the utility model, the utility model includes a sampling and conditioning circuit 1 for sampling and preprocessing the resonant current of the wireless charging receiving end;

[0030] A mixing and multiplication circuit 2 for receiving the analog signal output by the sampling and conditioning circuit 1 and mixing the received two-way common-phase and anti-phase analog signals;

[0031] A filter circuit 3 for filtering the signal mixed by the mixing and multiplication circuit 2 and outputting a valid signal;

[0032] A bias circuit 4 for removing the offset of the effective signal output by the filter circuit 3 and boosting the signal for output; and

[0033] A DSP processor 5 for processing the signal output by the bias circuit 4;

[0034] After the DSP processor 5 receives the signal output by the bias circuit 4, the DSP processor 5 generates a PWM signal to drive the full-bridge converter of the wireless charging receiving end. The mixing multiplication circuit 2 is provided with an address pin SEL, and the PWM signal generated by the DSP processor 5 is output to the address pin SEL to control the output of the mixing.

[0035] The PWM signals generated by the DSP processor 5 are two square wave signals with a 90° phase shift and two duty cycles of 50%. In this embodiment, the DSP processor 5 is a signal processor of model TMS320F28335.

[0036] The sampling and conditioning circuit 1 includes a current sensor and an inverting amplifier U2B connected to the current sensor. The mixing and multiplication circuit 2 includes two multiplexers OPA875, the negative input of the inverting amplifier U2B is connected to the V0 input pins of the two multiplexers OPA875, and the output of the inverting amplifier U2B is connected to the V1 input pins of the two multiplexers OPA875. The filter circuit 3 uses two Butterworth second-order voltage-controlled low-pass filters to filter the signal output by the mixing and multiplication circuit 2. The bias circuit 4 is composed of two bias amplifiers U17A and U17B.

[0037] The working principle of the utility model is as follows:

[0038] In order to force the wireless charging receiving end converter and the transmitting end converter to synchronize, the circuit of the utility model is set in the full-bridge converter of the receiving end for signal control. The resonant current of the receiving end is first sampled by the sampling and conditioning circuit 1, and then pre-processed to make it into a signal pattern acceptable to the ADC.

[0039] like Figure 1As shown, two of the analog signals are in phase, while the other two are in anti-phase. These signals are then mixed by connecting them to two analog multiplexers, each with a 1-bit address ( Figure 1 ) and are connected to two square wave signals with a 90° phase shift and a 50% duty cycle (such as Figure 1 The Square D and Square Q marked in the figure are generated by the PWM generator of the DSP processor. Then the two mixed signals are passed through a Butterworth-type second-order voltage-controlled low-pass filter to obtain the effective value. Then the voltage is increased in two bias circuits. Finally, it is connected to the ADC sampling port. Figure 1 In the mixing multiplication circuit 2, the output M D and M Q It is the mixing product output of the direct-axis and quadrature axis of the current Ilrs signal. After low-pass filtering by the filter circuit and biasing by the bias circuit, they become analog signals that can be processed by the ADC, namely Ds and Qs.

[0040] Here, after removing the offset from the received analog value, the corresponding algorithm process can be executed by the DSP processor to generate a PWM signal to drive the full bridge at the receiving end. Let these two values ​​be Ds and Qs. The various key waveforms of the circuit of the utility model are as follows Figure 3 The Euler angle of the resonant current is given by:

[0041] ,

[0042] The synchronization module of the DSP processor is a four-quadrant tangent inverse function, which is used to calculate the Euler angle of the resonant current. The value of the Euler angle and the quadrant in which it is located are calculated accordingly. The above formula finally calculates the Euler angle θ E The coordinate calculation relationship of the resonant current Euler angle is shown in Figure 3 . Figure 3 In the figure, Ds and Qs represent the signal waveforms output by the two bias circuits respectively; θ C is the system phase difference, that is, the phase difference between the transmitting system and the receiving system; θ E is the Euler angle corresponding to Ds and Qs, which is obtained by the above-mentioned Euler angle calculation formula of resonant current. In practical engineering applications, the system phase difference θ C and the Euler angle θ EIt is a one-to-one relationship, and θ is controlled through the PLL (phase locked loop) process. E The size and direction of θ C control.

[0043] Finally, it should be emphasized that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A wireless charging synchronous phase-locked circuit, characterized in that: The circuit includes A sampling and conditioning circuit (1) for sampling and preprocessing the resonant current of the wireless charging receiving end; A mixing and multiplication circuit (2) for receiving the analog signal output by the sampling and conditioning circuit (1) and mixing the received two analog signals of common phase and anti-phase; A filter circuit (3) for filtering the signal mixed by the mixing and multiplication circuit (2) and outputting a valid signal; A bias circuit (4) for removing the offset of the effective signal output by the filter circuit (3) and boosting the signal for output; and A DSP processor (5) for processing a signal output by the bias circuit (4); After the DSP processor (5) receives the signal output by the bias circuit (4), the DSP processor (5) generates a PWM signal for driving the full-bridge converter of the wireless charging receiving end. The frequency mixing multiplication circuit (2) is provided with an address pin (SEL), and the PWM signal generated by the DSP processor (5) is output to the address pin (SEL) to control the output of the mixing.

2. A wireless charging synchronous phase-locked circuit according to claim 1, characterized in that: The PWM signals generated by the DSP processor (5) are two square wave signals with a 90° phase shift from each other and a duty cycle of 50%.

3. A wireless charging synchronous phase-locked circuit according to claim 1, characterized in that: The sampling and conditioning circuit (1) comprises a current sensor and an inverting amplifier (U2B) connected to the current sensor, and the mixing and multiplication circuit (2) comprises two multiplexers (OPA875), wherein the negative input of the inverting amplifier (U2B) is connected to the V0 input pins of the two multiplexers (OPA875), and the output of the inverting amplifier (U2B) is connected to the V1 input pins of the two multiplexers (OPA875).

4. A wireless charging synchronous phase-locked circuit according to claim 1, characterized in that: The filter circuit (3) uses two Butterworth-type second-order voltage-controlled low-pass filters to filter the signal output by the mixing and multiplication circuit (2).

5. A wireless charging synchronous phase-locked circuit according to claim 1, characterized in that: The bias circuit (4) is composed of two bias amplifiers (U17A, U17B).

6. A wireless charging synchronous phase-locked circuit according to claim 1, characterized in that: The DSP processor (5) is a signal processor of model TMS320F28335.

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