Back contact solar cell, cell module and photovoltaic system
By setting a P-type doped polysilicon layer and an N-type doped polysilicon layer in the back contact solar cell, and optimizing its area and refractive index relationship, the problem of poor photoelectric conversion efficiency in the prior art is solved, and higher battery efficiency is achieved.
Patent Information
- Application Number
- CN202421459139.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-24
- Publication Date
- 2025-04-01
- Estimated Expiration
- 2034-06-24
AI Technical Summary
In the existing back contact solar cells, the area relationship between the P-type doped polysilicon layer and the N-type doped polysilicon layer has not been effectively optimized, resulting in poor photoelectric conversion efficiency.
By setting a plurality of P-type doped polysilicon layers and an N-type doped polysilicon layer on the back of the silicon substrate of the back contact solar cell, the total area of the P-type doped polysilicon layer is greater than the total area of the N-type doped polysilicon layer, and the refractive index is adjusted at the same time, so that the refractive index of the P-type doped polysilicon layer is smaller than the refractive index of the N-type doped polysilicon layer.
Without changing the area of the N-type doped polysilicon layer, the total area of the P-type doped polysilicon layer is increased, and the current collection ability of the emitter is improved, thereby improving the battery efficiency. By reducing the refractive index of the P-type doped polysilicon layer, the parasitic absorption effect is reduced, and the battery efficiency is further improved.
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Figure CN222706909U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of solar cells, in particular to a back-contact solar cell, a battery assembly and a photovoltaic system. Background Art
[0002] Solar cell power generation is a sustainable source of clean energy. It uses the photovoltaic effect of semiconductors to convert sunlight into electrical energy, and the conversion efficiency is an important indicator of solar cell performance. IBC (Interdigitated back contact) solar cells, also known as interdigitated back contact cells, have positive and negative electrodes designed on the back of the cell, so that the front surface is completely free from the shading of metal grid lines, eliminating the optical loss caused by the shading of metal grid lines. At the same time, the electrode width can be designed to be wider than the current one, reducing the series resistance loss, thereby greatly improving the cell conversion efficiency. In addition, due to the design of no electrode on the front of the cell, the product appearance is more beautiful and suitable for a variety of application scenarios.
[0003] In the prior art, a staggered P-type doped polysilicon layer and an N-type doped polysilicon layer are formed on the back side of a back-contact solar cell. Usually, the effect of the area relationship between the P-type doped polysilicon layer and the N-type doped polysilicon layer on the cell efficiency is not considered. For ease of processing, the areas of the P-type doped polysilicon layer and the N-type doped polysilicon layer are usually set equal. In particular, for an N-type silicon substrate, the total area of the P-type doped polysilicon layer is equal to the total area of the N-type doped polysilicon layer, resulting in poor photoelectric conversion efficiency of the back-contact cell. Utility Model Content
[0004] The utility model provides a back-contact solar cell, aiming to solve the problem that the total area of the P-type doped polysilicon layer is equal to the total area of the N-type doped polysilicon layer in the back-contact solar cell of the prior art, and the photoelectric conversion efficiency of the back-contact solar cell is poor.
[0005] The utility model is implemented by providing a back contact solar cell, comprising:
[0006] N-type silicon substrate;
[0007] A plurality of P-type doped polysilicon layers are sequentially and spaced apart from each other on the back side of the silicon substrate;
[0008] A plurality of N-type doped polysilicon layers are sequentially and spaced apart from each other on the back side of the silicon substrate, and the N-type doped polysilicon layers and the P-type doped polysilicon layers are alternately arranged;
[0009] The total area of the P-type doped polysilicon layer is greater than the total area of the N-type doped polysilicon layer, and the refractive index of the P-type doped polysilicon layer is less than the refractive index of the N-type doped polysilicon layer.
[0010] Preferably, the area of at least one of the P-type doped polysilicon layers is greater than the area of any one of the N-type doped polysilicon layers.
[0011] Preferably, the number of the P-type doped polysilicon layers is greater than the number of the N-type doped polysilicon layers.
[0012] Preferably, the ratio of the total area of the P-type doped polysilicon layer to the total area of the N-type doped polysilicon layer is 1-2 and is not equal to 1.
[0013] Preferably, the ratio of the total area of the P-type doped polysilicon layer to the total area of the N-type doped polysilicon layer is 1 to 1.5, and is not equal to 1.
[0014] Preferably, the length of each of the P-type doped polysilicon layers is equal to the length of each of the N-type doped polysilicon layers, and the width of each of the P-type doped polysilicon layers is greater than the width of each of the N-type doped polysilicon layers.
[0015] Preferably, the ratio of the refractive index of the P-type doped polysilicon layer to the refractive index of the N-type doped polysilicon layer is 0.5-1, and is not equal to 1.
[0016] Preferably, the volume of the P-type doped polysilicon layer is greater than the volume of the N-type doped polysilicon layer.
[0017] The utility model also provides a battery assembly, comprising the above-mentioned back contact solar cell.
[0018] The utility model also provides a photovoltaic system, comprising the above-mentioned battery assembly.
[0019] The utility model provides a back-contact solar cell. By setting the total area of a P-type doped polysilicon layer to be larger than the total area of an N-type doped polysilicon layer, the total area of the P-type doped polysilicon layer is increased while the area of the N-type doped polysilicon layer remains unchanged, thereby improving the current collection capacity of the emitter and thus improving the cell efficiency. Furthermore, by setting the refractive index of the P-type doped polysilicon layer to be smaller than the refractive index of the N-type doped polysilicon layer, the refractive index of the P-type doped polysilicon layer is reduced while the refractive index of the N-type doped polysilicon layer remains unchanged, thereby reducing the parasitic absorption effect of the P region and further improving the cell efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 A cross-sectional schematic diagram of a back-contact solar cell provided by an embodiment of the utility model;
[0021] Figure 2A schematic diagram of the distribution of a P-type doped polysilicon layer and an N-type doped polysilicon layer of an embodiment of a back contact solar cell provided by an embodiment of the utility model;
[0022] Figure 3 A schematic diagram of the distribution of another embodiment of a P-type doped polysilicon layer and an N-type doped polysilicon layer of a back contact solar cell provided by an embodiment of the utility model. DETAILED DESCRIPTION
[0023] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.
[0024] A back-contact solar cell provided by an embodiment of the utility model can improve the current collection capacity of the emitter and thus improve the cell efficiency by setting the total area of the P-type doped polysilicon layer to be larger than the total area of the N-type doped polysilicon layer. On the premise that the total area of the N-type doped polysilicon layer remains unchanged, the total area of the P-type doped polysilicon layer is increased, and the cell efficiency is thereby improved. Furthermore, the refractive index of the P-type doped polysilicon layer is set to be smaller than the refractive index of the N-type doped polysilicon layer. On the premise that the refractive index of the N-type doped polysilicon layer remains unchanged, the parasitic absorption effect of the P region can be reduced by reducing the refractive index of the P-type doped polysilicon layer, and thus the cell efficiency can be further improved.
[0025] Please refer to Figure 1-Figure 3 The utility model provides a back contact solar cell, comprising:
[0026] N-type silicon substrate 1;
[0027] A plurality of P-type doped polysilicon layers 2 are sequentially arranged at intervals on the back side of the silicon substrate 1;
[0028] A plurality of N-type doped polysilicon layers 3 are sequentially and spaced apart from each other on the back side of the silicon substrate 1, and the N-type doped polysilicon layers 3 and the P-type doped polysilicon layers 2 are alternately arranged;
[0029] The total area of the P-type doped polysilicon layer 2 is greater than the total area of the N-type doped polysilicon layer 3 , and the refractive index of the P-type doped polysilicon layer 2 is less than the refractive index of the N-type doped polysilicon layer 3 .
[0030] In the embodiment of the utility model, the total area of the P-type doped polysilicon layer 2 is the sum of the areas of all the P-type doped polysilicon layers 2 , and the total area of the N-type doped polysilicon layer 3 is the sum of the areas of all the N-type doped polysilicon layers 3 .
[0031] A back-contact solar cell provided by an embodiment of the utility model can improve the current collection capability of the emitter and thus improve the cell efficiency by setting the total area of a plurality of P-type doped polysilicon layers 2 to be larger than the total area of a plurality of N-type doped polysilicon layers 3. On the premise that the total area of the N-type doped polysilicon layers 3 remains unchanged, the total area of the P-type doped polysilicon layers 2 is increased; moreover, the refractive index of the P-type doped polysilicon layer 2 is set to be smaller than the refractive index of the N-type doped polysilicon layer 3. On the premise that the refractive index of the N-type doped polysilicon layer 3 remains unchanged, the parasitic absorption effect of the P region can be reduced by reducing the refractive index of the P-type doped polysilicon layer 2, thereby further improving the cell efficiency.
[0032] In the embodiment of the utility model, the specific number of P-type doped polysilicon layers 2 is not limited, and multiple P-type doped polysilicon layers 2 are distributed in a forked shape on the back side of the silicon substrate 1; the specific number of N-type doped polysilicon layers 3 is not limited, and multiple N-type doped polysilicon layers 3 are distributed in a forked shape on the back side of the silicon substrate 1, and the N-type doped polysilicon layers 3 and the P-type doped polysilicon layers 2 are alternately arranged.
[0033] As an embodiment of the present invention, the area of at least one P-type doped polysilicon layer 2 is larger than the area of any N-type doped polysilicon layer 3 .
[0034] In this embodiment, the areas of the N-type doped polysilicon layers 3 are equal, and the area of one, two, three or more P-type doped polysilicon layers 2 is larger than the area of any N-type doped polysilicon layer 3, so that the total area of the multiple P-type doped polysilicon layers 2 is larger than the total area of the multiple N-type doped polysilicon layers 3.
[0035] In this embodiment, the number of the P-type doped polysilicon layer 2 and the number of the N-type doped polysilicon layer 3 can be equal (eg Figure 2 As shown in FIG. 1 ), the number of the P-type doped polysilicon layer 2 and the number of the N-type doped polysilicon layer 3 may also be unequal (as shown in FIG. 1 ). Figure 3 As shown in the figure, it is only necessary to control the area of several P-type doped polysilicon layers 2 to be larger than the area of the N-type doped polysilicon layer 3, which can ensure that the total area of the multiple P-type doped polysilicon layers 2 is larger than the total area of the multiple N-type doped polysilicon layers 3 and reduce the cost.
[0036] Please refer to Figure 3 As an embodiment of the present utility model, the number of the P-type doped polysilicon layers 2 is greater than the number of the N-type doped polysilicon layers 3 .
[0037] In this embodiment, the number of P-type doped polysilicon layers 2 is greater than the number of N-type doped polysilicon layers 3, and the area of each P-type doped polysilicon layer 2 and each N-type doped polysilicon layer 3 may be equal or unequal. By controlling the number of P-type doped polysilicon layers 2 to be greater than the number of N-type doped polysilicon layers 3, the total area of the P-type doped polysilicon layers 2 can also be made greater than the total area of multiple N-type doped polysilicon layers 3.
[0038] In this embodiment, the number of N-type doped polysilicon layers 3 is N, and the number of P-type doped polysilicon layers 2 is N+1.
[0039] As an embodiment of the present invention, the ratio of the total area of the P-type doped polysilicon layer 2 to the total area of the N-type doped polysilicon layer 3 is 1-2 and is not equal to 1.
[0040] In this embodiment, the ratio of the total area of the P-type doped polysilicon layer 2 to the total area of the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 2, which can ensure that the total area of the multiple P-type doped polysilicon layers 2 is greater than the total area of the multiple N-type doped polysilicon layers 3, and facilitate the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.
[0041] As an embodiment of the present invention, the ratio of the total area of the P-type doped polysilicon layer 2 to the total area of the N-type doped polysilicon layer 3 is 1-1.5, and is not equal to 1.
[0042] In this embodiment, the ratio of the total area of the P-type doped polysilicon layer 2 to the total area of the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 1.5, which can ensure that the total area of the multiple P-type doped polysilicon layers 2 is greater than the total area of the multiple N-type doped polysilicon layers 3, ensuring higher battery efficiency, and more convenient for the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.
[0043] Please refer to Figure 2 and Figure 3 As an embodiment of the present utility model, the length of each P-type doped polysilicon layer 2 is equal to the length of each N-type doped polysilicon layer 3, and the width d3 of each P-type doped polysilicon layer 2 is greater than the width d4 of each N-type doped polysilicon layer 3.
[0044] In this embodiment, the lengths of the N-type doped polysilicon layer 3 and the P-type doped polysilicon layer 2 are equal. Specifically, the area of the P-type doped polysilicon layer 2 can be increased by increasing the width d3 of the P-type doped polysilicon layer 2 , which is simple to implement.
[0045] As a preferred embodiment of the present utility model, the area of each P-type doped polysilicon layer 2 is larger than the area of any N-type doped polysilicon layer 3, that is, the area of any P-type doped polysilicon layer 2 is larger than the area of any N-type doped polysilicon layer 3, which facilitates the preparation of P-type doped polysilicon layers 2 and N-type doped polysilicon layers 3.
[0046] As an embodiment of the present invention, the ratio of the refractive index of the P-type doped polysilicon layer 2 to the refractive index of the N-type doped polysilicon layer 3 is 0.5-1, and is not equal to 1.
[0047] In this embodiment, the ratio of the refractive index of the P-type doped polysilicon layer 2 to the refractive index of the N-type doped polysilicon layer 3 is greater than or equal to 0.5 and less than 1, which can ensure that the refractive index of the P-type doped polysilicon layer 2 is greater than the refractive index of the N-type doped polysilicon layer 3, ensuring higher battery efficiency, and more convenient for the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.
[0048] Please refer to Figure 1 As an embodiment of the present invention, the thickness d1 of the N-type doped polysilicon layer 3 is greater than the thickness d2 of the P-type doped polysilicon layer 2 .
[0049] In the present embodiment, by setting the thickness d1 of the N-type doped polysilicon layer 3 to be greater than the thickness d2 of the P-type doped polysilicon layer 2, the thickness d2 of the P-type doped polysilicon layer 2 is reduced compared with the thickness d1 of the N-type doped polysilicon layer 3, thereby reducing the etching difficulty of the P-type doped polysilicon layer 2 and the difficulty of the patterning process, thereby facilitating the patterning process of the P-type doped polysilicon layer 2; moreover, reducing the thickness d2 of the P-type doped polysilicon layer 2 can reduce the difficulty of boron diffusion, which is beneficial to the boron diffusion process and facilitates the preparation of a P-type doped polysilicon layer 2 with a higher concentration; moreover, the thickness d1 of the N-type doped polysilicon layer 3 is greater than the thickness d2 of the P-type doped polysilicon layer 2, and the N-type doped polysilicon is thicker than the P-type doped polysilicon layer 2, thereby enhancing the passivation effect and improving the battery efficiency.
[0050] As an embodiment of the present invention, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is 1-2 and is not equal to 1.
[0051] In this embodiment, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is greater than 1 and less than or equal to 2. This can reduce the etching difficulty of the P-type doped polysilicon layer 2 and facilitate the patterning process of the P-type doped polysilicon layer 2, and is beneficial to the boron diffusion process, reducing the difficulty of boron diffusion and facilitating the preparation of a P-type doped polysilicon layer 2 with a higher concentration.
[0052] For example, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 may be:
[0053] 1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2.
[0054] Optionally, when the ratio of d1 to d2 is 1 to 2, the thickness d1 of the N-type doped polysilicon layer 3 is 100nm to 600nm, and the thickness d2 of the P-type doped polysilicon layer 2 can be 50nm to 300nm. When d1 and d2 are within the above range, both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 are easy to achieve good doping effects, both have good passivation effects, and at the same time ensure that the metallization damage is small and the contact resistance is small, and the cost is relatively low; in addition, the etching difficulty of the P-type doped polysilicon can be reduced, which is convenient for the patterning process of the P-type doped polysilicon, which is conducive to the preparation of the N-type doped polysilicon layer 3, and is conducive to the boron diffusion process, reducing the difficulty of boron diffusion, and facilitating the preparation of a high-concentration P-type doped polysilicon layer 2.
[0055] As an embodiment of the present invention, the volume of the P-type doped polysilicon layer 2 is greater than the volume of the N-type doped polysilicon layer 3 .
[0056] In this embodiment, the volume of the P-type doped polysilicon layer 2 is greater than the volume of the N-type doped polysilicon layer 3, and the volume of the P-type doped polysilicon layer 2 can be increased, and the emitter current collection efficiency of the back contact solar cell can be improved, thereby improving the battery efficiency. Specifically, the width d3 and thickness d2 of the P-type doped polysilicon layer 2 can be adjusted accordingly, so that the volume of the P-type doped polysilicon layer 2 can be increased under the premise that the volume of the N-type doped polysilicon layer 3 remains unchanged, that is, the volume of the P-type doped polysilicon layer 2 is greater than the volume of the N-type doped polysilicon layer 3, which can further increase the current collection capacity of the emitter, thereby improving the battery efficiency.
[0057] As an embodiment of the present invention, the ratio of the volume of the P-type doped polysilicon layer 2 to the volume of the N-type doped polysilicon layer 3 is 1-2, and is not equal to 1.
[0058] In this embodiment, the ratio of the volume of the P-type doped polysilicon layer 2 to the volume of the N-type doped polysilicon layer 3 is 1 to 2, which can ensure that the volume of the P-type doped polysilicon layer 2 and the volume of the N-type doped polysilicon layer 3 remain within an appropriate range, maintain a high battery efficiency, and facilitate the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.
[0059] As an embodiment of the present invention, the average grain size of the P-type doped polysilicon layer 2 is greater than the average grain size of the N-type doped polysilicon layer 3 .
[0060] In this embodiment, the average grain size of the P-type doped polysilicon layer 2 and the average grain size of the N-type doped polysilicon layer 3 can be measured by X-ray diffraction (XRD), scanning electron microscopy (SEM) or transmission electron microscope (TEM). Among them, the average grain size of the P-type doped polysilicon layer 2 is greater than the average grain size of the N-type doped polysilicon layer 3, which can be understood as the average value of all grain sizes of the P-type doped polysilicon layer 2 per unit area is greater than the average value of all grain sizes of the N-type doped polysilicon layer 3 per unit area; that is, within a unit area, the number of doped polysilicon layers in the N-type doped polysilicon layer 3 is greater, and compared with the N-type doped polysilicon layer 3 per unit area, the P-type doped polysilicon layer 2 per unit area has fewer grain boundaries, thereby improving the compactness of the P-type doped polysilicon layer 2, reducing the square resistance of the P-type doped polysilicon layer 2, reducing current loss, and thus improving battery efficiency. Moreover, the P-type doped polysilicon layer 2 has fewer grain boundaries, which can reduce the metallization damage of the P-type doped polysilicon layer 2, which is also conducive to improving battery efficiency.
[0061] As an embodiment of the utility model, it also includes a first metal electrode 6 in contact with the P-type doped polysilicon layer 2, and a second metal electrode 7 in contact with the N-type doped polysilicon layer 3, and the depth of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is greater than the depth of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3.
[0062] In this embodiment, the depth at which the metal crystals of the first metal electrode 6 penetrate into the P-type doped polysilicon layer 2 is greater than the depth at which the metal crystals of the second metal electrode 7 penetrate into the N-type doped polysilicon layer 3, which can increase the contact area between the first metal electrode 6 and the P-type doped polysilicon layer 2 and enhance the contact effect between the first metal electrode 6 and the P-type doped polysilicon layer 2, thereby improving the conductivity of the first metal electrode 6 and the P-type doped polysilicon layer 2, thereby improving the battery conversion efficiency.
[0063] In the embodiment of the utility model, the first metal electrode 6 and the second metal electrode 7 can be printed by using slurries with different burn-through capabilities, so as to control the depth of metal crystals of the metal electrodes entering the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. For example, the burn-through capability of the slurry of the first metal electrode 6 is greater than the burn-through capability of the slurry of the second metal electrode 7, so that the depth of metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is greater than the depth of metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3.
[0064] In this embodiment, the first metal electrode 6 and the second metal electrode 7 both include silver, glass frit and organic material components; wherein the glass frit includes PbO, Bi 2 O 3 、ZnO、SiO 2 , and at least one of MgO, and the glass content in the first metal electrode 6 is greater than the glass content in the second metal electrode 7, so that the slurry burn-through ability of the first metal electrode 6 is greater than the slurry burn-through ability of the second metal electrode 7, so that the depth of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is greater than the depth of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3.
[0065] As an embodiment of the utility model, the silicon substrate 1 is further provided with a groove 9 between the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. The P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 are physically isolated by the groove 9, which can further enhance the isolation effect between the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, and further reduce the risk of short circuit or leakage. Among them, the width of the groove 9 can be flexibly set according to actual needs, and is not limited here.
[0066] As an embodiment of the utility model, the back-contact solar cell also includes a back passivation film layer 8 located on the surface of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, the first metal electrode 6 passes through the back passivation film layer 8 to contact the P-type doped polysilicon layer 2, and the second metal electrode 7 passes through the back passivation film layer 8 to contact the N-type doped polysilicon layer 3. The back passivation film layer 8 can be used to further improve the conversion efficiency of the back-contact solar cell.
[0067] The present invention also provides a battery assembly, which includes the back-contact solar cell of the above embodiment. It should be noted that the battery assembly and the back-contact solar cell have the same or similar beneficial effects, and the relevant parts between the two can be referenced to each other. In order to avoid repetition, they will not be described here.
[0068] The present invention also provides a photovoltaic system, which includes the battery assembly of the above embodiment. It should be noted that the battery assembly has the same or similar beneficial effects as the back contact solar cell, and the relevant parts between the two can be referenced to each other. In order to avoid repetition, it will not be repeated here.
[0069] A back-contact solar cell provided by an embodiment of the utility model increases the total area of the P-type doped polysilicon layers compared to the N-type doped polysilicon layers by setting the total area of the multiple P-type doped polysilicon layers to be larger than the total area of the multiple N-type doped polysilicon layers, while the area of the N-type doped polysilicon layers remains unchanged, thereby increasing the current collection capacity of the emitter and thus improving the cell efficiency; furthermore, the refractive index of the P-type doped polysilicon layer is set to be smaller than the refractive index of the N-type doped polysilicon layer, while the refractive index of the N-type doped polysilicon layer remains unchanged, thereby reducing the refractive index of the P-type doped polysilicon layer, thereby reducing the parasitic absorption effect of the P region and further improving the cell efficiency.
[0070] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A back contact solar cell, characterized in that: include: N-type silicon substrate; A plurality of P-type doped polysilicon layers are sequentially and spaced apart from each other on the back side of the silicon substrate; A plurality of N-type doped polysilicon layers are sequentially and spaced apart from each other on the back side of the silicon substrate, and the N-type doped polysilicon layers and the P-type doped polysilicon layers are alternately arranged; The total area of the P-type doped polysilicon layer is greater than the total area of the N-type doped polysilicon layer, and the refractive index of the P-type doped polysilicon layer is less than the refractive index of the N-type doped polysilicon layer.
2. The back contact solar cell according to claim 1, characterized in that: An area of at least one of the P-type doped polysilicon layers is greater than an area of any one of the N-type doped polysilicon layers.
3. The back contact solar cell according to claim 1, characterized in that: The number of the P-type doped polysilicon layers is greater than the number of the N-type doped polysilicon layers.
4. The back contact solar cell according to claim 1, characterized in that: The ratio of the total area of the P-type doped polysilicon layer to the total area of the N-type doped polysilicon layer is 1-2 and is not equal to 1.
5. The back contact solar cell according to claim 1, characterized in that: The ratio of the total area of the P-type doped polysilicon layer to the total area of the N-type doped polysilicon layer is 1 to 1.5, and is not equal to 1.
6. The back contact solar cell according to claim 1, characterized in that: The length of each of the P-type doped polysilicon layers is equal to the length of each of the N-type doped polysilicon layers, and the width of each of the P-type doped polysilicon layers is greater than the width of each of the N-type doped polysilicon layers.
7. The back contact solar cell according to claim 1, characterized in that: The ratio of the refractive index of the P-type doped polysilicon layer to the refractive index of the N-type doped polysilicon layer is 0.5-1, and is not equal to 1.
8. The back contact solar cell according to claim 1, characterized in that: The volume of the P-type doped polysilicon layer is greater than the volume of the N-type doped polysilicon layer.
9. A battery assembly, characterized in that: Comprising a back-contact solar cell as described in any one of claims 1 to 8.
10. A photovoltaic system, characterized in that: Comprising the battery assembly as claimed in claim 9.
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