A perovskite crystalline silicon stacked solar cell

Abstract

The utility model provides a perovskite crystalline silicon tandem solar cell, comprising a first metal electrode layer, a first transparent conductive layer, a P-type doped layer, a first intrinsic layer, a silicon substrate layer, a second intrinsic layer, an N-type doped layer, an intermediate connection layer, a hole transport layer, a perovskite absorption layer, an electron transport layer, a second transparent conductive layer, and a second metal electrode layer stacked in sequence; and further comprising: a first passivation layer; located between the hole transport layer and the perovskite absorption layer; and a second passivation layer; located between the perovskite absorption layer and the electron transport layer. The surface / interface defect density of the perovskite absorption layer in the perovskite crystalline silicon tandem solar cell provided by the utility model is low, so that the photoelectric conversion efficiency of the perovskite crystalline silicon tandem solar cell is high; secondly, the perovskite crystalline silicon tandem solar cell has high stability.

Description

Technical Field

[0001] The utility model relates to the technical field of perovskite / crystalline silicon stacked solar cells, in particular to a perovskite crystalline silicon stacked solar cell. Background Art

[0002] As one of the renewable clean energy sources, solar energy resources have the advantages of abundant resources and low cost. Using solar cells to convert solar energy into electrical energy is one of the most effective ways to utilize it. Among them, polycrystalline silicon, monocrystalline silicon and other solar cells have relatively mature industrialization technologies. In recent years, perovskite solar cells have attracted extensive attention from the scientific and industrial communities due to their high photoelectric conversion efficiency, adjustable band gap width and simple preparation methods.

[0003] As one of the structural modes of perovskite solar cells, perovskite / crystalline silicon stacking technology has become an important development direction in the field of photovoltaic technology, and its products have also received widespread attention from the entire industry. The basic principle of this technology is to stack perovskite cells and crystalline silicon cells together, using wide-bandgap perovskite as the top cell to absorb short-wave spectrum; and then using the good long-wavelength response effect of crystalline silicon materials to improve the photoelectric conversion efficiency of solar cells. At present, the preparation of perovskite absorption layer is one of the research focuses of perovskite / crystalline silicon stacked solar cells. The perovskite absorption layer is prone to surface or interface defects, which leads to a decrease in the photoelectric efficiency and stability of solar cell devices. Common measures to reduce defects are: 1. Precursor optimization. Before preparing the perovskite absorption layer, adjust the concentration, solvent ratio and chemical composition of the precursor solution to reduce the defect density; 2. Interface passivation. Use additives such as halogens, small molecules and organic polymers to reduce the defect concentration by using the physical or chemical reaction between perovskite and them.

[0004] However, although there are many effective methods for interface passivation, there are few solutions that can achieve both improved photoelectric conversion efficiency and stability, low cost, and conducive to commercial application and promotion. For example, researchers have proposed a solar cell based on quasi-two-dimensional-two-dimensional perovskite and its preparation method, which spin-coats a layer of amine halide / isopropanol solution on the surface of the quasi-two-dimensional perovskite absorption layer, and then makes a two-dimensional perovskite absorption layer. The surface defects of the quasi-two-dimensional perovskite layer are passivated by the introduction of the two-dimensional perovskite layer. However, its efficiency and stability are still poor, and there are problems such as carrier transport and charge accumulation between the interfaces.

[0005] Therefore, there is an urgent need to provide a perovskite crystalline silicon tandem solar cell to solve the above-mentioned problem of interface defects in the perovskite absorption layer. Utility Model Content

[0006] Therefore, the technical problem to be solved by the present invention is to overcome the problem of low photoelectric conversion efficiency and stability caused by interface defects of the perovskite absorption layer in the existing perovskite crystalline silicon tandem solar cell, thereby providing a perovskite crystalline silicon tandem solar cell.

[0007] The utility model provides a perovskite crystalline silicon stacked solar cell, comprising a first metal electrode layer, a first transparent conductive layer, a P-type doped layer, a first intrinsic layer, a silicon substrate layer, a second intrinsic layer, an N-type doped layer, an intermediate connecting layer, a hole transport layer, a perovskite absorption layer, an electron transport layer, a second transparent conductive layer, and a second metal electrode layer stacked in sequence; and further comprising: a first passivation layer; located between the hole transport layer and the perovskite absorption layer; and a second passivation layer; located between the perovskite absorption layer and the electron transport layer.

[0008] Optionally, the first passivation layer includes a stack of one or more of a lead iodide layer, a cesium iodide layer, a lead bromide layer, a lead chloride layer, a cesium bromide layer and a phenethylammonium iodide layer; the second passivation layer includes a stack of one or more of a magnesium fluoride layer, a lithium fluoride layer and a sodium fluoride layer; the thickness of the first passivation layer is 1nm to 50nm; the thickness of the second passivation layer is 1nm to 50nm.

[0009] Optionally, the first passivation layer is a lead iodide layer with a thickness of 5 nm; the second passivation layer is a lithium fluoride layer with a thickness of 1 nm.

[0010] Optionally, the general structural formula of the perovskite absorption layer is ABX3, A is an organic cation, B is a metal cation, and X is a halogen anion, wherein A includes but is not limited to a methylamino group (MA + ), formamidine group (FA + ) or cesium ion (Cs + ), B includes but is not limited to Pb 2+ Sn 2+ One or a combination of C, including but not limited to F - , C l - Br - and I - One or a combination of the foregoing; the thickness of the perovskite absorption layer is 500nm to 1500nm.

[0011] Optionally, the hole transport layer includes a stack of one or more of a poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] layer, a poly-3-hexylthiophene layer, a nickel oxide layer, a molybdenum oxide layer, a cuprous iodide layer, a cuprous thiocyanate layer, a [2-(3,6-dimethoxy-9H-carbazole-9-yl)ethyl]phosphonic acid layer, a [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphonic acid layer, a [2-(9H-carbazole-9-yl)ethyl]phosphonic acid layer, a [4-(9H-carbazole-9-yl)butyl]phosphonic acid layer and a [4-(3,6-dimethoxy-9H-carbazole-9-yl)butyl]phosphonic acid layer; the thickness of the hole transport layer is 10 nm to 500 nm.

[0012] Optionally, the hole transport layer includes a first hole transport layer and a second hole transport layer; the first hole transport layer is located on the side surface of the intermediate connecting layer away from the silicon substrate layer, and the second hole transport layer is located on the side surface of the first hole transport layer away from the silicon substrate layer, and is located between the first hole transport layer and the first passivation layer; the first hole transport layer is a nickel oxide layer; the second hole transport layer is a [2-(9H-carbazole-9-yl)ethyl]phosphonic acid layer; the thickness of the first hole transport layer is 10nm to 100nm; the thickness of the second hole transport layer is 1nm to 10nm.

[0013] Optionally, it also includes: an electron transport layer modification layer located between the electron transport layer and the second transparent conductive layer; the electron transport layer modification layer includes a zinc oxide layer, a tin dioxide layer, a titanium dioxide layer, a [6,6]-phenyl C61 butyric acid methyl ester layer and a carbon 60 layer, or a stack of several of them; the thickness of the electron transport layer modification layer is 10nm to 500nm; the electron transport layer includes a zinc oxide layer, a tin dioxide layer, a titanium dioxide layer, a [6,6]-phenyl C61 butyric acid methyl ester layer and a carbon 60 layer, or a stack of several of them; the thickness of the electron transport layer is 10nm to 500nm.

[0014] Optionally, it also includes: an anti-reflection layer located on the surface of the second metal electrode layer away from the silicon substrate layer; the anti-reflection layer includes a stack of one or more of magnesium fluoride, lithium fluoride, sodium fluoride and silicon oxide; the thickness of the anti-reflection layer is 100nm to 500nm.

[0015] Optionally, the first metal electrode layer includes a stack of one or more of a silver layer, a gold layer, a copper layer, an aluminum layer, a titanium layer, a chromium layer and a carbon layer; the second metal electrode layer includes a stack of one or more of a silver layer, a gold layer, a copper layer, an aluminum layer, a titanium layer, a chromium layer and a carbon layer; the thickness of the first metal electrode layer is 1000nm to 3000nm; the thickness of the second metal electrode layer is 50nm to 3000nm.

[0016] Optionally, the first transparent conductive layer includes a stack of one or more of an indium tin oxide layer, an indium zinc oxide layer, an aluminum zinc oxide layer, a tungsten-doped indium oxide layer and a cerium-doped indium oxide layer; the second transparent conductive layer includes a stack of one or more of an indium tin oxide layer, an indium zinc oxide layer, an aluminum zinc oxide layer, a tungsten-doped indium oxide layer and a cerium-doped indium oxide layer; the thickness of the first transparent conductive layer is 50nm to 500nm; the thickness of the second transparent conductive layer is 50nm to 500nm.

[0017] The technical solution of the utility model has the following advantages:

[0018] The perovskite crystalline silicon tandem solar cell provided by the utility model has a first passivation layer arranged between the hole transport layer and the perovskite absorption layer, which is equivalent to forming a quasi-two-dimensional perovskite passivation between the hole transport layer and the perovskite absorption layer. The quasi-two-dimensional perovskite passivation can not only effectively form an energy level ladder and reduce the energy level barrier; but also reduce the surface / interface defects of the perovskite absorption layer and reduce the non-radiative recombination of the interface; secondly, a second passivation layer is arranged between the perovskite absorption layer and the electron transport layer. Through the combined action of the first passivation layer and the second passivation layer, the surface / interface defect density of the perovskite absorption layer can be more effectively eliminated, the ability to reduce non-radiative recombination is stronger, and the effect of improving the photoelectric conversion efficiency of the perovskite crystalline silicon tandem solar cell device is better. Specifically, the perovskite crystalline silicon tandem solar cell provided by the utility model has a surface / interface defect density of the perovskite absorption layer reduced by 1.0×10 compared with the perovskite crystalline silicon tandem solar cell in the prior art. 16 ~4.0×10 16 ; The photoelectric conversion efficiency increased by 2% to 4%.

[0019] In addition, a first passivation layer and a second passivation layer are respectively arranged between the hole transport layer and the perovskite absorption layer, and between the perovskite absorption layer and the electron transport layer, which can also improve the contact adhesion between the perovskite absorption layer and the hole transport layer and the electron transport layer, and improve the stability of the perovskite crystalline silicon stacked solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 This is a schematic diagram of the structure of a perovskite crystalline silicon stacked solar cell in an embodiment of the utility model;

[0022] Reference numerals:

[0023] 1-first metal electrode layer; 2-first transparent conductive layer; 3-P-type doped layer; 4-first intrinsic layer; 5-silicon substrate layer; 6-second intrinsic layer; 7-N-type doped layer; 8-intermediate connecting layer; 9-hole transport layer; 91-first hole transport layer; 92-second hole transport layer; 14-first passivation layer; 10-perovskite absorption layer; 15-second passivation layer; 11-electron transport layer; 16-electron transport layer modification layer; 12-second transparent conductive layer; 13-second metal electrode layer; 17-anti-reflection layer. DETAILED DESCRIPTION

[0024] The technical solution of the utility model will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0025] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0026] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0028] refer to Figure 1The present embodiment provides a perovskite crystalline silicon stacked solar cell, comprising a first metal electrode layer 1, a first transparent conductive layer 2, a P-type doped layer 3, a first intrinsic layer 4, a silicon substrate layer 5, a second intrinsic layer 6, an N-type doped layer 7, an intermediate connecting layer 8, a hole transport layer 9, a perovskite absorption layer 10, an electron transport layer 11, a second transparent conductive layer 12, and a second metal electrode layer 13, which are stacked in sequence; and further comprising: a first passivation layer 14; located between the hole transport layer 9 and the perovskite absorption layer 10; a second passivation layer 15; located between the perovskite absorption layer 10 and the electron transport layer 11.

[0029] In this embodiment, a first passivation layer 14 is provided between the hole transport layer 9 and the perovskite absorption layer 10, which is equivalent to forming a quasi-two-dimensional perovskite passivation between the hole transport layer 9 and the perovskite absorption layer 10. The quasi-two-dimensional perovskite passivation can not only effectively form an energy level ladder and reduce the energy level barrier; but also reduce the surface / interface defects of the perovskite absorption layer 10 and reduce the non-radiative recombination of the interface; secondly, a second passivation layer 15 is provided between the perovskite absorption layer 10 and the electron transport layer 11. Through the combined action of the first passivation layer 14 and the second passivation layer 15, the surface / interface defect density of the perovskite absorption layer 10 can be more effectively eliminated, the ability to reduce non-radiative recombination is stronger, and the effect of improving the photoelectric conversion efficiency of the perovskite crystalline silicon stacked solar cell device is better. Specifically, the perovskite crystalline silicon stacked solar cell provided in the present application is reduced by 1.0×10 16 ~4.0×10 16 ; The photoelectric conversion efficiency increased by 2% to 4%.

[0030] In addition, a first passivation layer 14 and a second passivation layer 15 are respectively arranged between the hole transport layer 9 and the perovskite absorption layer 10, and between the perovskite absorption layer 10 and the electron transport layer 11, which can also improve the contact adhesion between the perovskite absorption layer 10 and the hole transport layer 9, the electron transport layer 11, and improve the stability of the perovskite crystalline silicon stacked solar cell.

[0031] In one embodiment, the first passivation layer 14 includes a stack of one or more of a lead iodide layer, a cesium iodide layer, a lead bromide layer, a lead chloride layer, a cesium bromide layer, and a phenethylammonium iodide layer; the second passivation layer 15 includes a stack of one or more of a magnesium fluoride layer, a lithium fluoride layer, and a sodium fluoride layer.

[0032] In one embodiment, the thickness of the first passivation layer 14 is 1 nm to 50 nm, for example, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm or 50 nm; the thickness of the second passivation layer 15 is 1 nm to 50 nm, for example, 1 nm, 10 nm, 20 nm, 30 nm, 40 nm or 50 nm.

[0033] In this embodiment, preferably, the first passivation layer 14 is a lead iodide layer with a thickness of 5 nm; the second passivation layer 15 is a lithium fluoride layer with a thickness of 1 nm. 5 nm of lead iodide can better participate in the crystallization process of the perovskite crystalline silicon stacked solar cell, and well achieve the defect passivation in the body of the perovskite crystalline silicon stacked solar cell, and obtain high photoelectric conversion efficiency; lithium fluoride, as an inorganic lithium salt, can better passivate interface defects, and 1 nm of lithium fluoride can better complete the passivation of surface defects and increase the carrier transmission capacity.

[0034] In one embodiment, the general structural formula of the perovskite absorption layer 10 is ABX3, A is an organic cation, B is a metal cation, and X is a halogen anion, wherein A includes but is not limited to a methylamino group (MA + ), formamidine group (FA + ) or cesium ion (Cs + ), B includes but is not limited to Pb 2+ Sn 2+ One or a combination of C, including but not limited to F － , Cl － Br － and I － Specifically, the perovskite absorption layer includes but is not limited to Cs x FA 1－x PBI3 layer, Cs x FA 1－x－y MA y PbI3 layer, MAPbI3 layer, FA y PbI3 layer or CsPbI3 layer.

[0035] In one embodiment, the thickness of the perovskite absorption layer 10 is 500 nm to 1500 nm, for example, 500 nm, 1000 nm or 1500 nm.

[0036] In one embodiment, the hole transport layer 9 includes a poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] layer, a poly-3-hexylthiophene layer, a nickel oxide layer, a molybdenum oxide layer, a cuprous iodide layer, a cuprous thiocyanate layer, a [2-(3,6-dimethoxy-9H-carbazole-9-yl)ethyl]phosphonic acid layer, a [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphonic acid layer, a [2-(9H-carbazole-9-yl)ethyl]phosphonic acid layer, a [4-(9H-carbazole-9-yl)butyl]phosphonic acid layer and a [4-(3,6-dimethoxy-9H-carbazole-9-yl)butyl]phosphonic acid layer.

[0037] Furthermore, the hole transport layer 9 includes a first hole transport layer 91 and a second hole transport layer 92; the first hole transport layer 91 is located on the surface of the intermediate connection layer 8 away from the silicon substrate layer 5, and the second hole transport layer 92 is located on the surface of the first hole transport layer 91 away from the silicon substrate layer 5, and is located between the first hole transport layer 91 and the first passivation layer 14. The setting of the two hole transport layers can not only better complete the transmission of hole carriers, but also more effectively block electron carriers and complete the collection of carriers.

[0038] In one embodiment, the thickness of the hole transport layer 9 is 10 nm to 500 nm, for example, 10 nm, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm or 500 nm. Specifically, the thickness of the first hole transport layer 91 is 10 nm to 100 nm, for example, 10 nm, 20 nm, 40 nm, 60 nm, 80 nm or 100 nm; the thickness of the second hole transport layer 92 is 1 nm to 10 nm, for example, 1 nm, 2 nm, 4 nm, 6 nm, 8 nm or 10 nm.

[0039] In one embodiment, the electron transport layer 11 includes a zinc oxide layer, a tin dioxide layer, a titanium dioxide layer, a [6,6]-phenyl C61 butyric acid methyl ester layer and a carbon 60 layer, or a stack of several of them.

[0040] In one embodiment, the thickness of the electron transport layer 11 is 10 nm to 500 nm, for example, 10 nm, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.

[0041] The perovskite crystalline silicon stacked solar cell further includes: an electron transport layer modification layer 16 located between the electron transport layer 11 and the second transparent conductive layer 12. The electron transport layer modification layer 16 is used to block hole carriers while completing electron carrier transmission.

[0042] In this embodiment, the electron transport layer modification layer 16 is made of the same material as the electron transport layer 11. Specifically, the electron transport layer modification layer 16 includes a zinc oxide layer, a tin dioxide layer, a titanium dioxide layer, a [6,6]-phenyl C61 butyrate methyl ester layer, and a carbon 60 layer or a stack of several thereof.

[0043] In one embodiment, the thickness of the electron transport layer modification layer 16 is 10 nm to 500 nm, for example, 10 nm, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.

[0044] The perovskite crystalline silicon stacked solar cell further includes: an anti-reflection layer 17 located on the surface of the second metal electrode layer 13 on the side away from the silicon substrate layer 5. Since the refractive index of the second transparent conductive layer is relatively large, part of the visible light is reflected, so the anti-reflection layer 17 can effectively increase the transmittance of visible light, thereby increasing the light absorption probability of the perovskite absorption layer.

[0045] In one embodiment, the anti-reflection layer 17 includes a stack of one or more of magnesium fluoride, lithium fluoride, sodium fluoride and silicon oxide.

[0046] In one embodiment, the anti-reflection layer 17 has a thickness of 100 nm to 500 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.

[0047] In one embodiment, the first metal electrode layer 1 and the second metal electrode layer 13 are made of the same material. Specifically, the first metal electrode layer 1 includes a stack of one or more of a silver layer, a gold layer, a copper layer, an aluminum layer, a titanium layer, a chromium layer and a carbon layer; the second metal electrode layer 13 includes a stack of one or more of a silver layer, a gold layer, a copper layer, an aluminum layer, a titanium layer, a chromium layer and a carbon layer.

[0048] In one embodiment, the thickness of the first metal electrode layer 1 is 1000nm to 3000nm, for example, 1000nm, 1500nm, 2000nm, 2500nm or 3000nm; the thickness of the second metal electrode layer 13 is 50nm to 3000nm, for example, 50nm, 400nm, 800nm, 1000nm, 2000nm or 3000nm.

[0049] In one embodiment, the first transparent conductive layer 2 and the second transparent conductive layer 12 are made of the same material. Specifically, the first transparent conductive layer 2 includes a stack of one or more of an indium tin oxide layer, an indium zinc oxide layer, an aluminum zinc oxide layer, a tungsten-doped indium oxide layer, and a cerium-doped indium oxide layer; the second transparent conductive layer 12 includes a stack of one or more of an indium tin oxide layer, an indium zinc oxide layer, an aluminum zinc oxide layer, a tungsten-doped indium oxide layer, and a cerium-doped indium oxide layer.

[0050] In one embodiment, the thickness of the first transparent conductive layer 2 is 50nm-500nm, for example, 50nm, 100nm, 200nm, 300nm, 400nm or 500nm; the thickness of the second transparent conductive layer 12 is 50nm-500nm, for example, 50nm, 100nm, 200nm, 300nm, 400nm or 500nm.

[0051] In one embodiment, the first intrinsic layer 4 includes an i-type hydrogenated amorphous silicon layer; and the second intrinsic layer 6 includes an i-type hydrogenated amorphous silicon layer.

[0052] In one embodiment, the P-type doping layer 3 includes a P-type amorphous silicon doping layer or a P-type microcrystalline silicon doping layer; and the N-type doping layer 7 includes an N-type amorphous silicon doping layer or an N-type microcrystalline silicon doping layer.

[0053] In one embodiment, the thickness of the first intrinsic layer 4 is 5nm to 50nm, and the thickness of the P-type doped layer 3 is 5nm to 30nm, for example, 5nm, 10nm, 20nm or 30nm; the thickness of the second intrinsic layer 6 is 5nm, and the thickness of the N-type doped layer 7 is 5nm to 30nm, for example, 5nm, 10nm, 20nm or 30nm.

[0054] In one embodiment, the intermediate connection layer 8 includes a transparent conductive oxide layer; the transparent conductive oxide layer includes one or more stacked layers of an indium tin oxide layer, a fluorine-doped tin oxide layer, and an aluminum-doped zinc oxide layer.

[0055] In one embodiment, the intermediate connection layer 8 has a thickness of 100 nm to 500 nm, for example, 100 nm, 200 nm, 300 nm, 400 nm or 500 nm.

[0056] This embodiment also provides a method for preparing a perovskite crystalline silicon tandem solar cell, which comprises the following steps:

[0057] Step 1: providing a silicon substrate layer;

[0058] Step 2: forming a first intrinsic layer, a P-type doped layer, a first transparent conductive layer and a first metal electrode layer in sequence on a surface of one side of the silicon substrate;

[0059] Specifically, the processes for forming the first intrinsic layer 4 and the P-type doped layer 3 both adopt plasma enhanced chemical vapor deposition processes; the process for forming the first transparent conductive layer 2 includes one of a magnetron sputtering process, a vacuum evaporation process or a reactive plasma deposition process; the process for forming the first metal electrode layer 1 includes one of a magnetron sputtering process, a vacuum evaporation process, a reactive plasma deposition process and a printing process.

[0060] Step 3: forming a second intrinsic layer, an N-type doping layer and an intermediate connection layer in sequence on the other side surface of the silicon substrate;

[0061] Specifically, the processes for forming the second intrinsic layer 6 and the N-type doped layer 7 both adopt plasma enhanced chemical vapor deposition process; the process for forming the intermediate connection layer 8 includes one of magnetron sputtering process, vacuum evaporation process, reactive plasma deposition process or chemical vapor deposition process.

[0062] Step 4: forming a hole transport layer on a surface of the intermediate connection layer away from the silicon substrate layer;

[0063] Preferably, before forming the hole transport layer 9 on the surface of the intermediate connecting layer 8 away from the silicon substrate layer 5, the intermediate connecting layer 8 is treated with an ultraviolet-ozone machine (UV-O3) for 10 minutes to 30 minutes, for example, 10 minutes, 20 minutes or 30 minutes.

[0064] Furthermore, a first hole transport layer 91 and a second hole transport layer 92 are sequentially formed on the surface of the intermediate connecting layer 8 on a side away from the silicon substrate layer 5; specifically, before the first hole transport layer 91 is formed on the surface of the intermediate connecting layer 8 on a side away from the silicon substrate layer 5, the intermediate connecting layer is treated with an ultraviolet-ozone machine (UV-O3) for 10 minutes to 30 minutes.

[0065] The process for forming the first hole transport layer 91 includes a spin coating process or a magnetron sputtering process; the process for forming the second hole transport layer 92 includes a spin coating process. In the present embodiment, the process for forming the first hole transport layer 91 adopts a magnetron sputtering process; the process for forming the second hole transport layer 92 adopts a spin coating process. Specifically, in the process for forming the first hole transport layer 91, the substrate prepared in step 3 is placed in a magnetron sputtering device, and the device parameters are controlled to perform magnetron sputtering. It can be known that the parameters of the magnetron sputtering device are conventionally defined in the art and are not described in detail here; in the process for forming the second hole transport layer 92, the spin coating solution is evenly spin coated on the surface of one side of the first hole transport layer 91 away from the silicon substrate layer 5, and then annealing is performed. Among them, the spin coating rotation speed is 1000rpm~5000rpm, for example, 1000rpm, 2000rpm, 3000rpm, 4000rpm or 5000rpm; the spin coating time is 10s~100s, for example, 10s, 20s, 40s, 60s, 80s or 100s; the annealing temperature is 50℃~300℃, for example, 50℃, 100℃, 200℃ or 300℃; the annealing time is 5min~50min, for example, 5min, 10min, 20min, 30min, 40min or 50min.

[0066] Step 5: forming a first passivation layer on a surface of the hole transport layer away from the silicon substrate layer;

[0067] The process of forming the first passivation layer 14 includes an evaporation process. Specifically, the first passivation material is evaporated to the surface of the second hole transport layer 92 away from the silicon substrate layer 5; wherein the parameters used in the evaporation process include: a vacuum degree of 5×10 －5 Pa~1×10 －3 Pa, for example, 5×10 －5 Pa, 4×10 －4 Pa or 1×10 －3 Pa, the temperature is 200°C to 1500°C, for example, 200°C, 500°C, 1000°C or 1500°C, and the rate is For example or

[0068] Preferably, the material of the first passivation layer 14 is lead iodide; and the thickness of the first passivation layer 14 is 5 nm.

[0069] Step 6: forming a perovskite absorption layer on a surface of the first passivation layer away from the silicon substrate layer;

[0070] The process of forming the perovskite absorption layer 10 includes a spin coating process, a spray coating process, a printing process or an evaporation process, or a combination of these processes.

[0071] In this embodiment, the process of forming the perovskite absorption layer 10 adopts a combination of an evaporation process and a spin coating process. Specifically, in one embodiment, the step of forming the perovskite absorption layer 10 on the surface of the first passivation layer 14 away from the silicon substrate layer 5 includes: forming an inorganic salt layer on the surface of the first passivation layer 14 away from the silicon substrate layer 5 by an evaporation process; providing a mixed solution of an organic salt solution and an isopropanol solution, and spin coating the mixed solution of the organic salt solution and the isopropanol solution on the surface of the inorganic salt layer away from the first passivation layer 14 by a spin coating process, and then performing an annealing treatment.

[0072] Furthermore, the step of spin coating a mixed solution of an organic salt solution and an isopropanol solution on the surface of the inorganic salt layer away from the first passivation layer 14 by a spin coating process includes: uniformly coating the mixed solution of an organic salt solution and an isopropanol solution on the surface of the inorganic salt layer away from the first passivation layer 14, and then performing static spin coating.

[0073] In one embodiment, the parameters of the evaporation process include: a vacuum degree of 5×10 －5 ~1×10 －3 Pa, for example, 5×10 －5 Pa, 4×10 －4 Pa or 1×10 －3 Pa, the temperature is 200℃~700℃, for example, 200℃, 500℃ or 700℃, and the rate is For example or

[0074] In one embodiment, the parameters of the spin coating process include: a rotation speed of 1200rpm to 6000rpm, for example, 1200rpm, 2400rpm, 3600rpm, 5400rpm or 6000rpm; a time of 20s to 120s, for example, 20s, 50s, 60s, 80s, 100s or 120s; in the mixed solution of the provided organic salt solution and the isopropanol solution, the volume of the organic salt solution is 50μL to 500μL, for example, 50μL, 100μL, 300μL or 500μL.

[0075] In one embodiment, the annealing temperature is 50° C. to 150° C., such as 50° C., 100° C. or 150° C.; the annealing time is 5 min to 40 min, such as 5 min, 10 min, 20 min, 30 min or 40 min.

[0076] In one embodiment, the inorganic salt layer includes one or a combination of lead iodide layer, lead bromide layer, cesium iodide layer, lead chloride layer and cesium bromide layer; the organic salt in the organic salt solution includes one or a combination of methyl iodide, methylamine iodide, methyl ether bromide and methylamine chloride.

[0077] In one embodiment, the thickness of the perovskite absorption layer 10 is 500nm to 1500nm, for example, 500nm, 1000nm or 1500nm; wherein the thickness of the inorganic salt layer is 100nm to 1000nm, for example, 100nm, 300nm, 600nm, 900nm or 1000nm.

[0078] Step 7: forming a second passivation layer on a surface of the perovskite absorption layer away from the silicon substrate layer;

[0079] The process of forming the second passivation layer 15 includes an evaporation process. Specifically, the second passivation material is evaporated to the surface of the perovskite absorption layer 10 away from the silicon substrate layer 5; wherein the parameters used in the evaporation process include: a vacuum degree of 5×10 －5 Pa~1×10 －3 Pa, for example, 5×10 －5 Pa, 4×10 －4 Pa or 1×10 －3 Pa, the temperature is 200°C to 1500°C, for example, 200°C, 500°C, 1000°C or 1500°C, and the rate is For example or

[0080] Preferably, the material of the second passivation layer 15 is lithium fluoride; and the thickness of the second passivation layer 15 is 1 nm.

[0081] Step eight: forming an electron transport layer, a second transparent conductive layer, and a second metal electrode layer in sequence on a surface of the second passivation layer that is away from the silicon substrate layer.

[0082] Preferably, after the electron transport layer 11 is sequentially formed on the surface of the second passivation layer 15 away from the silicon substrate layer 5 and before the second transparent conductive layer 12 is formed, it also includes: forming an electron transport layer modification layer 16 on the surface of the electron transport layer 11 away from the silicon substrate layer 5.

[0083] The process for forming the electron transport layer 11 includes a spin coating process, a spray coating process, a printing process, an evaporation process, a magnetron sputtering process, a chemical vapor deposition process or an atomic layer deposition process, or a combination of these processes. In this embodiment, the process for forming the electron transport layer 11 adopts an evaporation process; specifically, the electron transport layer material is evaporated to the surface of the second passivation layer 15 away from the silicon substrate layer 5; wherein the parameters adopted by the evaporation process include: the vacuum degree is 5×10 －5 Pa~1×10 －3 Pa, for example, 5×10 －5 Pa, 4×10 －4 Pa or 1×10 －3 Pa, the temperature is 100°C to 700°C, for example, 100°C, 300°C, 500°C or 700°C, and the rate is For example or

[0084] The process for forming the electron transport layer modification layer 16 includes a spin coating process, a spray coating process, a printing process, an evaporation process, a magnetron sputtering process, a chemical vapor deposition process or an atomic layer deposition process, or a combination of these processes. In this embodiment, the process for forming the electron transport layer modification layer 16 adopts an atomic layer deposition process; specifically, the electron transport layer modification layer material is deposited onto the surface of the electron transport layer 11 away from the silicon substrate layer 5 using an atomic layer deposition device; wherein the parameters adopted by the atomic layer deposition process include: a vacuum degree of 5×10 －5 Pa~1×10 －4 Pa, for example, 5×10 －5 Pa, 4×10 －4 Pa or 1×10 －4 Pa, the pipe temperature is 50℃~150℃, for example, 50℃, 100℃ or 150℃, the chamber temperature is 40℃~150℃, for example, 40℃, 60℃, 80℃, 100℃ or 150℃, the rate is For example or

[0085] The process for forming the second transparent conductive layer 12 includes one or a combination of a magnetron sputtering process, a reactive plasma deposition process, a chemical vapor deposition process or an evaporation process. In this embodiment, the process for forming the second transparent conductive layer 12 adopts a magnetron sputtering process; specifically, the second transparent conductive layer material is evaporated to the surface of the electron transport layer modification layer 16 on one side away from the silicon substrate layer 5.

[0086] In one embodiment, the process of forming the second metal electrode layer 13 includes an evaporation process. The parameters used in the evaporation process include: a vacuum degree of 5×10 －5 Pa~1×10 －3 Pa, for example, 5×10 －5 Pa, 4×10 －4 Pa or 1×10 －3 Pa, the temperature is 500°C to 2000°C, for example, 500°C, 1000°C, 1500°C or 2000°C, and the rate is For example or

[0087] Step nine: forming an anti-reflection layer on a surface of the second metal electrode layer away from the silicon substrate layer;

[0088] The process for forming the anti-reflection layer 17 includes one of an evaporation process, a magnetron sputtering process, and a chemical vapor deposition process. In this embodiment, the process for forming the anti-reflection layer 17 adopts an evaporation process; specifically, the anti-reflection layer material is evaporated to the surface of the second metal electrode layer 13 away from the silicon substrate layer 5 to form the anti-reflection layer; wherein the parameters adopted by the evaporation process include: the vacuum degree is 5×10 －5 Pa~5×10 －4 Pa, for example, 5×10 －5 Pa, 3×10 －5 Pa or 5×10 －4 Pa, the temperature is 500°C to 2000°C, for example, 500°C, 1000°C, 1500°C or 2000°C, and the rate is For example or

[0089] In summary, the present application provides a method for preparing a perovskite crystalline silicon tandem solar cell, which adopts a high-precision evaporation process to form a double passivation layer structure (the first passivation layer 14 and the second passivation layer 15, respectively) between the hole transport layer 9 and the perovskite absorption layer 10, and between the perovskite absorption layer 10 and the electron transport layer 11, which can improve the uniformity and stability of the first passivation layer 14 and the second passivation layer 15; in this way, the uniform and stable first passivation layer 14 and the second passivation layer 15 can interact with each other, which can more effectively eliminate the surface / interface defect density of the perovskite absorption layer 10, and has a stronger ability to reduce non-radiative recombination, and has a better effect on improving the photoelectric conversion efficiency of the perovskite crystalline silicon tandem solar cell device; secondly, it can also improve the contact viscosity between the perovskite absorption layer and the hole transport layer and the electron transport layer, and improve the stability of the perovskite crystalline silicon tandem solar cell.

[0090] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention of the utility model.

Claims

1. A perovskite crystalline silicon stacked solar cell, comprising a first metal electrode layer, a first transparent conductive layer, a P-type doped layer, a first intrinsic layer, a silicon substrate layer, a second intrinsic layer, an N-type doped layer, an intermediate connecting layer, a hole transport layer, a perovskite absorption layer, an electron transport layer, a second transparent conductive layer, and a second metal electrode layer stacked in sequence; characterized in that: Also includes: a first passivation layer; Located between the hole transport layer and the perovskite absorption layer; a second passivation layer; Located between the perovskite absorption layer and the electron transport layer.

2. The perovskite crystalline silicon tandem solar cell according to claim 1, characterized in that: The first passivation layer comprises a stack of one or more of a lead iodide layer, a cesium iodide layer, a lead bromide layer, a lead chloride layer, a cesium bromide layer and a phenethylammonium iodide layer; The second passivation layer comprises a stack of one or more of a magnesium fluoride layer, a lithium fluoride layer and a sodium fluoride layer; The thickness of the first passivation layer is 1 nm to 50 nm; the thickness of the second passivation layer is 1 nm to 50 nm.

3. The perovskite crystalline silicon tandem solar cell according to claim 2, characterized in that: The first passivation layer is a lead iodide layer with a thickness of 5 nm; the second passivation layer is a lithium fluoride layer with a thickness of 1 nm.

4. The perovskite crystalline silicon tandem solar cell according to claim 1, characterized in that: The thickness of the perovskite absorption layer is 500nm-1500nm.

5. The perovskite crystalline silicon tandem solar cell according to claim 1, characterized in that: The hole transport layer comprises a stack of one or more of a poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] layer, a poly-3-hexylthiophene layer, a nickel oxide layer, a molybdenum oxide layer, a cuprous iodide layer, a cuprous thiocyanate layer, a [2-(3,6-dimethoxy-9H-carbazole-9-yl)ethyl]phosphonic acid layer, a [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphonic acid layer, a [2-(9H-carbazole-9-yl)ethyl]phosphonic acid layer, a [4-(9H-carbazole-9-yl)butyl]phosphonic acid layer and a [4-(3,6-dimethoxy-9H-carbazole-9-yl)butyl]phosphonic acid layer; The thickness of the hole transport layer is 10 nm to 500 nm.

6. The perovskite crystalline silicon tandem solar cell according to claim 5, characterized in that: The hole transport layer includes a first hole transport layer and a second hole transport layer; the first hole transport layer is located on a side surface of the intermediate connection layer away from the silicon substrate layer, and the second hole transport layer is located on a side surface of the first hole transport layer away from the silicon substrate layer, and is located between the first hole transport layer and the first passivation layer; The first hole transport layer is a nickel oxide layer; the second hole transport layer is a [2-(9H-carbazole-9-yl)ethyl]phosphonic acid layer; The thickness of the first hole transport layer is 10 nm to 100 nm; the thickness of the second hole transport layer is 1 nm to 10 nm.

7. The perovskite crystalline silicon tandem solar cell according to claim 1, characterized in that: It also includes: an electron transport layer modification layer located between the electron transport layer and the second transparent conductive layer; The electron transport layer modification layer includes a zinc oxide layer, a tin dioxide layer, a titanium dioxide layer, a [6,6]-phenyl C61 butyric acid methyl ester layer and a carbon 60 layer, or a stack of several thereof; The thickness of the electron transport layer modification layer is 10nm to 500nm; The electron transport layer comprises a zinc oxide layer, a tin dioxide layer, a titanium dioxide layer, a [6,6]-phenyl C61 butyric acid methyl ester layer and a carbon 60 layer, or a stack of several thereof; The thickness of the electron transport layer is 10 nm to 500 nm.

8. The perovskite crystalline silicon tandem solar cell according to claim 1, characterized in that: Also includes: an anti-reflection layer located on a surface of the second metal electrode layer on a side away from the silicon substrate layer; The anti-reflection layer comprises a stack of one or more of magnesium fluoride, lithium fluoride, sodium fluoride and silicon oxide; The thickness of the anti-reflection layer is 100nm-500nm.

9. The perovskite crystalline silicon tandem solar cell according to claim 1, characterized in that: The first metal electrode layer includes a stack of one or more of a silver layer, a gold layer, a copper layer, an aluminum layer, a titanium layer, a chromium layer and a carbon layer; the second metal electrode layer includes a stack of one or more of a silver layer, a gold layer, a copper layer, an aluminum layer, a titanium layer, a chromium layer and a carbon layer; The thickness of the first metal electrode layer is 1000nm to 3000nm; the thickness of the second metal electrode layer is 50nm to 3000nm.

10. The perovskite crystalline silicon tandem solar cell according to claim 1, characterized in that: The first transparent conductive layer comprises a stack of one or more selected from the group consisting of an indium tin oxide layer, an indium zinc oxide layer, an aluminum zinc oxide layer, a tungsten-doped indium oxide layer, and a cerium-doped indium oxide layer; the second transparent conductive layer comprises a stack of one or more selected from the group consisting of an indium tin oxide layer, an indium zinc oxide layer, an aluminum zinc oxide layer, a tungsten-doped indium oxide layer, and a cerium-doped indium oxide layer; The thickness of the first transparent conductive layer is 50 nm to 500 nm; the thickness of the second transparent conductive layer is 50 nm to 500 nm.

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