Test fixture and test system applied to SOP23 packaging chip
By designing a test fixture containing multiple external test needles and internal test needles, the testing problem of SOP23 packaged chip was solved, and the accuracy, reliable testing and productivity of the chip were improved.
Patent Information
- Application Number
- CN202420620803.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-28
- Publication Date
- 2025-04-04
- Estimated Expiration
- 2034-03-28
AI Technical Summary
It is difficult to design a test fixture suitable for SOP23 package chips in the prior art, especially due to the particularity of the pin count and arrangement method, the design of the test fixture is difficult.
A test fixture including a first and second side test structures is designed. Each side test structure includes a plurality of external test pins and internal test pins. The external test pins and internal test pins are connected and fixed through plastic sealing structures and fixed structures, and can form a Kelvin test loop with the pins of the SOP23 package chip.
Accurate and reliable testing of SOP23 packaged chips is achieved, the chip productivity is improved, and the chip's electrical impedance or voltage can be measured more accurately through Kelvin testing.
Smart Images
Figure CN222719664U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic chip testing, and in particular to a test fixture and a test system for SOP23 packaged chips. Background Art
[0002] SOP (Small Out-Line Package) is a very common component packaging form, which is one of the surface mount packages. The pins are led out from both sides of the package in a seagull wing shape (L shape), and the materials are plastic and ceramic. Since SOP packages have a variety of sizes and the number and arrangement of pins are also different, different test fixtures need to be designed for SOP packages of different sizes, numbers of pins, and arrangements.
[0003] For example, reference Figure 1 , is a top view of a sample of the SOP23 package. The pins are led out from both sides of the package in a seagull-wing shape. The number of pins on the first side is 16 (#1 to #16) and the pins are arranged at equal intervals. The number of pins on the second side is 7 (#17 to #23) and the pins are arranged at non-equal intervals. How to design a method for Figure 1 The test fixture of the SOP23 package shown has become a problem that needs to be solved urgently. Utility Model Content
[0004] Based on this, it is necessary to provide a test fixture and test system that can test SOP23 packaged chips to address the above technical problems.
[0005] In a first aspect, the present application provides a test fixture for a SOP23 packaged chip, characterized in that it includes a first side test structure and a second side test structure;
[0006] The first side test structure and the second side test structure each include at least a plurality of external test pins and a plurality of internal test pins having the same number as the external test pins, wherein the number of the external test pins in the first side test structure and the number of the external test pins in the second side test structure are respectively the same as the number of pins on the corresponding side of the SOP23 packaged chip;
[0007] Wherein, a plurality of the external test pins are arranged side by side; each of the external test pins comprises a first portion extending along a first direction and a second portion extending along a second direction, the second portion is connected to a first end of the first portion, and the second direction is perpendicular to the first direction;
[0008] A plurality of the inner test needles are arranged side by side; each of the inner test needles comprises a body extending along the first direction, the body is opposite to the first portion, and is located within a plane surrounded by the first portion and the second portion and has a spacing with the first portion and the second portion respectively;
[0009] The second portion of the outer test pin and the corresponding body of the inner test pin are respectively used to contact different positions of the same pin of the SOP23 packaged chip at the same time to form a Kelvin test loop with the pin.
[0010] In one of the embodiments, the first side test structure and the second side test structure both further include a plastic packaging structure;
[0011] The plastic encapsulation structure is located on the side where the second end of the first part of each of the external test pins is located, and the second end of each of the first parts and the corresponding end of the body of each of the internal test pins are plastic encapsulated. The plastic encapsulation exposes the surface of the second end of each of the first parts away from the body and exposes the surface of the corresponding end of each of the bodies away from the first part, wherein the exposed surface is used to electrically connect to an external test circuit board, and the test function of the test circuit board is adapted to the items to be tested of the SOP23 packaged chip.
[0012] In one of the embodiments, the first side test structure and the second side test structure each further include a first fixing structure;
[0013] Each of the outer test needles and each of the inner test needles passes through the first fixing structure so as to fix each of the outer test needles and each of the inner test needles through the first fixing structure, and the first fixing structure is in contact with the plastic packaging structure.
[0014] In one of the embodiments, the first side test structure and the second side test structure each further include a second fixing structure;
[0015] The second fixing structure is located between each of the outer testing needles and each of the inner testing needles, and is mechanically connected to each of the outer testing needles and each of the inner testing needles.
[0016] In one embodiment, the first portion, the second portion and the main body are all in the shape of a cuboid.
[0017] In one embodiment, the thickness and width of the first portion, the second portion and the body are the same.
[0018] In one embodiment, the thickness of the first portion, the second portion and the main body is (0.2±0.02) mm; the width of the first portion, the second portion and the main body is (0.8±0.02) mm.
[0019] In one embodiment, the vertical distance between the first portion and the main body is (0.1±0.05) mm.
[0020] In one embodiment, the arrangement spacing of each external test pin in the first side test structure and the arrangement spacing of each external test pin in the second side test structure are respectively the same as the arrangement spacing of each pin on the corresponding side of the SOP23 packaged chip, and the arrangement spacing of each internal test pin in the first side test structure and the arrangement spacing of each internal test pin in the second side test structure are respectively the same as the arrangement spacing of each pin on the corresponding side of the SOP23 packaged chip.
[0021] In a second aspect, the present application further provides a test system for SOP23 packaged chips, characterized in that it comprises: a test device, a test circuit board, and a test fixture as described in the first aspect above;
[0022] Wherein, the test equipment is connected to the test circuit board, and the test function of the test circuit board is adapted to the items to be tested of the SOP23 packaged chip;
[0023] The second portion of the outer test pin and the end of the body of the corresponding inner test pin close to the second portion are respectively used to contact different positions of a pin of the SOP23 packaged chip at the same time to form a Kelvin test loop with the pin;
[0024] The second end of the first portion of each of the outer test pins and the end of the body of each of the inner test pins away from the second portion are both connected to the test circuit board.
[0025] The test fixture and test system applied to the SOP23 packaged chip include a first side test structure and a second side test structure; the first side test structure and the second side test structure both include at least a plurality of external test pins and a plurality of internal test pins with the same number as the external test pins, wherein the number of external test pins in the first side test structure and the number of external test pins in the second side test structure are respectively the same as the number of pins on the corresponding side of the SOP23 packaged chip. Further, a plurality of external test pins are arranged side by side, each external test pin includes a first portion extending along a first direction and a second portion extending along a second direction, the second portion is connected to the first end of the first portion, and the second direction is perpendicular to the first direction; a plurality of internal test pins are arranged side by side, each internal test pin includes a body extending along the first direction, the body is opposite to the first portion, and is located within the plane surrounded by the first portion and the second portion and has a spacing between the first portion and the second portion respectively; the second portion of an external test pin and the body of a corresponding internal test pin are respectively used to contact different positions of the same pin of the SOP23 packaged chip at the same time to form a Kelvin test loop with the pin. In this way, the embodiment of the present application realizes a test fixture for SOP23 packaged chips, which is beneficial to improving the productivity of SOP23 packaged chips, and the test fixture can be used to implement Kelvin test on SOP23 packaged chips, thereby achieving accurate and reliable testing of SOP23 packaged chips. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0027] Figure 1 A top view of a sample of SOP23 package;
[0028] Figure 2 for Figure 1 The top view of the structure of the SOP23 package is shown;
[0029] Figure 3 for Figure 2 The structural side view of the SOP23 package is shown;
[0030] Figure 4 The figure is a schematic diagram of the structure of a test fixture applied to a SOP23 packaged chip in one embodiment. DETAILED DESCRIPTION
[0031] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0032] The test fixture for SOP23 packaged chips provided in the embodiment of the present application can be applied to Figure 1 For example, refer to the SOP23 package. Figure 2 ,yes Figure 1 The structural top view of the SOP23 package shown in the figure shows that the length and width (excluding pins) of the SOP23 package can be (29.00±0.2) mm and 12.178 mm respectively; the spacing of the pins on the first side can be 1.778 mm, the length of the coverage range of all pins can be (26.67±0.2) mm, and the length of the coverage range of half of the pins can be 13.400 mm; the length of the coverage range of a portion of the pins on the second side can be (12.225±0.2) mm, and the length of the coverage range of the remaining pins can be (13.125±0.2) mm. For example, refer to Figure 3 ,yes Figure 2The structural side view of the SOP23 package is shown. The width of the SOP23 package including the pins can be 17mm, the vertical distance between the lowest part of the pins on one side and the horizontal plane can be 1.85mm, and the vertical distance between the highest part of the pins on the other side and the horizontal plane can be 3.15mm. For other dimensions, see Figure 3 Indicated in the middle.
[0033] In one embodiment, reference Figure 4 , a test fixture for SOP23 packaged chips is provided, the test fixture comprising a first side test structure 410 and a second side test structure 420. The first side test structure 410 and the second side test structure 420 both comprise at least a plurality of external test pins 401 and a plurality of internal test pins 402 having the same number as the external test pins 401, wherein the number of the external test pins 401 in the first side test structure 410 and the number of the external test pins 401 in the second side test structure 420 are respectively the same as the number of pins on the corresponding side of the SOP23 packaged chip.
[0034] For example, in combination Figure 1 and Figure 4 In the first side test structure 410, the number of external test pins 401 is the same as the number of internal test pins 402, and the external test pins 401 correspond to the internal test pins 402 one by one. The number of external test pins 401 can be the same as the number of pins on the first side of the SOP23 packaged chip, which is 16. In this way, when testing the SOP23 packaged chip, the first side test structure 410 can be used to contact the corresponding pins on the first side of the SOP23 packaged chip; in the second side test structure 420, the number of external test pins 401 is the same as the number of internal test pins 402, and the external test pins 401 correspond to the internal test pins 402 one by one. The number of external test pins 401 can be the same as the number of pins on the second side of the SOP23 packaged chip, which is 7. In this way, when testing the SOP23 packaged chip, the second side test structure 420 can be used to contact the corresponding pins on the second side of the SOP23 packaged chip.
[0035] A plurality of outer test pins 401 are arranged side by side; each outer test pin 401 includes a first portion 4011 extending along a first direction and a second portion 4012 extending along a second direction, the second portion 4012 being connected to a first end of the first portion 4011, and the second direction being perpendicular to the first direction. The length of the first portion 4011 along the first direction may be much greater than the length of the second portion 4012 along the second direction. A plurality of inner test pins 402 are arranged side by side; each inner test pin 402 includes a body 4021 extending along the first direction, the body 4021 being opposite to the first portion 4011, and being located within a plane surrounded by the first portion 4011 and the second portion 4012 and having a spacing between the first portion 4011 and the second portion 4012, respectively. The body 4021 and the vertical projection of the first portion 4011 in the same direction coincide, and the length of the body 4021 along the first direction may be similar to the length of the first portion 4011 along the first direction.
[0036] The second portion 4012 of an outer test pin 401 and the body 4021 of a corresponding inner test pin 402 are respectively used to contact different positions of the same pin of the SOP23 package chip at the same time to form a Kelvin test loop with the pin. Figure 3 and Figure 4 The end A of the second part 4012 of an outer test pin 401 and the end B of the body 4021 of a corresponding inner test pin 402 close to the second part 4012 can respectively contact the position C and the position D of the same pin at the same time to form a Kelvin test circuit with the pin, thereby realizing the Kelvin test of the pin.
[0037] In summary, the embodiment of the present application realizes a test fixture for SOP23 packaged chips, which is beneficial to improving the productivity of SOP23 packaged chips, and the test fixture can be used to implement Kelvin test on SOP23 packaged chips, thereby achieving accurate and reliable testing of SOP23 packaged chips.
[0038] In one embodiment, continue to refer to Figure 4 The first side test structure 410 and the second side test structure 420 both further include a plastic packaging structure 403; the plastic packaging structure 403 is located on the side where the second end of the first part 4011 of each outer test needle 401 is located, and plastic packaging is performed on the second end of each first part 4011 and the corresponding end of the body 4021 of each inner test needle 402.
[0039] In one embodiment, the plastic packaging may expose part or all of the surface of the second end of each first portion 4011 away from the body 4021 ( Figure 4 The exposure of the surface is not shown in the figure) and the corresponding end of each body 4021 may also expose part or all of the surface away from the first part 4011 ( Figure 4The exposed surface is not shown in the figure), wherein the exposed surface is used to electrically connect to an external test circuit board, for example, the exposed surface ( Figure 4 The exposed surface is not exemplarily shown in the figure) and is electrically connected to a test circuit board through an adapter, and the test function of the test circuit board is adapted to the items to be tested of the SOP23 packaged chip.
[0040] In this embodiment, the outer test pin 401 and the inner test pin 402 are encapsulated by the plastic encapsulation structure 403, which can play the role of encapsulation, support, insulation and fixation of the outer test pin 401 and the inner test pin 402, and also facilitate the electrical connection of the outer test pin 401 and the inner test pin 402 to the external test circuit board. The material of the plastic encapsulation structure 403 can be epoxy resin.
[0041] In one embodiment, continue to refer to Figure 4 , the first side test structure 410 and the second side test structure 420 both further include a first fixing structure 404; each outer test pin 401 and each inner test pin 402 all penetrate the first fixing structure 404, so as to fix each outer test pin 401 and each inner test pin 402 through the first fixing structure 404, and the first fixing structure 404 is in contact with the plastic packaging structure 403. The material of the first fixing structure 404 and the material of the plastic packaging structure 403 may be different, and the specific shape of the first fixing structure 404 is not limited in this embodiment, as long as each outer test pin 401 and each inner test pin 402 are well fixed.
[0042] In one embodiment, continue to refer to Figure 4 , the first side test structure 410 and the second side test structure 420 both further include a second fixing structure 405; the second fixing structure 405 is located between each outer test pin 401 and each inner test pin 402, and is mechanically connected to each outer test pin 401 and each inner test pin 402, so as to further fix each outer test pin 401 and each inner test pin 402 through the second fixing structure 405. The material of the second fixing structure 405 can be the same as that of the plastic packaging structure 403, and the specific shape of the second fixing structure 405 is not limited in this embodiment, as long as each outer test pin 401 and each inner test pin 402 are well fixed.
[0043] In one embodiment, continue to refer to Figure 4 The first part 4011, the second part 4012 and the main body 4021 are all in the shape of a rectangular parallelepiped, so as to facilitate good contact between the outer test needle 402 and the inner test needle 402 and the chip pin, and make the first part 4011, the second part 4012 and the main body 4021 simple in structure and easy to implement.
[0044] In one embodiment, continue to refer to Figure 4The thickness and width of the first part 4011, the second part 4012 and the main body 4021 are the same, so that the structure of the test fixture is simple and easy to implement.
[0045] In one embodiment, continue to refer to Figure 4 The thickness of the first part 4011, the second part 4012 and the main body 4021 can be (0.2±0.02) mm, and the width of the first part 4011, the second part 4012 and the main body 4021 can be (0.8±0.02) mm. In this way, the test fixture can achieve reliable contact with the pins of the SOP23 packaged chip and reliable detection, while the structure of the test fixture is simple and easy to implement.
[0046] In one embodiment, continue to refer to Figure 4 The vertical distance between the first part 4011 and the main body 4021 is (0.1±0.05) mm, so that when testing the SOP23 packaged chip, the external test pin 401 and the corresponding internal test pin 402 can simultaneously achieve good contact with the same pin of the SOP23 packaged chip, and the external test pin 401 and the corresponding internal test pin 402 will not interfere with or affect each other.
[0047] In one embodiment, continue to refer to Figure 4 The arrangement spacing of each external test pin 401 in the first side test structure 410 and the arrangement spacing of each external test pin 401 in the second side test structure 420 are respectively the same as the arrangement spacing of each pin on the corresponding side of the SOP23 package chip, and the arrangement spacing of each internal test pin 402 in the first side test structure 410 and the arrangement spacing of each internal test pin 402 in the second side test structure 420 are respectively the same as the arrangement spacing of each pin on the corresponding side of the SOP23 package chip.
[0048] For example, in combination Figure 1 and Figure 4 , the arrangement spacing of each external test pin 401 in the first side test structure 410 can be the same as the arrangement spacing of each pin on the first side of the SOP23 packaged chip, and they are all arranged at equal intervals, and the arrangement spacing of each internal test pin 402 is the same as the arrangement spacing of each external test pin 401, so when testing the SOP23 packaged chip, the first side test structure 410 can be used to contact the corresponding pins on the first side of the SOP23 packaged chip. The arrangement spacing of each external test pin 401 in the second side test structure 420 can be the same as the arrangement spacing of each pin on the second side of the SOP23 packaged chip, and they are all arranged at non-equal intervals, and the arrangement spacing of each internal test pin 402 is the same as the arrangement spacing of each external test pin 401, so when testing the SOP23 packaged chip, the second side test structure 420 can be used to contact the corresponding pins on the second side of the SOP23 packaged chip.
[0049] Based on the same utility model concept, the embodiment of the present application also provides a test system for SOP23 packaged chips, which can be applied to Figure 1 An exemplary SOP23 package is shown.
[0050] In one embodiment, the test system includes a test device, a test circuit board and a test fixture as provided in any of the above embodiments; wherein the test device is connected to the test circuit board, and the test function of the test circuit board is adapted to the test items of the SOP23 packaged chip; the second part 4012 of an external test pin 401 and the end of the body 4021 of a corresponding internal test pin 402 close to the second part 4012 are respectively used to simultaneously contact different positions of the same pin of the SOP23 packaged chip to form a Kelvin test loop with the pin; the second end of the first part 4011 of each external test pin 401 and the end of the body 4021 of each internal test pin 402 away from the second part 4012 are both connected to the test circuit board.
[0051] During the test of the SOP23 packaged chip, each external test pin 401 and each internal test pin 402 of the first side test structure 410 are in contact with each pin of the first side of the SOP23 packaged chip, each external test pin 401 and each internal test pin 402 of the second side test structure 420 are in contact with each pin of the second side of the SOP23 packaged chip, the first side test structure 410 and the second side test structure 420 are both electrically connected to the test circuit board, and the test equipment is electrically connected to the test circuit board, so that the test equipment performs Kelvin test on each pin of the first side of the SOP23 packaged chip and each pin of the second side of the SOP23 packaged chip through the test circuit board, the first side test structure 410, and the second side test structure 420. The Kelvin test method is adopted, which is an electrical impedance or voltage measurement technology, using separate current and voltage detection, and can perform more accurate measurements compared to traditional two-terminal sensing.
[0052] The test system and test fixture provided in the embodiments of the present application both belong to the same utility model concept, can solve the same technical problems and achieve the same technical effects, and the repeated contents will not be repeated here.
[0053] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0054] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A test fixture for SOP23 packaged chips, characterized in that: including a first side test structure and a second side test structure; The first side test structure and the second side test structure each include at least a plurality of external test pins and a plurality of internal test pins having the same number as the external test pins, wherein the number of the external test pins in the first side test structure and the number of the external test pins in the second side test structure are respectively the same as the number of pins on the corresponding side of the SOP23 packaged chip; Wherein, a plurality of the external test pins are arranged side by side; each of the external test pins comprises a first portion extending along a first direction and a second portion extending along a second direction, the second portion is connected to a first end of the first portion, and the second direction is perpendicular to the first direction; A plurality of the inner test needles are arranged side by side; each of the inner test needles comprises a body extending along the first direction, the body is opposite to the first portion, and is located within a plane surrounded by the first portion and the second portion and has a spacing with the first portion and the second portion respectively; The second portion of the outer test pin and the corresponding body of the inner test pin are respectively used to contact different positions of the same pin of the SOP23 packaged chip at the same time to form a Kelvin test loop with the pin.
2. The test fixture according to claim 1, characterized in that: The first side test structure and the second side test structure both further include a plastic packaging structure; The plastic encapsulation structure is located on the side where the second end of the first part of each of the external test pins is located, and the second end of each of the first parts and the corresponding end of the body of each of the internal test pins are plastic encapsulated. The plastic encapsulation exposes the surface of the second end of each of the first parts away from the body and exposes the surface of the corresponding end of each of the bodies away from the first part, wherein the exposed surface is used to electrically connect to an external test circuit board, and the test function of the test circuit board is adapted to the items to be tested of the SOP23 packaged chip.
3. The test fixture according to claim 2, characterized in that: The first side test structure and the second side test structure each further include a first fixing structure; Each of the outer test needles and each of the inner test needles passes through the first fixing structure so as to fix each of the outer test needles and each of the inner test needles through the first fixing structure, and the first fixing structure is in contact with the plastic packaging structure.
4. The test fixture according to claim 1, characterized in that: The first side test structure and the second side test structure each further include a second fixing structure; The second fixing structure is located between each of the outer testing needles and each of the inner testing needles, and is mechanically connected to each of the outer testing needles and each of the inner testing needles.
5. The test fixture according to claim 1, characterized in that: The first part, the second part and the main body are all in the shape of a cuboid.
6. The test fixture according to claim 5, characterized in that: The thickness and width of the first portion, the second portion and the main body are all the same.
7. The test fixture according to claim 6, characterized in that: The thickness of the first part, the second part and the main body is (0.2±0.02) mm; the width of the first part, the second part and the main body is (0.8±0.02) mm.
8. The test fixture according to claim 1, characterized in that: The vertical distance between the first part and the main body is (0.1±0.05) mm.
9. The test fixture according to claim 1, characterized in that: The arrangement spacing of the external test pins in the first side test structure and the arrangement spacing of the external test pins in the second side test structure are respectively the same as the arrangement spacing of the pins on the corresponding side of the SOP23 packaged chip, and the arrangement spacing of the internal test pins in the first side test structure and the arrangement spacing of the internal test pins in the second side test structure are respectively the same as the arrangement spacing of the pins on the corresponding side of the SOP23 packaged chip.
10. A test system for SOP23 packaged chips, characterized in that: include: A test device, a test circuit board, and a test fixture as claimed in any one of claims 1 to 9; Wherein, the test equipment is connected to the test circuit board, and the test function of the test circuit board is adapted to the items to be tested of the SOP23 packaged chip; The second portion of the outer test pin and the end of the body of the corresponding inner test pin close to the second portion are respectively used to contact different positions of a pin of the SOP23 packaged chip at the same time to form a Kelvin test loop with the pin; The second end of the first portion of each of the outer test pins and the end of the body of each of the inner test pins away from the second portion are both connected to the test circuit board.