Package substrate and integrated circuit device

Abstract

The present disclosure relates to a package substrate and an integrated circuit device, the package substrate comprising: a substrate body; the ball grid array is located on the surface of the substrate body, the ball grid array comprises a power supply array area, and the power supply array area comprises a plurality of power supply solder balls; wherein in the power supply array area, insulating layers of which the dielectric constant is higher than that of air are filled among the power supply solder balls. According to the invention, the parasitic capacitance of the power supply solder ball area is increased, the parasitic capacitance of the power supply network of the integrated circuit device to which the packaging substrate belongs is improved, the PDN impedance curve of the power supply system of the integrated circuit device is optimized, and the performance of the integrated circuit device is improved. Besides, the surface of the substrate body of the packaging substrate can be arranged to be a rotationally symmetrical polygon or a circle, the distance between the mounting holes can be shortened, the space occupied by the fixing auxiliary device on the PCB can be reduced, and therefore more wiring space can be vacated for the PCB.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit devices, and in particular to a packaging substrate and an integrated circuit device. Background Art

[0002] The PDN (Power Distribution Network) impedance curve is a curve that describes the impedance characteristics of the power distribution network at different frequencies. The PDN impedance curve is critical to the design of electronic systems because it can help evaluate and optimize the stability, efficiency, and noise performance of the power supply. By analyzing the PDN impedance curve, the optimal location and value of the decoupling capacitor can be determined, as well as potential power integrity issues can be identified and resolved. The analysis of the PDN impedance curve is particularly important in the design of high-speed digital circuits and RF circuits because these systems have very strict requirements on power supply noise and stability.

[0003] In the design and manufacture of integrated circuit devices, it is necessary to optimize the structure of the integrated circuit devices to make the PDN impedance curve as ideal as possible, so that the impedance value in the ideal PDN impedance curve is as low as possible within the entire frequency range of system operation, thereby reducing the voltage drop and loss in the current path. The ideal PDN impedance curve is kept as flat as possible within the entire frequency range of system operation, thereby ensuring that the power supply provides a stable voltage, reducing dynamic ripple, and ensuring the performance of the integrated circuit device, etc. Utility Model Content

[0004] In view of this, the present disclosure provides a packaging substrate and an integrated circuit device to help flatten the PDN impedance curve in a system where the integrated circuit device using the packaging substrate is located, help improve the voltage stability of the power supply of the integrated circuit device, and thus help improve the performance of the integrated circuit device.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] According to one aspect of an embodiment of the present disclosure, there is provided a packaging substrate, including:

[0007] substrate body;

[0008] A ball grid array is located on the surface of the substrate body, the ball grid array includes a power array area, and the power array area includes a plurality of power solder balls;

[0009] Wherein, in the power array area, an insulating layer having a dielectric constant higher than that of air is filled between the power solder balls.

[0010] In a possible implementation manner, the plurality of power solder balls include a plurality of output voltage solder balls and a plurality of ground solder balls;

[0011] The plurality of output voltage solder balls and the plurality of ground solder balls are distributed alternately on the surface of the substrate body.

[0012] In a possible implementation manner, the material of the insulating layer is colloid or high molecular polymer.

[0013] In a possible implementation manner, the ball grid array further includes a signal array area, and the signal array area includes a plurality of signal solder balls;

[0014] Wherein, in the signal array area, there is no insulating layer between the signal solder balls.

[0015] In one possible embodiment, the surface of the substrate body is a rotationally symmetric polygon or a circle, wherein the number of edges of the rotationally symmetric polygon is greater than four, and when the integrated circuit device including the packaging substrate is installed on a PCB board, at least two mounting holes for installing an auxiliary fixing device are provided on the PCB board, and the at least two mounting holes are symmetrically arranged on the outside of the edge of the substrate body, and the auxiliary fixing device is used to fix the integrated circuit device on the PCB board.

[0016] In a possible implementation manner, the area of ​​the surface of the substrate body is equal to the area occupied by the ball grid array.

[0017] In one possible implementation, the PCB board is provided with a square mounting area for mounting the auxiliary fixing device, the integrated circuit device is located in the mounting area, there are four mounting holes, and the four mounting holes are respectively arranged between the four corner vertices of the mounting area and the substrate body of the integrated circuit device, wherein the area of ​​the mounting area is the minimum area of ​​the substrate body that can accommodate the four mounting holes and the integrated circuit device.

[0018] In a possible implementation manner, there are four mounting holes, which are centrally symmetrically arranged around the periphery of the integrated circuit device.

[0019] According to another aspect of the present disclosure, there is provided an integrated circuit device, including:

[0020] The packaging substrate as described in any one of the above items; and

[0021] The chip is located on a side of the substrate body facing away from the ball grid array and is electrically connected to the ball grid array.

[0022] In one possible implementation, the integrated circuit device is at least one of a CPU, a GPU, a TPU, a NPU, a DPU, an APU, and a GPGPU.

[0023] It can be seen from the above scheme that in the package substrate and integrated circuit device disclosed in the present invention, an insulating layer with a dielectric constant higher than the dielectric constant of air is filled between the power solder balls, thereby increasing the parasitic capacitance of the power solder ball area, improving the parasitic capacitance of the power network of the integrated circuit device to which the package substrate belongs, and helping to optimize the PDN impedance curve of the power system of the integrated circuit device, and helping to improve the performance of the integrated circuit device. In addition, the surface of the substrate body of the package substrate disclosed in the present invention is set to a rotationally symmetrical polygon or circle, which helps to shorten the distance between the mounting holes and helps to reduce the space occupied by the fixing auxiliary device on the PCB board, thereby freeing up more wiring space for the PCB board. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic structural diagram of an integrated circuit device for a solution to flattening a PDN impedance curve in the related art;

[0025] Figure 2A is a schematic cross-sectional view of a packaging substrate according to an exemplary embodiment;

[0026] Figure 2B is a schematic structural diagram of one side of a ball grid array of a packaging substrate according to an exemplary embodiment;

[0027] Figure 3 A schematic diagram of the layout of mounting holes for integrated circuit devices and auxiliary fixing devices in a PCB board in the related art;

[0028] Figure 4 is a schematic diagram comparing the positions of a reference substrate, a reference mounting hole, a package substrate of an embodiment of the present disclosure, and the mounting hole on a PCB according to an exemplary embodiment;

[0029] Figure 5 The diagram is a schematic diagram showing the positions of another packaging substrate and mounting holes arranged around it according to an illustrative embodiment, compared with a reference substrate body and reference mounting holes. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0031] Figure 1 Schematic diagram of the structure of an integrated circuit device for a solution to flattening the PDN impedance curve in the related art. Figure 1 As shown, in the related art, in order to make the change of the PDN impedance curve of the integrated circuit device flat, a plurality of capacitors 3 are arranged on one side (top side) of the substrate body 1 facing the chip 2 in the integrated circuit device, for example Figure 1As shown, a plurality of capacitors 3 are arranged around the chip 2, and these capacitors 3 are connected to the power supply network of the integrated circuit device. In this way, a certain degree of impedance reduction is brought about in the 8Mhz to 30Mhz region of the PDN impedance curve, thereby reducing the dynamic ripple to a certain extent.

[0032] The embodiments of the present disclosure provide a packaging substrate and an integrated circuit device, which adopt a solution different from the related art. By filling an insulating layer with a dielectric constant higher than the dielectric constant of air between the power solder balls in the ball grid array arranged on the packaging substrate, the parasitic capacitance of the power network on the packaging substrate is increased to help optimize the PDN impedance curve and help improve the performance of the integrated circuit device.

[0033] Figure 2A is a schematic cross-sectional view of a packaging substrate according to an exemplary embodiment. Figure 2B FIG. 1 is a schematic diagram showing a structure of a ball grid array on one side of a package substrate according to an exemplary embodiment. Figure 2A , Figure 2B As shown, the package substrate of the embodiment of the present disclosure mainly includes a substrate body 1 and a ball grid array 4. The ball grid array 4 is located on the surface of the substrate body 1, and the ball grid array 4 includes a power array area 41, and the power array area 41 includes a plurality of power solder balls 411. In the power array area 41, an insulating layer 412 with a dielectric constant higher than that of air is filled between each power solder ball 411. The power solder ball 411 is connected to the power network of the integrated circuit device to which the package substrate belongs.

[0034] Based on the following capacitance formula

[0035] C=ε·δ·s / d

[0036] It can be seen that after the introduction of the insulating layer 412, ε will become larger, so that when δ, s, and d are unchanged, the parasitic capacitance of the power array area 41 will increase, which will help increase the parasitic capacitance of the power network in the package substrate, help optimize the PDN impedance curve, and help improve the performance of the integrated circuit device. Wherein, C is the parasitic capacitance of the power solder ball, ε is the relative dielectric constant of the medium between the power solder balls, δ is the absolute dielectric constant (i.e., the vacuum dielectric constant), ε·δ is the dielectric constant of the medium between the power solder balls, the ε of the insulating layer 412 is higher than the ε of the air, and thus the dielectric constant of the insulating layer 412 is higher than the dielectric constant of the air. When the insulating layer 412 is not filled in the power array area 41, the medium between each power solder ball 411 is air, where the ε of air is approximately 1, the relative dielectric constant can also be called the relative permittivity, s is used to characterize the effective area of ​​the power solder ball in the insulating layer, and d is used to characterize the distance between the power solder balls. It can also be seen from the above formula that when the ε value of air becomes the ε value of the insulating layer 412 (that is, when the dielectric constant increases from the dielectric constant value of air to the dielectric constant value of the insulating layer 412), s can be appropriately increased and / or d can be appropriately decreased. In other words, the effective area of ​​the power solder ball can be appropriately increased (for example, the effective area can be increased by changing the shape of the power solder ball) and / or the spacing between the power solder balls can be reduced to further increase the parasitic capacitance of the power array area 41.

[0037] In the package substrate of the embodiment of the present disclosure, an insulating layer 412 having a dielectric constant higher than that of air is filled between the power solder balls 411, thereby increasing the parasitic capacitance of the power solder balls 411 region and improving the integrated circuit device 10 (such as Figure 3 The parasitic capacitance of the power supply network (as shown) helps to optimize the PDN impedance curve of the power supply system of the integrated circuit device 10, and helps to improve the performance of the integrated circuit device 10.

[0038] The packaging substrate of the embodiment of the present disclosure is helpful to reduce the PDN impedance curve. Compared with the packaging substrate in the related art where no insulating layer with a dielectric constant higher than that of air is filled between the power solder balls, the minimum value of the dynamic ripple (V min ) will be improved, thereby reserving a certain space for the appropriate improvement of the main frequency, and then on the basis of adopting the packaging substrate of the embodiment of the present disclosure, it is helpful to set the voltage (V set ) remains unchanged while the performance of integrated circuit devices can be improved by appropriately increasing the main frequency.

[0039] In addition, because the added insulating layer can also help enhance the anti-bending ability of the package substrate, it helps to reduce the deformation of the package substrate caused by external stress, making the package substrate more shock-resistant, which is more conducive to the shock-resistant ability of the manufactured integrated circuit device. And because of the existence of the added insulating layer, in the subsequent possible tin furnace process, the package substrate is provided with support force to prevent the package substrate from being excessively deformed during the tin furnace process.

[0040] like Figure 2A , Figure 2B As shown, the multiple power solder balls 411 in the power array area 41 include multiple output voltage solder balls 4111 and multiple ground solder balls 4112. Among them, the multiple output voltage solder balls 4111 and the multiple ground solder balls 4112 are staggered on the surface of the substrate body 1. In other words, in the power array area 41, the power solder ball 411 adjacent to any output voltage solder ball 4111 is a ground solder ball 4112, and the power solder ball 411 adjacent to any ground solder ball 4112 is an output voltage solder ball 4111. The staggered distribution of the output voltage solder balls 4111 and the ground solder balls 4112 helps to form more parasitic capacitance, thereby optimizing the PDN impedance characteristics and improving chip performance.

[0041] In an exemplary embodiment, the material of the insulating layer 412 is a colloid or a polymer. In an exemplary embodiment, the polymer is, for example, an epoxy resin. In an exemplary embodiment, the insulating layer 412 can be made of AB glue. In an exemplary embodiment, after the ball grid array 4 is prepared, the insulating layer 412 can be formed by coating the AB glue on the power array area 41 in a room temperature environment. In an exemplary embodiment, the AB glue can be an epoxy resin-based AB glue, wherein the A component is an epoxy resin matrix, the A component can further include a catalyst and other auxiliary agents, the B component is mainly a curing agent, and the B component can further include other auxiliary agents for promoting and controlling the curing reaction as needed. When used, the A component and the B component of the AB glue are mixed evenly according to the set ratio, and coated between the output voltage solder ball 4111 and the ground solder ball 4112 of the power array area 41, and the curing agent in the B component reacts with the epoxy resin matrix in the A component to initiate the curing process, and finally forms an insulating layer 412 in the form of a three-dimensional cross-linked cured product between the output voltage solder ball 4111 and the ground solder ball 4112.

[0042] In an illustrative embodiment, the material of the insulating layer 412 can also be injected between the power solder balls 411 before passing through the tin furnace in SMT (Surface-Mounted Technology). After passing through the tin furnace, the material of the insulating layer 412 is hardened between the power solder balls 411.

[0043] In the exemplary embodiment, before preparing the ball grid array 4, an insulating layer 412 may be prepared in the power array area 41 on the surface of the substrate body 1. At this time, the material of the insulating layer 412 needs to avoid the positions of the output voltage solder balls 4111 and the ground solder balls 4112 to be prepared later in the power array area 41. At this time, the morphology of the insulating layer 412 may be controlled so that the positions of the avoided output voltage solder balls 4111 and the ground solder balls 4112 are square, and then the output voltage solder balls 4111 and the ground solder balls 4112 prepared later are also square, which helps to further increase the area of ​​the power solder balls in the insulating layer, and helps to further increase the parasitic capacitance of the power array area 41.

[0044] like Figure 2A , Figure 2B As shown, in the exemplary embodiment, the ball grid array 4 further includes a signal array area 42, and the signal array area 42 includes a plurality of signal solder balls 421. In the signal array area 42, there is no insulating layer 412 between each signal solder ball 421. In the exemplary embodiment, there is air between each signal solder ball 421. In this way, the parasitic capacitance between the signal solder balls 421 will not be affected, which helps to ensure the performance of the integrated circuit device.

[0045] In an exemplary embodiment, the package substrate may further include: a plurality of chip interconnection bumps and interconnection lines. Figure 2A As shown, a plurality of chip interconnect bumps 5 are located on a side of the substrate body 1 facing away from the ball grid array 4, and the chip interconnect bumps 5 are used to connect the chip 2. Interconnect wires (not shown) are located in the substrate body 1 and connect the ball grid array 4 and the plurality of chip interconnect bumps 5. In the exemplary embodiment, the chip interconnect bumps 5 are C4 bumps.

[0046] In an exemplary embodiment, the combination Figure 1 As shown, it can also be combined with related technologies. The package substrate of the embodiment of the present disclosure can further include at least one capacitor 3, which is arranged on the side of the substrate body 1 facing away from the ball grid array 4 and is located in the peripheral area of ​​the chip 2. Combining the package substrate of the embodiment of the present disclosure with related technologies can further reduce the variation range of the PDN impedance curve on the basis of the related technologies, thereby helping to further optimize the PDN impedance curve and help to further improve the performance of the integrated circuit device.

[0047] It should be noted that Figure 2A , Figure 2B The dotted box shown is only used to indicate the area range and is not a physical part of the package substrate structure.

[0048] In addition, in the related art, the surface of the substrate body is usually square or rectangular. In this case, Figure 3The schematic diagram of the layout of the mounting holes of the integrated circuit device and the fixing auxiliary device in the PCB board in the related art shown in the figure, the integrated circuit device 10 manufactured in the related art is also square or rectangular, when the square or rectangular integrated circuit device 10 is installed on the PCB board 20, and when the fixing auxiliary device for fixing the integrated circuit device 10 is installed on the PCB board 20, it is necessary to open a plurality of (for example, four) mounting holes 30 outside the four corners of the integrated circuit device 10. Due to the orientation restrictions of the four corners of the integrated circuit device 10, the distance between adjacent mounting holes 30 may be large. In this case, the fixing auxiliary device will occupy a large space of the PCB board 20, for example Figure 3 The dotted box area shown is the space occupied by the auxiliary fixing device in the PCB board 20. With the continuous improvement of integration, the space of the PCB board 20 occupied by the auxiliary fixing device is increasingly unfavorable to the wiring requirements of the PCB board 20. Among them, the auxiliary fixing device includes a fixing fixture, a heat sink, etc.

[0049] Therefore, if the distance between adjacent mounting holes 30 can be shortened, it will help miniaturize the auxiliary fixing device, thereby reducing the space occupied by the auxiliary fixing device on the PCB board 20, which is helpful for the wiring of the PCB board 20. Based on this, in an exemplary embodiment, a new type of packaging substrate is also provided. The surface of the substrate body of the packaging substrate is a rotationally symmetrical polygon or a circle, wherein the number of edges of the rotationally symmetrical polygon is greater than four, and when the integrated circuit device including the packaging substrate is installed on the PCB board, at least two mounting holes for installing the auxiliary fixing device and arranged on the outside of the edge of the substrate body are provided on the PCB board, and the auxiliary fixing device is used to fix the integrated circuit device on the PCB board. In the exemplary embodiment, there are four mounting holes, which are centrally symmetrically arranged on the outside of the edge of the substrate body. Optionally, the four mounting holes are centrally symmetrically and rotationally symmetrically arranged on the outside of the edge of the substrate body. In the exemplary embodiment, the connecting line of the four mounting holes forms a square.

[0050] In the exemplary embodiment, the area of ​​the substrate body surface is equal to the area of ​​the ball grid array area. In this way, the area of ​​the substrate body surface can be made as small as possible, which helps to shorten the distance between the mounting holes, helps to miniaturize the fixing auxiliary device, and helps to provide more wiring space for the PCB board.

[0051] In the exemplary embodiment, the PCB board is provided with a square mounting area for mounting the fixing auxiliary device (see Figure 3The integrated circuit device is located in the installation area, and there are four installation holes, which are respectively arranged between the four corner vertices of the installation area and the substrate body of the integrated circuit device, wherein the area of ​​the installation area is the minimum area of ​​the substrate body that can accommodate the four installation holes and the integrated circuit device. Adopting this method and when the surface of the substrate body is a rotationally symmetrical polygon or a circle, it helps to reduce the distance between the installation holes, thereby helping to miniaturize the fixing auxiliary device, helping to reduce the space occupied by the fixing auxiliary device on the PCB board 20, and facilitating the wiring of the PCB board. The following will be combined with the comparative description of the comparative device and Figure 4 , Figure 5 This is further explained.

[0052] In an illustrative embodiment, a ball grid array is composed of a plurality of external connection solder balls, and the plurality of external connection solder balls include a plurality of power supply solder balls of the above-mentioned embodiments. The design spacing between adjacent mounting holes in at least two mounting holes is smaller than the design spacing between adjacent control mounting holes in at least two control mounting holes when the control device is installed on a PCB board. Wherein, the control device includes a control substrate, and the control substrate includes a control substrate body and a ball grid control array. The surface of the control substrate body is square. The ball grid control array is located on the surface of the control substrate body, and the ball grid control array is composed of a plurality of control solder balls, and the area of ​​the surface of the control substrate body is equal to the area of ​​the ball grid control array. Wherein, the size of the external connection solder balls is equal to that of the control solder balls, the average spacing between adjacent external connection solder balls is equal to the average spacing between adjacent control solder balls, and the number of the plurality of external connection solder balls is equal to that of the plurality of control solder balls. Wherein, the control device, for example Figure 3 An integrated circuit device 10 is shown.

[0053] Figure 4 1 is a schematic diagram showing a comparison of the positions of a reference substrate, a reference mounting hole, a package substrate of an embodiment of the present disclosure, and the mounting hole on a PCB board according to an exemplary embodiment, wherein a reference substrate body 401, a reference mounting hole 402, and a reference ball grid array 403 are represented by dotted lines, and a substrate body 1, a mounting hole 30, and a ball grid array 4 of an embodiment of the present disclosure are represented by solid lines. Figure 4 The surface shape of the reference substrate body 401 shown is square, the surface shape of the substrate body 1 is circular, and the reference device made from the reference substrate is square. Figure 4 The integrated circuit device made of the package substrate shown is circular. Figure 4As shown, the control substrate includes a control substrate body 401 and a ball grid control array 403. The ball grid control array 403 is located on the surface of the control substrate body 401. The ball grid control array 403 is composed of a plurality of control solder balls. The area of ​​the surface of the control substrate body 401 is equal to the area of ​​the ball grid control array 403. Four control mounting holes 402 are axially symmetrically arranged outside the four corners of the control substrate body 401. The package substrate includes a substrate body 1 and a ball grid array 4. The ball grid array 4 is located on the surface of the substrate body 1. The ball grid array 4 is composed of a plurality of externally connected solder balls. The area of ​​the surface of the substrate body 1 is equal to the area of ​​the ball grid array 4.

[0054] like Figure 4 As shown, since the size of the external connection solder balls is equal to that of the control solder balls, the average spacing between adjacent external connection solder balls is equal to that between adjacent control solder balls, and the number of the plurality of external connection solder balls is equal to that of the plurality of control solder balls, the surface area of ​​the substrate body 1 with a circular surface shape is equal to that of the control substrate body 401 with a square surface shape. However, the four corner regions of the substrate body 1 with a circular surface shape are significantly indented relative to the four corner regions of the control substrate body 401 with a square surface shape, and thus, the spacing between adjacent mounting holes 30 of the four mounting holes 30 axially symmetrically arranged on the outer side of the substrate body 1 can be reduced with this indentation ( Figure 4 As shown, the spacing between adjacent mounting holes 30 is significantly smaller than the spacing between adjacent control mounting holes 402 . In this case, the space occupied by the auxiliary fixing device on the PCB board 20 can be smaller, thereby freeing up more wiring space for the PCB board 20 .

[0055] Figure 5 FIG. 1 is a schematic diagram showing a comparison of another embodiment of a package substrate and mounting holes arranged around it according to an exemplary embodiment, and a comparison of the positions of a reference substrate body and reference mounting holes, wherein the reference substrate body 401, reference mounting holes 402 and reference ball grid array 403 are represented by dotted lines, and the substrate body 1, mounting holes 30 and ball grid array 4 of the embodiment of the present disclosure are represented by solid lines, as shown in FIG. Figure 5 As shown, the shape of the surface of the substrate body 1 is a rotationally symmetrical octagon, wherein the upper left edge, the lower left edge, the upper right edge and the lower right edge are relatively short, and the upper edge, the lower edge, the left edge and the right edge are relatively long. Compared with the square surface of the reference substrate body 401, although the distance between the upper edge and the lower edge, and the distance between the left edge and the right edge may be slightly larger, the existence of the upper left edge, the lower left edge, the upper right edge and the lower right edge indents the space in the four corner areas of the reference substrate body 401, so that the distance between the four mounting holes 30 can be reduced with the indentation, thereby Figure 5It can be seen that the spacing between adjacent mounting holes 30 is significantly smaller than the spacing between adjacent control mounting holes 402, which helps to shorten the distance between the mounting holes 30 and the space occupied by the fixing auxiliary device on the PCB board, thereby freeing up more wiring space for the PCB board. Figure 5 The shape of the substrate body 1 of the illustrated embodiment is easier to manufacture, making the packaging substrate of this configuration easier to realize.

[0056] In an illustrative embodiment, an integrated circuit device is also provided, which includes a packaging substrate and a chip, wherein the packaging substrate is the packaging substrate of any of the above embodiments, and the chip is located on a side of the substrate body facing away from the ball grid array and is electrically connected to the ball grid array.

[0057] In an illustrative embodiment, the integrated circuit device is at least one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Unit).

[0058] In an exemplary embodiment, the chip may be a SoC (System on Chip) chip.

[0059] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A packaging substrate, characterized in that: include: substrate body; A ball grid array is located on the surface of the substrate body, the ball grid array includes a power array area, and the power array area includes a plurality of power solder balls; Wherein, in the power array area, an insulating layer having a dielectric constant higher than that of air is filled between the power solder balls.

2. The packaging substrate according to claim 1, characterized in that: The plurality of power solder balls include a plurality of output voltage solder balls and a plurality of ground solder balls; The plurality of output voltage solder balls and the plurality of ground solder balls are distributed alternately on the surface of the substrate body.

3. The packaging substrate according to claim 1, wherein: The material of the insulating layer is colloid or high molecular polymer.

4. The packaging substrate according to claim 1, wherein: The ball grid array further comprises a signal array area, wherein the signal array area comprises a plurality of signal solder balls; Wherein, in the signal array area, there is no insulating layer between the signal solder balls.

5. The packaging substrate according to claim 1, wherein: The surface of the substrate body is a rotationally symmetric polygon or a circle, wherein the number of edges of the rotationally symmetric polygon is greater than four, and when the integrated circuit device including the packaging substrate is installed on a PCB board, at least two mounting holes for installing a fixing auxiliary device are provided on the PCB board, and the at least two mounting holes are centrally symmetrically arranged on the outside of the edge of the substrate body, and the fixing auxiliary device is used to fix the integrated circuit device on the PCB board.

6. The packaging substrate according to claim 5, characterized in that: The area of ​​the surface of the substrate body is equal to the area occupied by the ball grid array.

7. The packaging substrate according to claim 6, characterized in that: The PCB board is provided with a square mounting area for mounting the auxiliary fixing device, the integrated circuit device is located in the mounting area, there are four mounting holes, and the four mounting holes are respectively arranged between the four corner vertices of the mounting area and the substrate body of the integrated circuit device, wherein the area of ​​the mounting area is the minimum area of ​​the substrate body that can accommodate the four mounting holes and the integrated circuit device.

8. The packaging substrate according to claim 5, characterized in that: There are four mounting holes, which are centrally symmetrically arranged on the periphery of the integrated circuit device.

9. An integrated circuit device, characterized in that: include: The packaging substrate according to any one of claims 1 to 8; as well as, The chip is located on a side of the substrate body facing away from the ball grid array and is electrically connected to the ball grid array.

10. The integrated circuit device according to claim 9, characterized in that: The integrated circuit device is at least one of a CPU, a GPU, a TPU, a NPU, a DPU, an APU, and a GPGPU.

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