Chip packaging structure

Abstract

The utility model provides a chip packaging structure. The chip packaging structure comprises a chip, at least one first pin, at least one second pin, a plurality of bonding wires and a plastic package; the front of the chip has a plurality of lead pads; the first pin and the second pin both have a first part close to the chip and a second part far from the chip, the first pin and the corresponding lead pad are connected by a bonding wire, and the second pin and the corresponding lead pad are connected by a bonding wire; the second parts of the first pin and the second pin both extend out of the side wall of the plastic package, the second pin extends in the plane where the bottom surface of the plastic package is located, the first part of the first pin is located above the second pin, and the distance that the first pin extends out of the plastic package sideways is greater than the second pin, so that the second pin is arranged within the space range where the first pin extends out, the number of pins of the chip packaging structure can be increased under the condition of the same chip packaging area, and it is also beneficial to reduce the inductance effect of the chip packaging structure.

Description

Technical Field

[0001] The utility model relates to the technical field of packaging, in particular to a chip packaging structure. Background Art

[0002] Existing packages include transistor outline package (TO), dual in-line package (DIP), small epitaxial package (SOP), J-lead small outline package (SOJ), plastic chip carrier with leads (PLCC), quad flat package (QFP), quad flat no-lead package (QFN) and ball grid array package (BGA), etc., and also include some complex system packages. The above packages have their own advantages, and the appropriate package can be selected according to the actual application environment.

[0003] With the development of integrated circuits, the functions of chip packaging structures are increasing, which requires the number of peripheral pins of chip packaging structures to gradually increase; as the interface speed continues to increase, the inductance effect of chip packaging structures needs to be reduced. However, existing packaging is difficult to meet the requirements of small size, multiple pins and small inductance effect of chip packaging structures. Utility Model Content

[0004] One of the purposes of the utility model is to provide a chip packaging structure that can meet the requirements of small size, multiple pins and small inductance effect of the chip packaging structure.

[0005] In order to achieve the above-mentioned purpose, the chip packaging structure provided by the utility model includes a chip, at least one first pin, at least one second pin, a plurality of bonding wires and a plastic package. The chip has a front side and a back side facing opposite directions, and the front side of the chip has a plurality of lead pads; the first pin and the second pin each have a first part close to the chip and a second part away from the chip, the first part of the first pin and the lead pad corresponding to the first pin are connected through the bonding wire, and the first part of the second pin and the lead pad corresponding to the second pin are connected through the bonding wire; the plastic package wraps the chip, the plurality of bonding wires, the first part of the first pin and the first part of the second pin, the first pin and the second part of the second pin both extend out of the side wall of the plastic package, and the plastic package has a bottom surface on the same side as the back side of the chip; wherein the second pin extends in the plane where the bottom surface of the plastic package is located, the first part of the first pin is located above the second pin, and the distance that the first pin extends laterally out of the plastic package is greater than the distance that the second pin extends laterally out of the plastic package.

[0006] Optionally, in the plane where the bottom surface of the plastic package body is located, the orthographic projection of the first lead and the orthographic projection of the second lead at least partially overlap.

[0007] Optionally, the first pin is a bent strip pin and is bent from the middle of the plastic package body in the thickness direction toward the bottom surface of the plastic package body; the second pin is a straight strip pin.

[0008] Optionally, the orthographic projections of the first pin and the second pin in the plane where the bottom surface of the plastic package body is located do not overlap.

[0009] Optionally, the orthographic projections of the first pin and the second pin in the plane where the bottom surface of the plastic package body is located partially overlap.

[0010] Optionally, in the plane where the bottom surface of the plastic package body is located, the orthographic projection of one of the second pins is located within the orthographic projection of one of the first pins above the second pin.

[0011] Optionally, the second portion of the first pin extends into a plane where the bottom surface of the plastic package body is located.

[0012] Optionally, the lead frame of the chip packaging structure includes the first pin, the second pin and a chip pad, the back side of the chip is attached to the chip pad, and the first pin and the second pin are arranged around the chip pad.

[0013] Optionally, the lead pads are distributed in an edge area of ​​the front side of the chip.

[0014] Optionally, the chip includes a plurality of side edges, the number of the first pin and the number of the second pin are both plural, and the plurality of the first pins and the plurality of the second pins are alternately arranged on the side edges of the chip.

[0015] The chip packaging structure provided by the utility model comprises a chip, at least one first pin, at least one second pin, a plurality of bonding wires and a plastic package body, wherein the first pin and the second pin both have a first part close to the chip and a second part far away from the chip, the first part of the first pin and the lead pad corresponding to the first pin are connected through a bonding wire, and the first part of the second pin and the lead pad corresponding to the second pin are connected through the bonding wire; the plastic package body wraps the chip, the plurality of bonding wires, the first part of the first pin and the first part of the second pin, the second parts of the first pin and the second pin both extend out of the side wall of the plastic package body, and the plastic package body has a bottom surface on the same side as the back side of the chip; wherein the second pin is disposed on the plastic package body. The first pin extends within the plane where the bottom surface of the package body is located, the first part of the first pin is located above the second pin, and the distance that the first pin extends laterally out of the plastic package body is greater than the distance that the second pin extends laterally out of the plastic package body. In this way, the second pin is arranged within the spatial range where the first pin extends, and the width of the chip packaging structure will not be increased additionally. Under the condition of the same chip packaging area, the number of pins of the chip packaging structure can be increased, and the length of the bonding wire connecting the pin and the lead pad does not need to be lengthened. In other words, when the chip packaging structure has a considerable number of pins, the area of ​​the chip packaging structure is reduced, and the length of the bonding wire is shortened, thereby reducing the inductance effect of the chip packaging structure, solving the problem of signal integrity caused by ground bounce caused by large inductance ground, that is, the signal integrity can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A cross-sectional schematic diagram of a chip packaging structure provided in one embodiment of the utility model.

[0017] Figures 2 to 4 1 is a top view of a chip packaging structure according to different embodiments of the present invention.

[0018] Description of the accompanying drawings: 10 - chip; 11 - lead pad; 21 - first pin; 22 - second pin; 23 - chip pad; 30 - bonding wire; 40 - plastic package; 41 - plane where the bottom surface of the plastic package is located. DETAILED DESCRIPTION

[0019] The chip packaging structure proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0020] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. Unless otherwise defined in the present application document, the technical terms or scientific terms used in the present invention should be the common meanings understood by people with general skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not indicate quantitative restrictions, but indicate that there is at least one. "Multiple" or "several" means two or more. Unless otherwise specified, similar words such as "upper" and / or "lower" are only for the convenience of explanation and are not limited to one position or one spatial orientation. Similar words such as "include" or "comprise" mean that the elements or structures appearing in front of "include" or "comprise" cover the elements or structures listed after "include" or "comprise" and their equivalents, and do not exclude other elements or structures.

[0021] In order to meet the requirements of small size, multiple pins and small inductance effect of chip packaging structure, the utility model provides a chip packaging structure.

[0022] Figure 1 The schematic cross-sectional view of a chip packaging structure provided by an embodiment of the present utility model is shown in FIG. Figure 1 As shown, the chip packaging structure includes a chip 10, at least one first pin 21, at least one second pin 22, a plurality of bonding wires 30 and a plastic package 40; the chip 10 has a front side and a back side facing oppositely, and the front side of the chip 10 has a plurality of lead pads 11; the first pin 21 and the second pin 22 both have a first portion close to the chip 10 and a second portion away from the chip 10, the first portion of the first pin 21 and the lead pad 11 corresponding to the first pin 21 are connected through the bonding wire 30, and the first portion of the second pin 22 and the lead pad 11 corresponding to the second pin 22 are connected through the bonding wire 30. The chip 10 is connected with the bonding wire 30; the plastic package 40 wraps the chip 10, the plurality of bonding wires 30, the first part of the first pin 21 and the first part of the second pin 22, the second parts of the first pin 21 and the second pin 22 both extend out of the side wall of the plastic package 40, and the plastic package 40 has a bottom surface on the same side as the back side of the chip 10; wherein the second pin 22 extends in the plane where the bottom surface of the plastic package is located, the first part of the first pin 21 is located above the second pin 22, and the distance that the first pin 21 extends laterally out of the plastic package 40 is greater than the distance that the second pin 22 extends laterally out of the plastic package 40.

[0023] Exemplarily, the chip 10 may be a silicon chip. The chip 10 may have multiple metal layers inside, such as 4 layers or 8 layers. The chip 10 may be a chip particle obtained by cutting a wafer, and has not undergone a packaging process, that is, the chip 10 may be a bare chip. In this embodiment, the chip 10 is a wire-bonded packaging type chip.

[0024] The material of the lead pad 11 on the front side of the chip 10 may include copper, nickel, stainless steel or beryllium copper, but is not limited thereto. The lead pad 11 is connected to the metal layer inside the chip 10 .

[0025] refer to Figure 1 As shown, in this embodiment, the plurality of lead pads 11 are distributed in the edge area of ​​the front side of the chip 10, which is beneficial to reduce the distance between the lead pads 11 and the pins, and reduce the length of the bonding wires 30 connecting the lead pads 11 and the pins, thereby reducing the inductance effect of the chip packaging structure.

[0026] The chip 10 includes multiple sides. For example, the chip 10 may be a rectangular chip, and the multiple lead pads 11 are distributed on one side, two sides, three sides, or four sides of the chip 10. The number of lead pads 11 and the location of the lead pads 11 may be selected according to actual needs; the shape of the chip 10 may also be selected according to actual conditions.

[0027] In this embodiment, the number of the first pin 21 and the second pin 22 are both plural, and the plural first pins 21 and the plural second pins 22 are arranged around the chip 10, and each of the first pins 21 and the corresponding lead pad 11 are located on the same side of the chip 10, and each of the second pins 22 and the corresponding lead pad 11 are located on the same side of the chip 10. Corresponding to the distribution of the lead pad 11, the first pin 21 and the second pin 22 can be distributed on one side, two sides, three sides, or four sides of the chip 10.

[0028] refer to Figure 1 As shown, the lead frame of the chip package structure includes a first pin 21 and a second pin 22, and in one embodiment further includes a die pad 23, the back side of the chip 10 is attached to the die pad 23, and the first pin 21 and the second pin 22 are arranged around the die pad 23. The back side of the chip 10 can be attached to the die pad 23 by adhesive, but is not limited thereto.

[0029] Exemplarily, the materials of the first pin 21 and the second pin 22 can both be metal. In a specific embodiment, the materials of the first pin 21 and the second pin 22 can be one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni.

[0030] The material of the chip pad 23 may be the same as or different from the material of the pin. In some embodiments, the material of the chip pad 23 is a metal or an insulating material, the metal may be one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni, the insulating material may be an inorganic insulating material or an organic insulating material, the inorganic insulating material may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, the organic insulating material may be an epoxy resin, a polyimide resin, a benzocyclobutene resin or a polybenzoxazole resin, or the organic insulating material may be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol.

[0031] refer to Figure 1 As shown, illustratively, there is a one-to-one correspondence between the pins and the lead pads 11 ; specifically, one first pin 21 corresponds to one lead pad 11 , and one second pin 22 corresponds to one lead pad 11 .

[0032] The first pin 21 and the second pin 22 each have a first portion close to the chip 10 and a second portion away from the chip 10, the first portion of the first pin 21 and the lead pad 11 corresponding to the first pin 21 are connected via the bonding wire 30, and the first portion of the second pin 22 and the lead pad 11 corresponding to the second pin 22 are connected via the bonding wire 30. Exemplarily, the bonding wire 30 is, for example, a gold wire, a silver wire, or a copper wire.

[0033] It should be noted that for a multi-pin LQFP (Low-profile Quad Flat Package) structure, the larger the area, the longer the bonding wire. Each millimeter of bonding wire has an inductance of 1nH, and the longer the bonding wire, the greater the inductance effect.

[0034] In the present application, the first part of the first pin 21 is located above the second pin 22, and the distance that the first pin 21 extends laterally from the plastic package 40 is greater than the distance that the second pin 22 extends laterally from the plastic package 40, that is, the second pin 22 is arranged within the spatial range where the first pin 21 extends, and the width of the chip packaging structure will not be increased additionally, and the length of the bonding wire 30 connecting the pin and the lead pad 11 does not need to be lengthened. In other words, when the chip packaging structure has a considerable number of pins, the length of the bonding wire 30 is shortened, thereby reducing the inductance effect of the chip packaging structure.

[0035] refer to Figure 1As shown, the plastic package 40 wraps the chip 10, the plurality of bonding wires 30, the first portion of the first pin 21 and the first portion of the second pin 22, the second portions of the first pin 21 and the second pin 22 both extend out of the side wall of the plastic package 40, and the bottom surface of the plastic package 40 is on the same side as the back surface of the chip. Exemplarily, the material of the plastic package 40 includes but is not limited to epoxy molding compound (EMC).

[0036] Exemplary, reference Figure 1 As shown, the second pin 22 extends in the plane 41 where the bottom surface of the plastic package body is located, and the second pin 22 is a straight strip pin; the first pin 21 is a bent strip pin and bends from the middle of the thickness direction of the plastic package body 40 to the bottom surface of the plastic package body 40.

[0037] Figures 2 to 4 1 is a top view of a chip packaging structure according to different embodiments of the present invention.

[0038] like Figures 2 to 4 As shown, in the chip packaging structure, the number of the first pins 21 and the number of the second pins 22 are both multiple, and on the side of the plastic package 40, the extension space of the multiple first pins 21 covers the extension space of the multiple second pins 22.

[0039] In one embodiment, the orthographic projections of the first pin 21 and the second pin 22 in the plane 41 where the bottom surface of the plastic package body is located do not overlap. Figure 3 As shown, a plurality of the first pins 21 and a plurality of the second pins 22 are alternately arranged on the side of the chip 10 , and the orthographic projections of adjacent first pins 21 and second pins 22 in the plane 41 where the bottom surface of the plastic package is located do not overlap.

[0040] In some embodiments of the present application, in the plane 41 where the bottom surface of the plastic package body is located, the orthographic projection of the first pin 21 and the orthographic projection of the second pin 22 at least partially overlap, which helps to reduce the area of ​​the chip packaging structure.

[0041] In one embodiment, a plurality of the first pins 21 and a plurality of the second pins 22 are alternately arranged on the side of the chip 10, and the orthographic projections of adjacent first pins 21 and second pins 22 in the plane 41 where the bottom surface of the plastic package is located partially overlap. Figure 1 and Figure 3 As shown, taking the first pin 21 and the second pin 22 as an example, both the first pin 21 and the second pin 22 are elongated in a direction away from the chip 10, and for adjacent first pins 21 and second pins 22, the edge portion of the first pin 21 and the edge portion of the second pin 22 overlap.

[0042] In one embodiment, reference Figure 1 and Figure 2 As shown, a second pin 22 is arranged directly below a first pin 21 , and in a plane 41 where the bottom surface of the plastic package body is located, an orthographic projection of the second pin 22 is located within an orthographic projection of the first pin 21 above it, that is, a first pin 21 covers a second pin 22 .

[0043] like Figures 2 to 4 As shown, on the outside of the plastic package body 40 , the length of the first pin 21 is greater than the length of the second pin 22 thereunder.

[0044] refer to Figure 1 As shown, in this embodiment, the second part of the first pin 21 extends to the plane 41 where the bottom surface of the plastic package body is located. Specifically, the end of the first pin 21 away from the chip 10 is located in the plane 41 where the bottom surface of the plastic package body is located and serves as the mounting part of the first pin 21; the second pin 22 extends in the plane 41 where the bottom surface of the plastic package body is located, and the second part of the second pin 22 extends laterally from the bottom surface of the plastic package body 40 to the plastic package body 40, so that the mounting parts of the first pin 21 and the second pin 22 are located in the same plane, which facilitates the electrical connection of the second parts of the first pin 21 and the second pin 22 with other components such as the substrate.

[0045] The chip package structure of this embodiment may be an LQFP package structure, but is not limited thereto. Those skilled in the art should easily understand the details of the present application and that the present application is applicable to all lead package types and their variants.

[0046] The chip packaging structure provided by the utility model includes a chip 10, a first pin 21, a second pin 22, a plurality of bonding wires 30 and a plastic package 40, wherein the first pin 21 and the second pin 22 both have a first portion close to the chip 10 and a second portion away from the chip 10, the first portion of the first pin 21 and the lead pad 11 corresponding to the first pin 21 are connected through the bonding wire 30, and the first portion of the second pin 22 and the lead pad 11 corresponding to the second pin 22 are connected through the bonding wire 30; the plastic package 40 wraps the chip 10, the plurality of bonding wires 30, the first portion of the first pin 21 and the first portion of the second pin 22, the second portions of the first pin 21 and the second pin 22 both extend out of the side wall of the plastic package 40, and the plastic package 40 has a bottom surface on the same side as the back of the chip 10 ; wherein, the second pin 22 extends within the plane 41 where the bottom surface of the plastic package body is located, the first pin 21 is located above the second pin 22, and the distance that the first pin 21 extends laterally from the plastic package body 40 is greater than the distance that the second pin 22 extends laterally from the plastic package body 40. In this way, the second pin 22 is arranged within the spatial range where the first pin 21 extends, and the width of the chip packaging structure will not be increased additionally. The number of pins of the chip packaging structure can be increased without increasing the area of ​​the chip packaging structure. The length of the bonding wire 30 connecting the pin and the lead pad 11 does not need to be lengthened. In other words, when the chip packaging structure has a considerable number of pins, the area of ​​the chip packaging structure is reduced, and the length of the bonding wire is shortened, thereby reducing the inductance effect of the chip packaging structure, solving the problem of signal integrity caused by ground bounce caused by large inductance ground, that is, the signal integrity can be improved.

[0047] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation on the scope of rights of the utility model. Any technical personnel in this field can make possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the protection scope of the technical solution of the utility model.

Claims

1. A chip packaging structure, characterized in that: It includes a chip, at least one first pin, at least one second pin, a plurality of bonding wires and a plastic package; The chip has a front side and a back side facing oppositely, and the front side of the chip has a plurality of lead pads; The first pin and the second pin each have a first portion close to the chip and a second portion far from the chip, the first portion of the first pin and the lead pad corresponding to the first pin are connected via the bonding wire, and the first portion of the second pin and the lead pad corresponding to the second pin are connected via the bonding wire; The plastic package body wraps the chip, the plurality of bonding wires, the first portion of the first pin and the first portion of the second pin, the second portions of the first pin and the second pin both extend out of the side wall of the plastic package body, and the plastic package body has a bottom surface on the same side as the back surface of the chip; The second pin extends in the plane where the bottom surface of the plastic package body is located, the first part of the first pin is located above the second pin, and the distance that the first pin extends laterally out of the plastic package body is greater than the distance that the second pin extends laterally out of the plastic package body.

2. The chip packaging structure according to claim 1, characterized in that: In the plane where the bottom surface of the plastic package body is located, the orthographic projection of the first lead and the orthographic projection of the second lead at least partially overlap.

3. The chip packaging structure according to claim 1, characterized in that: The first pin is a bent strip pin and is bent from the middle of the plastic package body in the thickness direction toward the bottom surface of the plastic package body; the second pin is a straight strip pin.

4. The chip packaging structure according to claim 1, characterized in that: The orthographic projections of the first pin and the second pin in the plane where the bottom surface of the plastic package body is located do not overlap.

5. The chip packaging structure according to claim 1, characterized in that: The orthographic projections of the first pin and the second pin in the plane where the bottom surface of the plastic package body is located partially overlap.

6. The chip packaging structure according to claim 1, characterized in that: In the plane where the bottom surface of the plastic package body is located, the orthographic projection of one of the second pins is located within the orthographic projection of one of the first pins above the second pin.

7. The chip packaging structure according to claim 1, characterized in that: The second portion of the first pin extends into the plane where the bottom surface of the plastic package body is located.

8. The chip packaging structure according to claim 1, characterized in that: The lead frame of the chip packaging structure includes the first pin, the second pin and a chip pad, the back side of the chip is attached to the chip pad, and the first pin and the second pin are arranged around the chip pad.

9. The chip packaging structure according to claim 1, characterized in that: The lead pads are distributed in the edge area of ​​the front side of the chip.

10. The chip packaging structure according to claim 1, characterized in that: The chip includes a plurality of side edges, the number of the first pins and the number of the second pins are both plural, and the plurality of the first pins and the plurality of the second pins are alternately arranged on the side edges of the chip.

Images