Electronic package
By providing dislocated and uninterrupted recesses on both sides of the core plate, the chip offset or skew caused by the semiconductor package in the prior art is solved, and the precise alignment and effective electrical connection between the conductive blind holes and electronic components is realized, thereby improving the reliability of the product.
Patent Information
- Application Number
- CN202421436923.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-06-13
- Filing Date
- 2024-06-21
- Publication Date
- 2025-04-04
- Estimated Expiration
- 2034-06-21
AI Technical Summary
When existing semiconductor packages fill the dielectric layer, they may cause the semiconductor chip to shift or skew, affecting the accuracy of subsequent electrical connections and product reliability.
There are dislocated and not penetrated recesses on both sides of the core plate to accommodate electronic components. When the insulating layer is filled with the recess, offset or skew of the electronic components is avoided, thereby achieving accurate alignment and effective electrical connection between the conductive blind holes and the electronic components.
Through the precise alignment design, the reliability of the product is improved, the effective electrical connection between the conductive blind holes and the electronic components is ensured, and the reliability problems caused by offset or skew are reduced.
Smart Images
Figure CN222720432U_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a semiconductor packaging technology, in particular to an electronic packaging component. Background Art
[0002] With the evolution of semiconductor packaging technology, semiconductor devices have developed different packaging types. Among them, semiconductor devices mainly set chips on a packaging substrate, and the chips are electrically connected to the packaging substrate, and then the chips are coated with packaging colloid. In order to meet the demand for thinning, the industry has embedded the chips in a packaging substrate to reduce the volume of the entire semiconductor device and improve the electrical performance, which has become a packaging trend.
[0003] Figures 1A to 1G It is a cross-sectional schematic diagram of a method for manufacturing a conventional semiconductor package 1 .
[0004] like Figure 1A As shown, a core board 10 is provided, wherein the upper and lower sides of the core board 10 have wiring layers 101 , and at least one conductive through hole 102 electrically connecting the wiring layers 101 is formed in the core board 10 .
[0005] like Figure 1B As shown, an opening 100 penetrating the core board 10 is formed on the core board 10 .
[0006] like Figure 1C As shown, a semiconductor chip 11 having a plurality of electrode pads 110 is accommodated in the opening 100 .
[0007] like Figure 1D As shown, a dielectric layer 14 is pressed on the upper and lower sides of the core board 10 , so that the dielectric layer 14 fills the opening 100 to cover the semiconductor chip 11 .
[0008] like Figure 1E As shown, a plurality of blind holes 140 are formed on the dielectric layer 14 so that a portion of the surface of each of the electrode pads 110 and the wiring layer 101 is exposed through the blind holes 140 .
[0009] like Figure 1F As shown, a circuit layer 13 is formed on each of the dielectric layers 14 , and the circuit layer 13 forms a plurality of conductive blind vias 130 in each of the blind vias 140 that electrically connect the electrode pad 110 and the wiring layer 101 .
[0010] like Figure 1G As shown, a solder mask 15 is formed on each of the dielectric layer 14 and the circuit layer 13 , and a plurality of openings 150 are formed on the solder mask 15 so that a portion of the surface of the circuit layer 13 is exposed through the openings 150 .
[0011] However, in the manufacturing method of the conventional semiconductor package 1, an opening 100 needs to be formed in the core board 10 to place the semiconductor chip 11. If the depth D of the opening 100 is greater than the thickness H of the semiconductor chip 11, when the dielectric layer 14 is filled into the opening 100, the semiconductor chip 11 will be impacted and the semiconductor chip 11 will be offset (e.g., Figure 1D As shown, the left and right spacings t1 and t2 between the semiconductor chip 11 and the hole wall of the opening 100 are different (where t1<t2), or even skewed, so that in the subsequent process, the electrode pad 110 of the semiconductor chip 11 cannot be accurately aligned with the blind hole 140, resulting in the conductive blind hole 130 and the electrode pad 110 failing to be effectively electrically connected, thereby resulting in poor product reliability.
[0012] Therefore, how to avoid the shortcomings of the prior art has become a topic that needs to be solved urgently. Utility Model Content
[0013] In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic package, including: a core board, which has a first side and a second side opposite to each other, and a first recess and a second recess that do not penetrate the core board are respectively provided on the first side and the second side; a first electronic component, which is arranged in the first recess; a second electronic component, which is arranged in the second recess; an insulating layer, which is arranged on the first side and the second side of the core board and filled in the first recess and the second recess to cover the first electronic component and the second electronic component; a circuit layer, which is arranged on the insulating layer; and a plurality of conductive blind holes, which are arranged in the insulating layer to electrically connect the circuit layer with the first electronic component and the second electronic component.
[0014] The present invention also provides a method for manufacturing an electronic package, including: providing a core board having a first side and a second side opposite to each other, and respectively providing a first recess and a second recess that do not penetrate the core board on the first side and the second side; placing a first electronic component in the first recess, and placing a second electronic component in the second recess; forming an insulating layer on the first side and the second side of the core board, and filling the first recess and the second recess with the insulating layer to cover the first electronic component and the second electronic component; and forming a circuit layer on the insulating layer, and forming a plurality of conductive blind holes in the insulating layer, so that the plurality of conductive blind holes electrically connect the circuit layer with the first electronic component and the second electronic component.
[0015] In the aforementioned electronic package and the manufacturing method thereof, the position of the first recess is not aligned with the position of the second recess.
[0016] In the aforementioned electronic package and the manufacturing method thereof, the position of the first electronic component is not aligned with the position of the second electronic component.
[0017] In the aforementioned electronic package and its manufacturing method, the first side and the second side are provided with wiring layers respectively; and the core board is provided with conductive through holes electrically connected to the wiring layers.
[0018] In the aforementioned electronic packaging component and its manufacturing method, the insulating layer has a plurality of blind holes, so that the conductive blind holes are formed in the blind holes.
[0019] From the above, it can be seen that the electronic package of the present invention mainly accommodates the first electronic component and the second electronic component by opening offset and non-through recesses on both sides of the core board, so that when the insulating layer is filled into the first recess and the second recess, the first electronic component and the second electronic component will not be offset or skewed. Therefore, compared with the prior art, when making the blind hole, the first electronic component and the second electronic component can be precisely aligned with the blind hole, so that each of the conductive blind holes can be effectively electrically connected to the first electronic component and the second electronic component, so as to improve the reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figures 1A to 1G The cross-sectional view is a schematic diagram of a conventional method for manufacturing a semiconductor package.
[0021] Figures 2A to 2G A schematic cross-sectional view of a method for manufacturing an electronic package of the present invention.
[0022] Main component symbols
[0023] 1 Semiconductor Package
[0024] 10,20 core board
[0025] 100 Open
[0026] 101,201 Wiring Layer
[0027] 102,202 Conductive vias
[0028] 11. Semiconductor Chip
[0029] 110,210,220 Electrode pads
[0030] 13,23 Circuit layer
[0031] 130,230 Conductive blind vias
[0032] 14 Dielectric layer
[0033] 140,240 Blind holes
[0034] 15 Solder mask
[0035] 150,250 Opening
[0036] 2 Electronic packaging
[0037] 20a First side
[0038] 20b Second side
[0039] 203 Plug material
[0040] 21 First Electronic Components
[0041] 22 Second electronic component
[0042] 21a, 22a Active surface
[0043] 21b, 22b Non-active surface
[0044] 211,221 Conductive bumps
[0045] 24 Insulation layer
[0046] 25 Insulation protective layer
[0047] 26 Adhesive layer
[0048] D,D1,D2 Depth
[0049] H,H1,H2 Thickness
[0050] S1 first recess
[0051] S2 second recess
[0052] t1,t2 spacing. DETAILED DESCRIPTION
[0053] The following describes the implementation of the present invention through specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
[0054] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this creation, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by this creation, should still fall within the scope of the technical content disclosed by this creation. At the same time, the terms such as "upper", "first", "second", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of this creation. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of this creation without substantially changing the technical content.
[0055] Figures 2A to 2G A cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention.
[0056] like Figure 2A As shown, a core board 20 is provided, which has a first side 20a and a second side 20b opposite to each other, and has a wiring layer 201 on the first side 20a and the second side 20b respectively, and at least one conductive through hole 202 electrically connecting the wiring layers 201 is formed in the core board 20.
[0057] In this embodiment, the core board 20 may be a board material including bismaleimidetriazine (BT), prepreg (PP) or other boards, and the wiring layer 201 may be formed by electroplating metal (such as copper) or other methods.
[0058] Furthermore, the conductive via 202 is a hollow copper column, and the hollow part thereof can be filled with a plugging material 203. For example, the plugging material 203 can be an insulating material or a conductive material, etc., without any particular limitation. It should be understood that in other embodiments, the conductive via 202 can also be a solid metal column without being filled with the plugging material 203.
[0059] like Figure 2B As shown, a first recess S1 is formed on the first side 20 a of the core board 20 , and a second recess S2 is formed on the second side 20 b of the core board 20 , so that the position of the first recess S1 is not aligned with the position of the second recess S2 .
[0060] In this embodiment, the position of the first concave portion S1 and the position of the second concave portion S2 are offset from each other.
[0061] Furthermore, the first recess S1 and / or the second recess S2 may be formed by drilling, etching, laser or other methods. It should be understood that the first recess S1 and the second recess S2 may be formed by the same or different methods.
[0062] like Figure 2C As shown, the first electronic component 21 is placed in the first concave portion S1 , and the second electronic component 22 is placed in the second concave portion S2 , so that the position of the first electronic component 21 is not aligned with the position of the second electronic component 22 .
[0063] In this embodiment, the first electronic component 21 can be an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the first electronic component 21 is a semiconductor chip having an active surface 21a and an inactive surface 21b opposite to each other, and the active surface 21a has a plurality of electrode pads 210, so that the first electronic component 21 is fixed in the first recess S1 with its inactive surface 21b through an adhesive layer 26, and the active surface 21a faces outward. Further, a conductive bump 211 such as a copper column can be formed on the electrode pad 210 as required.
[0064] Furthermore, the second electronic component 22 can be an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. For example, the second electronic component 22 is a semiconductor chip having an active surface 22a and an inactive surface 22b opposite to each other, and the active surface 22a has a plurality of electrode pads 220, so that the second electronic component 22 is fixed in the second recess S2 with its inactive surface 22b through an adhesive layer 26, so that the active surface 22a faces outward. Further, a conductive bump 221 such as a copper column can be formed on the electrode pad 220 as required.
[0065] In addition, the thickness H1 of the first electronic component 21 (together with the adhesive layer 26 ) is greater than or equal to the depth D1 of the first recess S1 , and the thickness H2 of the second electronic component 22 (together with the adhesive layer 26 ) is greater than or equal to the depth D2 of the second recess S2 .
[0066] In addition, the position of the first electronic component 21 and the position of the second electronic component 22 are offset from each other.
[0067] like Figure 2D As shown, an insulating layer 24 is formed on the first side 20 a and the second side 20 b of the core board 20 , so that the insulating layer 24 fills the first recess S1 and the second recess S2 .
[0068] In this embodiment, the insulating layer 24 is a dielectric layer, such as Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.
[0069] like Figure 2E As shown, a plurality of blind holes 240 are formed on each of the insulating layers 24 so that each of the electrode pads 210 , 220 (or each of the conductive bumps 211 , 221 ) is exposed through the blind holes 240 .
[0070] In this embodiment, the blind holes 240 may be formed by drilling, etching, laser, exposure and development or other patterning methods, and the blind holes 240 may expose a portion of the surface of the wiring layer 201 as required.
[0071] like Figure 2F As shown, a circuit layer 23 is formed on each of the insulating layers 24 , and a plurality of conductive blind vias 230 electrically connecting the electrode pads 210 , 220 (or each of the conductive bumps 211 , 221 ) and the wiring layer 201 are formed in each of the blind vias 240 .
[0072] In this embodiment, the circuit layer 23 and the conductive blind via 230 can be integrally formed by electroplating metal (such as copper) or other methods.
[0073] like Figure 2G As shown, an insulating protection layer 25 is formed on each of the insulating layer 24 and the circuit layer 23 , and a plurality of openings 250 are formed on the insulating protection layer 25 so that a portion of the surface of the circuit layer 23 is exposed through the openings 250 .
[0074] In this embodiment, the insulating protection layer 25 is a solder resist material such as green paint, ink or other materials.
[0075] Therefore, the invention mainly provides recesses that are offset and not penetrated on both sides of the core board 20 to accommodate the first electronic component 21 and the second electronic component 22, so that when the insulating layer 24 is filled into the first recess S1 (and / or the second recess S2), the first electronic component 21 (and / or the second electronic component 22) will not be offset or skewed. Therefore, compared with the prior art, when making the blind hole 240, the invention can accurately align the electrode pads 210, 220 with the blind hole 240, so that each of the conductive blind holes 230 and each of the electrode pads 210, 220 can be effectively electrically connected to improve the reliability of the product. In addition, the first recess S1 and the second recess S2 do not penetrate the core board 20, so that multiple electronic components can be embedded on both sides of the core board 20, thereby improving the electrical function of the overall electronic package.
[0076] Furthermore, by designing that the position of the first recess S1 is not aligned with the position of the second recess S2 (or the position of the first electronic component 21 is not aligned with the position of the second electronic component 22), the impact force of the insulating layer 24 on the first electronic component 21 and the second electronic component 22 when filling the first recess S1 and the second recess S2 is reduced, thereby better ensuring the positioning of the first electronic component 21 and the second electronic component 22 to avoid problems such as deviation or skewness of the first electronic component 21 and the second electronic component 22.
[0077] The present invention also provides an electronic package 2, including: a core board 20, at least one first recess S1, at least one second recess S2, at least one first electronic component 21, at least one second electronic component 22, an insulating layer 24, a circuit layer 23 and a plurality of conductive blind vias 230.
[0078] The core board 20 has a first side 20 a and a second side 20 b opposite to each other, and has a first concave portion S1 and a second concave portion S2 on the first side 20 a and the second side 20 b respectively.
[0079] The first electronic component 21 is disposed in the first recess S1 .
[0080] The second electronic component 22 is disposed in the second recess S2 .
[0081] The insulating layer 24 is disposed on the first side 20 a and the second side 20 b of the core board 20 and is filled into the first recess S1 and the second recess S2 to cover the first electronic component 21 and the second electronic component 22 .
[0082] The circuit layer 23 is disposed on the insulating layer 24 .
[0083] The conductive blind vias 230 are disposed in the insulating layer 24 to electrically connect the circuit layer 23 with the first electronic component 21 and the second electronic component 22 .
[0084] In one embodiment, the position of the first recess S1 is not aligned with the position of the second recess S2 .
[0085] In one embodiment, the position of the first electronic component 21 is not aligned with the position of the second electronic component 22 .
[0086] In one embodiment, the insulating layer 24 has a plurality of blind holes 240 , so that the conductive blind vias 230 are formed in the blind holes 240 .
[0087] In summary, the electronic package of the present invention opens offset and non-through recesses on both sides of the core board to accommodate electronic components, so that when the insulating layer is filled into the recess, the electronic components will not be offset or skewed. Therefore, the electronic components of the present invention can be effectively electrically connected with the conductive blind holes to improve the reliability of the product.
[0088] The above embodiments are only used to illustrate the principle and efficacy of the invention, and are not used to limit the invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the invention. Therefore, the scope of protection of the invention should be as listed in the claims.
Claims
1. An electronic package, characterized in that: include: A core board having a first side and a second side opposite to each other, and a first recess and a second recess which do not penetrate the core board are respectively provided on the first side and the second side; A first electronic component is disposed in the first recess; A second electronic component is disposed in the second recess; An insulating layer is disposed on the first side and the second side of the core board and is filled into the first recess and the second recess to cover the first electronic component and the second electronic component; A circuit layer, which is disposed on the insulating layer; as well as A plurality of conductive blind holes are disposed in the insulating layer to electrically connect the circuit layer with the first electronic element and the second electronic element.
2. The electronic package according to claim 1, wherein: The position of the first recess is not aligned with the position of the second recess.
3. The electronic package according to claim 1, wherein: The position of the first electronic component is not aligned with the position of the second electronic component.
4. The electronic package of claim 1, wherein: The first side and the second side are respectively provided with wiring layers.
5. The electronic package as claimed in claim 4, characterized in that The core board is formed with a conductive through hole electrically connected to the wiring layer.
6. The electronic package according to claim 1, wherein: The insulating layer has a plurality of blind holes, so that the conductive blind holes are formed in the blind holes.