GPIO circuit of edge computer
By using level converters, RC filtering circuits and multi-stage lightning protection modules in the GPIO circuit of edge computers, the problems of insufficient driving force and poor noise resistance of the GPIO port of the traditional computing power module are solved, and the IO interface design with high driving ability, noise resistance and waterproof is realized.
Patent Information
- Application Number
- CN202421267562.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-05
- Publication Date
- 2025-04-11
- Estimated Expiration
- 2034-06-05
AI Technical Summary
The GPIO port of the traditional computing power module is directly driven externally, with insufficient driving force and poor anti-noise interference capability, unable to prevent high-power surges, and the IO interface does not have a waterproof design, and there is a lack of filtering processing in the circuit.
A GPIO circuit for edge computers was designed, using a level converter to increase the GPIO level of the computing power module, from 1.8V to 5V, enhance the driving capability, and combine RC filtering circuits and multi-stage lightning protection modules to enhance noise and lightning protection capabilities, and at the same time, waterproof connectors are used to support waterproof design.
Through the use of level converters, high driving capability and high-speed output are achieved. RC filtering and multi-stage lightning protection modules effectively prevent noise interference and surge damage. The waterproof connector ensures the waterproof capability of the IO interface.
Smart Images
Figure CN222748970U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a GPIO circuit of an edge computer. Background Art
[0002] The general-purpose input / output (GPIO) circuit is a functional module frequently used in chips, which can realize functions such as digital input, digital output, and analog input by configuring registers.
[0003] High computing power modules are now commonly used in the field of V2X edge computing. For example, computing power modules are used as the core processor unit of V2X edge computers. V2X edge computers are designed with external GPIO ports for collecting or outputting external IO signals. In existing designs, the GPIO provided by computing power modules is often used for collecting or outputting external IO signals. However, in existing designs, Figure 1 The GPIO port of the computing power module is only connected to a simple ESD tube for electrostatic protection, and then the external IO signal is connected.
[0004] In the prior art, the use of the GPIO port provided by the computing power module to collect or output external IO signals has the following problems:
[0005] 1. In the existing design, the GPIO port inside the computing power module is directly driven externally, and the driving capability is weak.
[0006] 2. The GPIO port provided by the existing computing power module is at a 1.8V level, and its anti-noise interference ability is not as good as that of the 5V or 3.3V IO port; that is, the GPIO port is at a 1.8V level and is easily interfered when used externally.
[0007] 3. It only provides electrostatic protection, but cannot prevent high-power surges. After the device is struck by lightning, the IO circuit is easily damaged, and the computing power module will be damaged. That is, if the GPIO port of the computing power module is used directly, it is easy to be damaged by surges in the signal line.
[0008] 4. The connector used in the IO interface is not a waterproof connector and does not support waterproof design.
[0009] 5. The circuit is not filtered and is easily interfered by external high-frequency pulse noise signals.
[0010] Therefore, the GPIO port of the traditional computing power module is directly driven externally, and insufficient driving force is a technical problem that technical personnel in this field urgently need to solve.
[0011] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Utility Model Content
[0012] An embodiment of the present application provides a GPIO circuit for an edge computer to solve the technical problem that the GPIO port of a traditional computing power module is directly driven externally and has insufficient driving force.
[0013] The GPIO circuit of the edge computer of the embodiment of the present application includes:
[0014] Computing power module;
[0015] A level converter; wherein:
[0016] The pin GPIO13 of the computing power module is connected to the pin A1 of the level converter; wherein the pin GPIO13 of the computing power module outputs GPIO13-first level, and the pin B1 of the level converter outputs GPIO13-second level;
[0017] The pin GPIO14 of the computing power module is connected to the pin A2 of the level converter; wherein, the pin GPIO14 of the computing power module outputs GPIO14-first level, and the pin B2 of the level converter outputs GPIO14-second level.
[0018] The embodiment of the present application adopts the above technical solution, which has the following technical effects:
[0019] The GPIO circuit of the edge computer of the embodiment of the present application has two output ports of IO functions. The two output ports of the IO functions use the GPIO13 pin and the GPIO14 pin of the computing power module. The GPIO13 pin of the computing power module outputs the GPIO13-first level, and the GPIO14 pin of the computing power module outputs the GPIO14-first level. The GPIO13-first level (such as 1.8V) is upgraded by the level converter to form the GPIO13-second level (such as 5V), and the pin B1 of the level converter outputs the GPIO13-second level. Correspondingly, the GPIO14-first level (such as 1.8V) is upgraded by the level converter to form the GPIO14-second level (5V), and the pin B2 of the level converter outputs the GPIO14-second level. The level converter is used to realize directional data transmission from the pin A1 of the level converter to the pin B1 of the level converter, and from the pin A2 of the level converter to the pin B2 of the level converter. When the GPIO output signal (GPIO13-first level and GPIO14-first level) is boosted (e.g., from 1.8V to 5V), a high current (e.g., 12mA) high drive can be achieved, supporting a high rate (e.g., 200Mbps). The GPIO output signal of the GPIO circuit of the edge computer of the embodiment of the present application is boosted (e.g., from 1.8V to 5V), and the driving force is greater when driven externally, achieving a higher rate output. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0021] Figure 1 Schematic diagram designed for the existing GIPO circuit;
[0022] Figure 2 A schematic diagram of a GPIO circuit of an edge computer according to an embodiment of the present application;
[0023] Figure 3 A schematic diagram of a level converter of a GPIO circuit of an edge computer according to an embodiment of the present application;
[0024] Figure 4 A schematic diagram of the connection of an RC filter circuit, a first lightning protection module, and a second lightning protection module of a GPIO circuit of an edge computer according to an embodiment of the present application;
[0025] Figure 5 A schematic diagram of a waterproof connector for a GPIO circuit of an edge computer according to an embodiment of the present application. DETAILED DESCRIPTION
[0026] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.
[0027] Embodiment 1
[0028] like Figure 2 , Figure 3 As shown, a GPIO circuit of an edge computer in an embodiment of the present application includes:
[0029] Computing power module;
[0030] A level converter that increases and decreases the signal of the computing power module; wherein:
[0031] The pin GPIO13 of the computing power module is connected to the pin A1 of the level converter; wherein the pin GPIO13 of the computing power module outputs GPIO13-first level, and the pin B1 of the level converter outputs GPIO13-second level, and the GPIO13-first level is increased to form GPIO13-second level;
[0032] The pin GPIO14 of the computing power module is connected to the pin A2 of the level converter; wherein, the pin GPIO14 of the computing power module outputs GPIO14-first level, and the pin B2 of the level converter outputs GPIO14-second level, and the GPIO14-first level is increased to form GPIO14-second level.
[0033] like Figure 1 As shown, specifically:
[0034] The pin A1 of the level converter is used as an input pin, and the pin B1 of the level converter is used as the corresponding output pin;
[0035] The pin A2 of the level converter serves as another input pin, and the pin B2 of the level converter serves as the corresponding output pin;
[0036] Pin B3 of the level converter serves as another input pin, and pin A3 of the level converter serves as the corresponding output pin;
[0037] The pin B4 of the level converter serves as another input pin, and the pin A4 of the level converter serves as the corresponding output pin.
[0038] The GPIO circuit of the edge computer of the embodiment of the present application has two output ports of IO functions. The two output ports of the IO functions use the GPIO13 pin and the GPIO14 pin of the computing power module. The GPIO13 pin of the computing power module outputs the GPIO13-first level, and the GPIO14 pin of the computing power module outputs the GPIO14-first level. The GPIO13-first level (such as 1.8V) is upgraded by the level converter to form the GPIO13-second level (such as 5V), and the pin B1 of the level converter outputs the GPIO13-second level. Correspondingly, the GPIO14-first level (such as 1.8V) is upgraded by the level converter to form the GPIO14-second level (5V), and the pin B2 of the level converter outputs the GPIO14-second level. The level converter is used to realize directional data transmission from the pin A1 of the level converter to the pin B1 of the level converter, and from the pin A2 of the level converter to the pin B2 of the level converter. When the GPIO output signal (GPIO13-first level and GPIO14-first level) is boosted (e.g., from 1.8V to 5V), a high current (e.g., 12mA) high drive can be achieved, supporting a high rate (e.g., 200Mbps). The GPIO output signal of the GPIO circuit of the edge computer of the embodiment of the present application is boosted (e.g., from 1.8V to 5V), and the driving force is greater when driven externally, achieving a higher rate output.
[0039] Specifically, the computing power module uses the Jetson AGX Orin module.
[0040] In implementation, such as Figure 2 and Figure 4 As shown, the GPIO circuit further includes an RC filter circuit and a first lightning protection module, and the RC filter circuit is connected to the level converter and the first lightning protection module respectively;
[0041] The first lightning protection module includes a first field effect transistor trigger TBU1 and a second field effect transistor trigger TBU2 for providing overcurrent protection;
[0042] Among them, the pin 1 of the first field effect transistor trigger TBU1 is connected to the RC filtering circuit to access the GPIO13-third level, and the GPIO13-second level is filtered to form the GPIO13-third level; the pin 2 of the first field effect transistor trigger TBU2 outputs the GPIO13-fourth level, and the GPIO13-third level is formed by the first field effect transistor trigger TBU2. The GPIO13-fourth level is used as the output signal OUT1;
[0043] Pin 1 of the second field effect transistor trigger TBU2 is connected to the RC filtering circuit to access the GPIO14-third level. The GPIO14-second level is filtered to form the GPIO14-third level. Pin 2 of the second field effect transistor trigger TBU2 outputs the GPIO14-fourth level. The GPIO14-third level is formed by the second field effect transistor trigger TBU2 to form the GPIO14-fourth level. The GPIO14-fourth level is used as the output signal OUT2.
[0044] When the third level current of GPIO13 exceeds the limit value, the first field effect transistor trigger TBU1 is disconnected internally to protect the back-end circuit.
[0045] When the third level current of GPIO14 exceeds the limit value, the second field effect transistor trigger TBU2 is disconnected internally to protect the back-end circuit.
[0046] In implementation, such as Figure 4 As shown, the first lightning protection module also includes a first gas discharge tube GDT1 for discharging most of the surge energy;
[0047] The e pin of the first gas discharge tube GDT1 is grounded, the a pin is connected to the pin 2 of the first field effect transistor trigger TBU1, and the b pin is connected to the pin 2 of the second field effect transistor trigger TBU2.
[0048] GPIO13-the fourth level is connected to the a pin of the first gas discharge tube GDT1, GPIO14-the fourth level is connected to the b pin of the second gas discharge tube GDT1, and the e pin of the first gas discharge tube GDT1 is connected to the device chassis ground, and the device chassis ground needs to be connected to the earth. When a surge occurs in the circuit, most of the energy can be released to the earth through the first gas discharge tube GDT1. GPIO13-the fourth level and GPIO14-the fourth level share a first gas discharge tube GDT1, which can save PCB design space.
[0049] In implementation, such as Figure 4 As shown, the first lightning protection module also includes a first dual-channel bidirectional TVS tube D1 for discharging residual surge energy and static electricity;
[0050] Among them, pin 3 of the first dual-channel bidirectional TVS tube D1 is grounded, pin 2 of the first dual-channel bidirectional TVS tube D1 is connected to the RC filter circuit to access GPIO13-third level, and pin 1 of the first dual-channel bidirectional TVS tube D1 is connected to the RC filter circuit to access GPIO14-third level.
[0051] GPIO13-the third level is connected in series with the first field effect tube trigger TBU1 and then connected to pin 2 of the first dual-channel bidirectional TVS tube D1. Pin 3 of the first dual-channel bidirectional TVS tube D1 is connected to the digital ground. The first dual-channel bidirectional TVS tube D1 is a dual-channel bidirectional TVS tube SMC05, which can discharge the residual surge energy in the circuit into the digital ground.
[0052] In implementation, such as Figure 4 As shown, the GPIO circuit also includes a waterproof connector, wherein:
[0053] Pin 1 of the waterproof connector is connected to pin 2 of the first field effect transistor trigger TBU1 to access GPIO13-fourth level, so that GPIO13-fourth level can be connected to an external device through the waterproof connector, that is, GPIO13-fourth level is used as the output signal OUT1;
[0054] Pin 7 of the waterproof connector is connected to pin 2 of the second field effect transistor trigger TBU2 to access GPIO14-fourth level, so that GPIO14-fourth level can be connected to another external device through the waterproof connector, that is, GPIO14-fourth level is used as the output signal OUT2;
[0055] Pins 2, 4, 8 and 10 of the waterproof connector are connected to the digital ground signal.
[0056] The waterproof connector can achieve IP67 level waterproof.
[0057] In implementation, such as Figure 4 As shown, the GPIO circuit also includes a second lightning protection module; the second lightning protection module includes a third field effect transistor trigger TBU3 and a fourth field effect transistor trigger TBU4 that provide overcurrent protection;
[0058] Among them, the pin 1 of the third field effect transistor trigger TBU3 is connected to the RC filter circuit, the pin 2 of the third field effect transistor trigger TBU3 and the pin 3 of the waterproof connector are connected to access the GPIO15-fourth level as the input signal IN1, and the pin 1 of the third field effect transistor trigger TBU3 outputs the GPIO15-third level;
[0059] Pin 1 of the fourth field effect transistor trigger TBU4 is connected to the RC filtering circuit, pin 2 of the fourth field effect transistor trigger TBU4 and pin 9 of the waterproof connector are connected to access GPIO16-fourth level as the input signal IN2, and pin 1 of the fourth field effect transistor trigger TBU4 outputs GPIO16-third level.
[0060] The GPIO15-fourth level is converted into the GPIO15-third level after passing through the third field effect transistor trigger TBU3, and the GPIO16-fourth level is converted into the GPIO16-third level after passing through the fourth field effect transistor trigger TBU4.
[0061] Specifically, the waterproof connector can be connected to an external device to receive the input signal IN1 , and the waterproof connector can be connected to another external device to receive the input signal IN2 .
[0062] The third field effect transistor trigger TBU3 and the fourth field effect transistor trigger TBU4 play corresponding roles to the first field effect transistor trigger TBU1 and the second field effect transistor trigger TBU2.
[0063] In implementation, such as Figure 4 As shown, the second lightning protection module also includes a second gas discharge tube GDT2 for discharging most of the surge energy;
[0064] Among them, the e pin of the second gas discharge tube GDT2 is grounded, the a pin is connected to the pin 2 of the third field effect transistor trigger TBU3, and the b pin is connected to the pin 2 of the fourth field effect transistor trigger TBU4.
[0065] The second gas discharge tube GDT2 plays a corresponding role to the first gas discharge tube GDT1.
[0066] In implementation, such as Figure 4 As shown, the second lightning protection module also includes a second dual-channel bidirectional TVS tube D2 for discharging residual surge energy and static electricity;
[0067] Among them, pin 3 of the second dual-channel bidirectional TVS tube D2 is grounded, pin 2 of the second dual-channel bidirectional TVS tube D2 is connected to pin 1 of the fourth field effect tube trigger TBU4, and pin 1 of the second dual-channel bidirectional TVS tube D2 is connected to pin 1 of the third field effect tube trigger TBU4.
[0068] The second dual-channel bidirectional TVS tube D2 and the first dual-channel bidirectional TVS tube D1 play corresponding roles.
[0069] Specifically, the first dual-channel bidirectional TVS tube D1 is a device for the IO output channel, and the second dual-channel bidirectional TVS tube D2 is a device for the input channel, so the capacitors (the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4) are placed in different positions.
[0070] In implementation, such as Figure 2 and Figure 3As shown, GPIO15-third level is output through the RC filter circuit to GPIO15-second level, and GPIO16-third level is output through the RC filter circuit to GPIO16-second level;
[0071] The pin B3 of the level converter is connected to the RC filter circuit to access the GPIO15-second level; the pin A3 of the level converter is connected to the pin GPIO15 of the computing power module to input the GPIO15-first level, and the GPIO15-second level is reduced to form the GPIO15-first level;
[0072] Pin B4 of the level converter is connected to the RC filter circuit to access GPIO16-second level; pin A4 of the level converter is connected to pin GPIO16 of the computing power module to access GPIO16-first level, and the GPIO16-second level is reduced to form GPIO16-first level.
[0073] In implementation, such as Figure 5 As shown, the RC filter circuit includes:
[0074] A first resistor R1 is connected to the output signal low level pin B1 of the level converter and the pin 1 of the first field effect transistor trigger TBU1;
[0075] A first capacitor C1, wherein one plate of the first capacitor C1 is grounded, and the other plate is connected to a side of the first resistor R1 close to the first lightning protection module;
[0076] A second resistor R2 is connected to the output signal low level pin B2 of the level converter and the pin 1 of the second field effect transistor trigger TBU2;
[0077] A second capacitor C2, wherein one plate of the second capacitor C2 is grounded, and the other plate is connected to a side of the second resistor R2 close to the first lightning protection module;
[0078] A third resistor R3 is connected to the input signal low level pin B3 of the level converter and the pin 1 of the third field effect transistor trigger TBU3;
[0079] A third capacitor C3, one plate of the third capacitor C3 is grounded, and the other plate is connected to a side of the third resistor R3 close to the level converter;
[0080] A fourth resistor R4 is connected to the input signal low level pin B4 of the level converter and the pin 1 of the fourth field effect transistor trigger TBU4;
[0081] A fourth capacitor C4, one electrode plate of the fourth capacitor C4 is grounded, and the other electrode plate is connected to a side of the fourth resistor R4 close to the level converter.
[0082] In the implementation, the level converter adopts a 4-bit directional voltage level converter of TXU0204; the VCCA pin of TXU0204 is connected to a 1.8V power supply, the VCCB pin is connected to a 5V power supply, and the level conversion of TXU0204 is set to a conversion from 1.8V to 5V;
[0083] The first dual-channel bidirectional TVS tube D1 and the second dual-channel bidirectional TVS tube D2 each use a dual-channel bidirectional TVS tube SMC05;
[0084] The first field effect transistor trigger TBU1, the second field effect transistor trigger TBU2, the third field effect transistor trigger TBU3 and the fourth field effect transistor trigger TBU4 are each a field effect transistor trigger TBU-CA065-100-WH;
[0085] The first gas discharge tube GDT1 and the second gas discharge tube GDT2 are each a gas discharge tube 3R090A-5SS.
[0086] The GPIO circuit of the edge computer of the utility model is a method for designing off-board GPIO functions using the internal GPIO port of the computing power module (corresponding to pins GPIO13, GPIO14, GPIO15, and GPIO16). A level conversion circuit (corresponding to a level converter), an RC filter circuit, and a lightning protection circuit (including a first lightning protection module and a second lightning protection module) are designed in the GPIO circuit of the edge computer, and the GPIO port in the GPIO circuit of the edge computer is connected to the outside through a waterproof connector. Therefore, the GPIO signal of the GPIO circuit of the edge computer of the utility model has the capabilities of being waterproof, surge-proof, anti-static, and having strong driving capabilities, thereby making the IO interface of the edge computer waterproof, surge-proof, anti-static, and having driving capabilities.
[0087] The GPIO circuit of the edge computer has two IO function output ports and two IO function input ports. The two IO function output ports use the GPIO13 and GPIO14 pins of the computing power module, and the two IO function input ports use the GPIO15 and GPIO16 pins of the computing power module. The GPIO signal is converted by the level converter TXU0204, and then connected to the RC filter circuit and the lightning protection circuit in turn, and then connected to the outside world through the waterproof connector MX23A12NF1.
[0088] The computing power module is a high computing power module developed by NVIDA, which can be used as a processor unit of an edge computer. In the utility model, the GPIO13 pin, GPIO14 pin, GPIO15 pin, and GPIO16 pin of the computing power module are used to realize the IO interface function of edge computing.
[0089] The level converter uses the 4-bit directional voltage level converter TXU0204 from Texas Instruments (TI). The directional data transmission from A1 to B1, A2 to B2, B3 to A3, B4 to A4 is realized through the level converter TXU0204. At 5V, it can achieve a high drive current of 12mA and support a maximum rate of 200Mbps.
[0090] The lightning protection circuit includes a primary lightning protection circuit, a secondary lightning protection circuit, and a tertiary lightning protection circuit.
[0091] The waterproof connector uses the MX23A12NF1 connector of Japan Aviation Electronics (JAE), which provides 12 pins and can achieve IP67 level waterproofing.
[0092] like Figure 2 As shown in the figure, the GPIO13, GPIO14, GPIO15 and GPIO16 pins of the computing power module are connected to the A1, A2, A3 and A4 pins of TXU0204 respectively. Among them, the GPIO13 and GPIO14 pins are used as IO output ports, which can achieve 5V level output. Among them, the GPIO15 and GPIO16 pins are used as IO input ports, which can detect the status of the external 5V level.
[0093] The VCCA pin of TXU0204 is connected to a 1.8V power supply, and the VCCB pin is connected to a 5V power supply. The level conversion of TXU0204 is set to 1.8V to 5V conversion, realizing directional data transmission from A1 to B1, A2 to B2, B3 to A3, and B4 to A4. The OE pin of TXU0204 is configured to work enable mode through the pull-up resistor R3.
[0094] The GPIO signal processed by TXU0204 is connected to the RC filter circuit for filtering, and then enters the lightning protection circuit.
[0095] RC filter circuit and lightning protection circuit such as Figure 4 As shown. The lightning protection processing of the 4-way IO interface circuits all goes through the first-level lightning protection circuit, the second-level lightning protection circuit, and the third-level lightning protection circuit. The first-level lightning protection circuit uses the gas discharge tube 3R090A-5SS (i.e., the first gas discharge tube GDT1 and the second gas discharge tube GDT2), the second-level lightning protection circuit uses the field effect tube trigger TBU-CA065-100-WH of Bourns (i.e., the first field effect tube trigger TBU1 and the second field effect tube trigger TBU2, the third field effect tube trigger TBU3 and the fourth field effect tube trigger TBU4), and the third-level lightning protection circuit is composed of a dual-channel bidirectional TVS tube SMC05 (i.e., the first dual-channel bidirectional TVS tube D1 and the second dual-channel bidirectional TVS tube D2).
[0096] The output signal OUT1 and the output signal OUT2 are output signals of the GPIO circuit of the edge computer, and the input signal IN1 and the input signal IN2 are input signals of the GPIO circuit of the edge computer.
[0097] The output signal OUT1 is connected to the a pin of the gas discharge tube GDT1, and the e pin of GDT1 is connected to the chassis ground of the device, which needs to be connected to the earth. When a surge occurs in the circuit, most of the energy can be released to the earth through GDT1.
[0098] The output signal OUT1 is processed by GDT1 and then connected in series with TBU1. When the current of the output signal OUT1 exceeds the limit value, TBU1 is disconnected internally to protect the back-end circuit.
[0099] The output signal OUT1 is connected in series with TBU1 and then connected to the 2nd pin of D1. The 3rd pin of D1 is connected to the digital ground. D1 is a dual-channel bidirectional TVS tube SMC05, which can discharge the residual surge energy in the circuit to the digital ground. Through this three-level lightning protection circuit, the IO interface can be protected against lightning surges.
[0100] The output signal OUT1 is finally processed by the RC filter circuit and then connected to the level conversion circuit (ie, the level converter).
[0101] Similarly, the output signal OUT2, input signal IN1, and input signal IN2 are also processed by the 3-level lightning protection circuit and RC filter circuit.
[0102] The output signal OUT1 and the output signal OUT2 share a gas discharge tube GDT1 and a TVS tube D1, which can save PCB design space.
[0103] The input signal IN1 and the input signal IN2 share a gas discharge tube GDT2 and a TVS tube D2, which can save PCB design space.
[0104] During PCB design, GDT1, GDT2, TBU1, TBU2, TBU3, TBU4, D1, and D2 devices should be placed close to the waterproof connector, and the width of the signal trace from the waterproof connector to the TVS tube should be greater than 15 mil to ensure that the PCB trace meets the power requirements for lightning surge discharge.
[0105] The IO interface connector uses the MX23A12NF1 waterproof connector from Japan Aviation Electronics (JAE). Pin 1 of the waterproof connector is connected to OUT1, pin 7 is connected to OUT2, pin 3 is connected to IN1, and pin 9 is connected to IN2. Pins 2, 4, 8, and 10 of the connector are connected to the digital ground signal. The waterproof connector is soldered on the PCB board.
[0106] Compared with the prior art, the utility model has the following advantages:
[0107] 1. It contains 2 IO output ports and 2 IO input ports, and has IO input and output channels. The GPIO port of the computing module can achieve higher rate output and input status detection. The 2 output ports of the IO function use the GPIO13 and GPIO14 pins of the computing module, and the 2 input ports of the IO function use the GPIO15 and GPIO16 pins of the computing module.
[0108] 2. The design uses dual-channel gas discharge tubes and TVS tubes to facilitate device layout and signal routing and reduce PCB area. The two IO output ports share a gas discharge tube (GDT1) and a TVS tube (D1). The two IO input ports share a gas discharge tube (GDT2) and a TVS tube (D2).
[0109] 3. There are three levels of protection in the lightning protection circuit. The first level uses a gas discharge tube to discharge most of the surge energy. The second level uses a field effect transistor trigger (TBU) to provide overcurrent protection. The third level uses a TVS tube to further discharge the residual surge energy and static electricity.
[0110] 4. When designing the PCB, the GDT1, GDT2, TBU1, TBU2, TBU3, TBU4, D1, and D2 devices should be placed close to the connector, and the width of the signal trace from the waterproof connector to the TVS tube should be greater than 15 mil to ensure that the PCB trace meets the power requirements for lightning surge discharge.
[0111] 5. The interface is also subjected to RC filtering after passing through the lightning protection circuit.
[0112] 6. The circuit uses a 4-bit directional voltage level converter TXU0204 to process the IO level conversion from 1.8V to 5V, which can improve the driving capability and noise suppression ability of the IO interface.
[0113] 7. The GPIO port in this circuit is connected to the outside through a waterproof connector to make the IO interface waterproof.
[0114] In the description of the present application and its embodiments, it should be understood that the orientation or positional relationship indicated by the terms "top", "bottom", "height", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0115] In the present application and its embodiments, unless otherwise clearly specified and limited, the terms "set", "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.
[0116] In the present application and its embodiments, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0117] The disclosure above provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.
[0118] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0119] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A GPIO circuit of an edge computer, characterized in that: include: Computing power module; A level converter; wherein: The pin GPIO13 of the computing power module is connected to the pin A1 of the level converter; wherein the pin GPIO13 of the computing power module outputs GPIO13-first level, and the pin B1 of the level converter outputs GPIO13-second level; The pin GPIO14 of the computing power module is connected to the pin A2 of the level converter; wherein, the pin GPIO14 of the computing power module outputs GPIO14-first level, and the pin B2 of the level converter outputs GPIO14-second level.
2. The GPIO circuit according to claim 1, characterized in that: It also includes an RC filter circuit and a first lightning protection module, wherein the RC filter circuit is connected to the level converter and the first lightning protection module respectively; The first lightning protection module includes a first field effect transistor trigger TBU1 and a second field effect transistor trigger TBU2 for providing overcurrent protection; Among them, the pin 1 of the first field effect transistor trigger TBU1 is connected to the RC filter circuit to access the GPIO13-third level, and the GPIO13-second level is filtered to form the GPIO13-third level; the pin 2 of the first field effect transistor trigger TBU2 outputs the GPIO13-fourth level; Pin 1 of the second field effect transistor trigger TBU2 is connected to the RC filtering circuit to access GPIO14-third level, and the GPIO14-second level is filtered to form GPIO14-third level, and pin 2 of the second field effect transistor trigger TBU2 outputs GPIO14-fourth level.
3. The GPIO circuit according to claim 2, characterized in that: The first lightning protection module also includes a first gas discharge tube GDT1 for discharging most of the surge energy; The e pin of the first gas discharge tube GDT1 is grounded, the a pin is connected to the pin 2 of the first field effect transistor trigger TBU1, and the b pin is connected to the pin 2 of the second field effect transistor trigger TBU2.
4. The GPIO circuit according to claim 3, characterized in that: The first lightning protection module also includes a first dual-channel bidirectional TVS tube D1 for discharging residual surge energy and static electricity; Among them, pin 3 of the first dual-channel bidirectional TVS tube D1 is grounded, pin 2 of the first dual-channel bidirectional TVS tube D1 is connected to the RC filter circuit to access GPIO13-third level, and pin 1 of the first dual-channel bidirectional TVS tube D1 is connected to the RC filter circuit to access GPIO14-third level.
5. The GPIO circuit according to claim 4, characterized in that: Also included is a waterproof connector, wherein: Pin 1 of the waterproof connector is connected to pin 2 of the first field effect transistor trigger TBU1 to access GPIO13-fourth level, and GPIO13-fourth level is used as the output signal OUT1; Pin 7 of the waterproof connector is connected to pin 2 of the second field effect transistor trigger TBU2 to access GPIO14-fourth level, and GPIO14-fourth level is used as the output signal OUT2; Pins 2, 4, 8 and 10 of the waterproof connector are connected to the digital ground signal.
6. The GPIO circuit according to claim 5, characterized in that: It also includes a second lightning protection module; the second lightning protection module includes a third field effect transistor trigger TBU3 and a fourth field effect transistor trigger TBU4 for providing overcurrent protection; Among them, the pin 1 of the third field effect transistor trigger TBU3 is connected to the RC filter circuit, the pin 2 of the third field effect transistor trigger TBU3 and the pin 3 of the waterproof connector are connected to access the GPIO15-fourth level as the input signal IN1, and the pin 1 of the third field effect transistor trigger TBU3 outputs the GPIO15-third level; Pin 1 of the fourth field effect transistor trigger TBU4 is connected to the RC filtering circuit, pin 2 of the fourth field effect transistor trigger TBU4 and pin 9 of the waterproof connector are connected to access GPIO16-fourth level as the input signal IN2, and pin 1 of the fourth field effect transistor trigger TBU4 outputs GPIO16-third level.
7. The GPIO circuit according to claim 6, characterized in that: The second lightning protection module also includes a second gas discharge tube GDT2 for discharging most of the surge energy; Among them, the e pin of the second gas discharge tube GDT2 is grounded, the a pin is connected to the pin 2 of the third field effect transistor trigger TBU3, and the b pin is connected to the pin 2 of the fourth field effect transistor trigger TBU4.
8. The GPIO circuit according to claim 7, characterized in that: The second lightning protection module also includes a second dual-channel bidirectional TVS tube D2 for discharging residual surge energy and static electricity; Among them, pin 3 of the second dual-channel bidirectional TVS tube D2 is grounded, pin 2 of the second dual-channel bidirectional TVS tube D2 is connected to pin 1 of the fourth field effect tube trigger TBU4, and pin 1 of the second dual-channel bidirectional TVS tube D2 is connected to pin 1 of the third field effect tube trigger TBU4.
9. The GPIO circuit according to claim 8, characterized in that: GPIO15-third level is output through the RC filter circuit as GPIO15-second level, and GPIO16-third level is output through the RC filter circuit as GPIO16-second level; The pin B3 of the level converter is connected to the RC filter circuit to access the GPIO15-second level; the pin A3 of the level converter is connected to the pin GPIO15 of the computing power module to input the GPIO15-first level, and the GPIO15-second level is reduced to form the GPIO15-first level; Pin B4 of the level converter is connected to the RC filter circuit to access GPIO16-second level; the output signal high level pin A4 of the level converter is connected to pin GPIO16 of the computing power module to access GPIO16-first level, and the GPIO16-second level is reduced to form GPIO16-first level.
10. The GPIO circuit according to claim 9, characterized in that: The RC filter circuit includes: A first resistor R1 is connected to the output signal low level pin B1 of the level converter and the pin 1 of the first field effect transistor trigger TBU1; A first capacitor C1, wherein one plate of the first capacitor C1 is grounded, and the other plate is connected to a side of the first resistor R1 close to the first lightning protection module; A second resistor R2 is connected to the output signal low level pin B2 of the level converter and the pin 1 of the second field effect transistor trigger TBU2; A second capacitor C2, wherein one plate of the second capacitor C2 is grounded, and the other plate is connected to a side of the second resistor R2 close to the first lightning protection module; A third resistor R3 is connected to the input signal low level pin B3 of the level converter and the pin 1 of the third field effect transistor trigger TBU3; A third capacitor C3, one plate of the third capacitor C3 is grounded, and the other plate is connected to the The third resistor R3 is close to one side of the level converter; A fourth resistor R4 is connected to the input signal low level pin B4 of the level converter and the pin 1 of the fourth field effect transistor trigger TBU4; A fourth capacitor C4, one electrode plate of the fourth capacitor C4 is grounded, and the other electrode plate is connected to a side of the fourth resistor R4 close to the level converter.