An analog switch

Abstract

The utility model provides an analog switch, the analog switch comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube. When the analog switch is turned on, the on-potential of the first circuit node is determined by the third NMOS tube or the fourth NMOS tube, which solves the problems of the influence of the first PMOS tube and the second PMOS tube on the threshold voltage and the increase of the on-resistance due to the substrate bias effect, and ensures that the first PMOS tube and the second PMOS tube are fully turned on. Correspondingly, the on-potential of the second circuit node is determined by the third PMOS tube or the fourth PMOS tube, which solves the problems of the influence of the first NMOS tube and the second NMOS tube on the threshold voltage and the increase of the on-resistance due to the substrate bias effect, and ensures that the first NMOS tube and the second NMOS tube are fully turned on. In this way, the leakage risk caused by the crosstalk between the second voltage end and the first voltage end of the analog switch is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, in particular to an analog switch. Background Art

[0002] Analog switches are devices that can pass or block analog signals and are mainly used for the interface between analog signals and digital control. With the development of integrated circuits in recent years, the switching performance of analog switches has been greatly improved. They can operate at very low operating voltages, have low on-resistance, and small package sizes. They are widely used in test equipment, communication products, and multimedia systems.

[0003] Currently, a transmission gate circuit is usually used as an analog switch. The transmission gate circuit includes a PMOS tube and an NMOS tube connected in parallel. Since there is a bias effect (body effect) between the substrate of the PMOS tube and the substrate of the NMOS tube, and the bias effect affects the substrate of the PMOS tube and the threshold voltage of the NMOS tube, the on-resistance of the MOS tube will increase significantly, or even turn off and fail to transmit analog signals. In this way, the transmission gate circuit cannot be regarded as a switch.

[0004] Figure 1 is a schematic diagram of an analog switch in the prior art. Figure 1 In order to solve the influence of bias effect on the threshold voltage of MOS tube, the following method is adopted: Figure 1 The analog switch shown includes a PMOS tube TP and an NMOS tube TN. The substrate and source of the PMOS tube TP are short-circuited and connected to the input terminal Vin of the analog switch. The input terminal Vin receives an analog signal. The substrate and source of the NMOS tube TN are short-circuited and connected to the input terminal Vin. The drain of the PMOS tube TP and the drain of the NMOS tube TN are both connected to the output terminal Vout. The gate of the PMOS tube TP receives a first control signal Ctr1, and the first control signal Ctr1 is used to control the on and off of the PMOS tube TP. The gate of the NMOS tube TN receives a second control signal Ctr2, and the second control signal Ctr2 is used to control the on and off of the NMOS tube RN. The structural arrangement of the analog switch can prevent the bias effect of the PMOS tube TP and the NMOS tube TN, thereby solving the problem caused by the substrate bias effect. However, the output terminal Vout of the analog switch will crosstalk the input terminal Vin, causing the analog switch to be unable to be turned off, causing a leakage risk. Utility Model Content

[0005] The utility model aims to provide an analog switch to solve the problem that the analog switch in the prior art cannot avoid the output end of the analog switch from crosstalking with the input end and causing leakage in the way of solving the bias effect of the MOS tube.

[0006] In order to solve the above technical problems, the utility model provides an analog switch, which includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; the analog switch has a first voltage terminal and a second voltage terminal;

[0007] The source and substrate of the third NMOS tube, the drain of the first PMOS tube, the drain of the first NMOS tube, and the source and substrate of the third PMOS tube are all connected to the first voltage end;

[0008] The source and substrate of the fourth NMOS tube, the drain of the second PMOS tube, the drain of the second NMOS tube, and the source and substrate of the fourth PMOS tube are all connected to the second voltage end;

[0009] The drain of the third NMOS tube, the source and substrate of the first PMOS tube, the drain of the fourth NMOS tube, and the source and substrate of the second PMOS tube are all connected to a first circuit node;

[0010] The source and substrate of the first NMOS tube, the drain of the third PMOS tube, the source and substrate of the second NMOS tube, and the drain of the fourth PMOS tube are all connected to a second circuit node;

[0011] The first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are turned on or off at the same time.

[0012] Optionally, the analog switch also includes a fifth PMOS tube, the source and substrate of the fifth PMOS tube are used to access the power supply voltage, and the drain of the fifth PMOS tube is connected to the first circuit node; when one of the fifth PMOS tube and the first PMOS tube is turned on, the other of the fifth PMOS tube and the first PMOS tube is turned off.

[0013] Optionally, the gate of the first NMOS tube, the gate of the second NMOS tube, the gate of the third NMOS tube, the gate of the fourth NMOS tube and the gate of the fifth PMOS tube are all used to access the first control signal, the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube are all used to access the second control signal, and the first control signal and the second control signal are complementary control signals.

[0014] Optionally, the analog switch also includes a fifth NMOS tube, the source and substrate of the fifth NMOS tube are grounded, and the drain of the fifth NMOS tube is connected to the second circuit node; when one of the fifth NMOS tube and the first NMOS tube is turned on, the other of the fifth NMOS tube and the first NMOS tube is turned off.

[0015] Optionally, the gate of the first NMOS tube, the gate of the second NMOS tube, the gate of the third NMOS tube and the gate of the fourth NMOS are all used to access the first control signal, the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube, the gate of the fourth PMOS tube and the gate of the fifth NMOS tube are all used to access the second control signal, and the first control signal and the second control signal are complementary control signals.

[0016] Optionally, when the first control signal is at a high level, the second control signal is at a low level; when the first control signal is at a low level, the second control signal is at a high level.

[0017] Optionally, one of the first voltage terminal and the second voltage terminal is a voltage input terminal, and the other of the first voltage terminal and the second voltage terminal is a voltage output terminal.

[0018] Optionally, when the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are all turned on, and the first voltage terminal is a voltage input terminal and the second voltage terminal is a voltage output terminal, the on-state potential at the first circuit node is determined through the third NMOS tube, and the on-state potential at the second circuit node is determined through the third PMOS tube.

[0019] Optionally, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are all turned on, the second voltage end is the voltage input end, and the first voltage end is the voltage output end, the on-state potential at the first circuit node is determined through the fourth NMOS tube, and the on-state potential at the second circuit node is determined through the fourth PMOS tube.

[0020] Optionally, the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are all deep N-well MOS transistors.

[0021] The analog switch as above includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube. When the analog switch is turned on, that is, the first to fourth PMOS tubes and the first to fourth NMOS tubes are all turned on, the substrate of the first PMOS tube and the substrate of the second PMOS tube are both connected to the first circuit node, and the on-state potential of the first circuit node is determined by the third NMOS tube or the fourth NMOS tube, which solves the problems of the influence of the substrate bias effect on the threshold voltage and the increase of the on-state resistance of the first PMOS tube and the second PMOS tube, ensures that the first PMOS tube and the second PMOS tube are fully turned on, and can ensure that the first voltage end and the second voltage end of the analog switch will not be crosstalked through the first PMOS tube and the second PMOS tube. Accordingly, the substrate of the first NMOS tube and the substrate of the second NMOS tube are both connected to the second circuit node, and the conduction potential of the second circuit node is determined by the third PMOS tube or the fourth PMOS tube, which solves the problems of the influence of the substrate bias effect on the threshold voltage and the increase of the conduction resistance of the first NMOS tube and the second NMOS tube, ensures that the first NMOS tube and the second NMOS tube are fully turned on, and can ensure that the first voltage end and the second voltage end of the analog switch will not crosstalk through the first NMOS tube and the second NMOS tube. In this way, the leakage risk caused by the second voltage end of the analog switch crosstalking the first voltage end (or the first voltage end crosstalking the second voltage end) is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Those skilled in the art should understand that the drawings provided are for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0023] Figure 1 is a schematic diagram of an analog switch in the prior art;

[0024] Figure 2 It is a schematic diagram of an analog switch according to an embodiment of the utility model. DETAILED DESCRIPTION

[0025] In order to make the purpose, advantages and features of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0026] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "the proximal end" and "the distal end" generally refer to two corresponding parts, which not only include the endpoints, and the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. In addition, as used in the present invention, an element disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements may be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element may be in any orientation such as inside, outside, above, below or on one side of another element, unless otherwise clearly indicated in the content. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] Figure 2 Schematic diagram of an analog switch of an embodiment of the utility model. Figure 2As shown, the utility model provides an analog switch, which includes a first PMOS tube TP1, a second PMOS tube TP2, a third PMOS tube TP3, a fourth PMOS tube TP4, a first NMOS tube TN1, a second NMOS tube TN2, a third NMOS tube TN3 and a fourth NMOS tube TN4; the analog switch has a first voltage terminal A and a second voltage terminal B. The source and substrate of the third NMOS tube TN3, the drain of the first PMOS tube TP1, the drain of the first NMOS tube TN1, and the source and substrate of the third PMOS tube TP3 are all connected to the first voltage terminal A, which can also be understood as the source and substrate of the third NMOS tube TN3, the drain of the first PMOS tube TP1, the drain of the first NMOS tube TN1, and the source and substrate of the third PMOS tube TP3 are connected together as the first voltage terminal A of the analog switch; the source and substrate of the fourth NMOS tube TN4, the drain of the second PMOS tube TP2, the drain of the second NMOS tube TN2, and the source and substrate of the fourth PMOS tube TP4 are all connected to the second voltage terminal B, which can also be understood as the source and substrate of the fourth NMOS tube TN4, the drain of the second PMOS tube TP2, the drain of the second NMOS tube TN2, and the source and substrate of the fourth PMOS tube TP4. The source and substrate of the PMOS tube TP4 are connected together as the second voltage terminal B; the drain of the third NMOS tube TN3, the source and substrate of the first PMOS tube TP1, the drain of the fourth NMOS tube TN4, and the source and substrate of the second PMOS tube TP2 are all connected to the first circuit node Y1. The source and substrate of the first NMOS tube TN1, the drain of the third PMOS tube TP3, the source and substrate of the second NMOS tube TN2, and the drain of the fourth PMOS tube TP4 are all connected to the second circuit node Y2. The first PMOS tube TP1, the second PMOS tube TP2, the third PMOS tube TP3, the fourth PMOS tube TP4, the first NMOS tube TN1, the second NMOS tube TN2, the third NMOS tube TN3, and the fourth NMOS tube TN4 are turned on or off at the same time.Thus, the analog switch has two states, namely, an on state and an off state, wherein when the analog switch is in the on state, the first PMOS tube TP1, the second PMOS tube TP2, the third PMOS tube TP3, the fourth PMOS tube TP4, the first NMOS tube TN1, the second NMOS tube TN2, the third NMOS tube TN3 and the fourth NMOS tube TN4 are all on; when the analog switch is in the off state, the first PMOS tube TP1, the second PMOS tube TP2, the third PMOS tube TP3, the fourth PMOS tube TP4, the first NMOS tube TN1, the second NMOS tube TN2, the third NMOS tube TN3 and the fourth NMOS tube TN4 are all off (cut off). It can be understood that one of the first voltage terminal A and the second voltage terminal B is used as a voltage input terminal of the analog switch for receiving an analog signal, and the other of the first voltage terminal A and the second voltage terminal B is a voltage output terminal for outputting a signal passing through the analog switch.

[0028] As for the analog switch above, when the analog switch is in the on state, the substrate of the first PMOS tube TP1 and the substrate of the second PMOS tube TP2 are both connected to the first circuit node, and the on potential of the first circuit node is determined by the third NMOS tube TN3 or the fourth NMOS tube TN4, which solves the problems of the influence of the substrate bias effect on the threshold voltage and the increase of the on resistance of the first PMOS tube TP1 and the second PMOS tube TP2, ensures that the first PMOS tube TP1 and the second PMOS tube TP2 are fully turned on, and can ensure that the first voltage terminal A and the second voltage terminal B of the analog switch will not crosstalk through the first PMOS tube TP1 and the second PMOS tube TP2. Accordingly, the substrate of the first NMOS tube TN1 and the substrate of the second NMOS tube TN2 are both connected to the second circuit node, and the conduction potential of the second circuit node is determined by the third PMOS tube TP3 or the fourth PMOS tube TP4, which solves the problems of the influence of the substrate bias effect on the threshold voltage and the increase of the conduction resistance of the first NMOS tube TN1 and the second NMOS tube TN2, ensures that the first NMOS tube TN1 and the second NMOS tube TN2 are fully turned on, and can ensure that the first voltage terminal A and the second voltage terminal B of the analog switch will not crosstalk through the first NMOS tube TN1 and the second NMOS tube TN2. In this way, the leakage risk caused by the second voltage terminal B of the analog switch crosstalking the first voltage terminal A (or the first voltage terminal A crosstalking the second voltage terminal B) is solved.

[0029] Specifically, when the analog switch is in the on state, and the first voltage terminal A is the voltage input terminal, and the second voltage terminal B is the voltage output terminal, the voltage at the first circuit node and the voltage at the second circuit node are the same as the input voltage of the first voltage terminal A, the on potential at the first circuit node is determined through the third NMOS transistor TN3, and the on potential at the second circuit node is determined through the third PMOS transistor TP3. When the analog switch is in the on state, and the second voltage terminal B is the voltage input terminal, and the first voltage terminal A is the voltage output terminal, the voltage at the first circuit node and the voltage at the second circuit node are the same as the input voltage of the second voltage terminal B, the on potential at the first circuit node is determined through the fourth NMOS transistor TN4, and the on potential at the second circuit node is determined through the fourth PMOS transistor TP4. In this way, the problem of the first PMOS transistor TP1 and the second PMOS transistor TP2 caused by the substrate bias effect is solved, and the problem of the first NMOS transistor TN1 and the second NMOS transistor TN2 caused by the substrate bias effect is solved.

[0030] Preferably, the first PMOS transistor TP1, the second PMOS transistor TP2, the first NMOS transistor TN1 and the second NMOS transistor TN2 are all deep N-well MOS transistors, that is, the deep N-well process is used to further reduce the threshold voltage of the first PMOS transistor TP1, the second PMOS transistor TP2, the first NMOS transistor TN1 and the second NMOS transistor TN2.

[0031] Further, regarding the manner of controlling the first PMOS transistor TP1, the second PMOS transistor TP2, the third PMOS transistor TP3, the fourth PMOS transistor TP4, the first NMOS transistor TN1, the second NMOS transistor TN2, the third NMOS transistor TN3 and the fourth NMOS transistor TN4 to be turned on simultaneously, this embodiment can be implemented by a complementary first control signal Ctr1 and a second control signal Ctr2. Specifically, the gate of the first NMOS transistor TN1, the gate of the second NMOS transistor TN2, the gate of the third NMOS transistor TN3 and the gate of the fourth NMOS are all used to access the first control signal Ctr1, and the gate of the first PMOS transistor TP1, the gate of the second PMOS transistor TP2, the gate of the third PMOS transistor TP3 and the gate of the fourth PMOS transistor TP4 are all used to access the second control signal Ctr2. In this way, the first NMOS transistor TN1, the second NMOS transistor TN2, the third NMOS transistor TN3 and the fourth NMOS transistor TN4 are turned on or off at the same time by the first control signal Ctr1, and the first PMOS transistor TP1, the second PMOS transistor TP2, the third PMOS transistor TP3 and the fourth PMOS transistor TP4 are turned on or off at the same time by the second control signal Ctr2. Generally, the first control signal Ctr1 and the second control signal Ctr2 are complementary level signals. When the first control signal Ctr1 is at a high level, the second control signal Ctr2 is at a low level; when the first control signal Ctr1 is at a low level, the second control signal Ctr2 is at a high level. It can be understood by those skilled in the art that the high level signal is used to turn on the NMOS transistor and turn off the PMOS transistor; the low level signal is used to turn on the PMOS transistor and turn off the NMOS transistor.

[0032] Preferably, the analog switch further includes a fifth PMOS tube TP5, a source and a substrate of the fifth PMOS tube TP5 are both used to access the power supply voltage Vcc, and a drain of the fifth PMOS tube TP5 is connected to the first circuit node Y1. When one of the fifth PMOS tube TP5 and the first PMOS tube TP1 is turned on, the other of the fifth PMOS tube TP5 and the first PMOS tube TP1 is turned off, that is, the first NMOS tube TN1, the second NMOS tube TN2, the third NMOS tube TN3, the fourth NMOS tube TN4 and the fifth PMOS tube TP5 are turned on or off at the same time. In this way, when the analog switch is in the off state, it is ensured that the substrate of the first PMOS tube TP1 and the substrate of the second PMOS tube TP2 are pulled up to the power supply voltage Vcc through the fifth PMOS tube TP5, so the voltage on the substrate of the first PMOS tube TP1 is the highest voltage among the four terminals (source, drain, gate and substrate) of the first PMOS tube TP1, ensuring that the first PMOS tube TP1 can be completely turned off; similarly, the voltage on the substrate of the second PMOS tube TP2 is the highest voltage among the four terminals of the second PMOS tube TP2, ensuring that the second PMOS tube TP2 can be completely turned off, further reducing the leakage risk caused by the crosstalk between the first voltage terminal A and the second voltage terminal B. Regarding the specific method of simultaneously turning on or off the first NMOS tube TN1, the second NMOS tube TN2, the third NMOS tube TN3, the fourth NMOS tube TN4 and the fifth PMOS tube TP5, in one embodiment, the gate of the fifth PMOS tube TP5 is connected to the first control signal Ctr1 to achieve.

[0033] Preferably, the analog switch further includes a fifth NMOS tube TN5, a source and a substrate of the fifth NMOS tube TN5 are grounded, and a drain of the fifth NMOS tube TN5 is connected to the second circuit node Y2. When one of the fifth NMOS tube TN5 and the first NMOS tube TN1 is turned on, the other of the fifth NMOS tube TN5 and the first NMOS tube TN1 is turned off, that is, the first PMOS tube TP1, the second PMOS tube TP2, the third PMOS tube TP3, the fourth PMOS tube TP4 and the fifth NMOS tube TN5 are turned on or off at the same time. In this way, when the analog switch is in the off state, it is ensured that the substrate of the first NMOS tube TN1 and the substrate of the second NMOS tube TN2 are pulled down to ground through the fifth NMOS tube TN5, so the voltage on the substrate of the first NMOS tube TN1 is the lowest voltage among the four terminals (source, drain, gate and substrate) of the first NMOS tube TN1, ensuring that the first NMOS tube TN1 can be completely turned off; similarly, the voltage on the substrate of the second NMOS tube TN2 is the lowest voltage among the four terminals of the second NMOS tube TN2, ensuring that the second NMOS tube TN2 can be completely turned off, further reducing the leakage risk caused by the crosstalk between the first voltage terminal A and the second voltage terminal B. Regarding the specific manner of simultaneously turning on or off the first PMOS tube TP1, the second PMOS tube TP2, the third PMOS tube TP3, the first PNMOS tube and the fifth NMOS tube TN5, in one embodiment, the gate of the fifth NMOS tube TN5 is connected to the second control signal Ctr2 to achieve.

[0034] Although the utility model is disclosed as above with preferred embodiments, the above embodiments are not intended to limit the utility model. For any technician familiar with the art, without departing from the scope of the technical solution of the utility model, the above disclosed technical content can be used to make many possible changes and modifications to the technical solution of the utility model, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model still falls within the scope of protection of the technical solution of the utility model.

Claims

1. An analog switch, characterized in that: It includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; the analog switch has a first voltage terminal and a second voltage terminal; The source and substrate of the third NMOS tube, the drain of the first PMOS tube, the drain of the first NMOS tube, and the source and substrate of the third PMOS tube are all connected to the first voltage end; The source and substrate of the fourth NMOS tube, the drain of the second PMOS tube, the drain of the second NMOS tube, and the source and substrate of the fourth PMOS tube are all connected to the second voltage end; The drain of the third NMOS tube, the source and substrate of the first PMOS tube, the drain of the fourth NMOS tube, and the source and substrate of the second PMOS tube are all connected to a first circuit node; The source and substrate of the first NMOS tube, the drain of the third PMOS tube, the source and substrate of the second NMOS tube, and the drain of the fourth PMOS tube are all connected to a second circuit node; The first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are turned on or off at the same time.

2. The analog switch according to claim 1, wherein: The analog switch also includes a fifth PMOS tube, a source and a substrate of the fifth PMOS tube are both used to access the power supply voltage, and a drain of the fifth PMOS tube is connected to the first circuit node; when one of the fifth PMOS tube and the first PMOS tube is turned on, the other of the fifth PMOS tube and the first PMOS tube is turned off.

3. The analog switch according to claim 2, characterized in that: The gate of the first NMOS tube, the gate of the second NMOS tube, the gate of the third NMOS tube, the gate of the fourth NMOS tube and the gate of the fifth PMOS tube are all used to access the first control signal, the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube are all used to access the second control signal, and the first control signal and the second control signal are complementary control signals.

4. The analog switch according to claim 1, wherein: The analog switch also includes a fifth NMOS tube, a source and a substrate of the fifth NMOS tube are both grounded, and a drain of the fifth NMOS tube is connected to the second circuit node; when one of the fifth NMOS tube and the first NMOS tube is turned on, the other of the fifth NMOS tube and the first NMOS tube is turned off.

5. The analog switch according to claim 4, characterized in that: The gate of the first NMOS tube, the gate of the second NMOS tube, the gate of the third NMOS tube and the gate of the fourth NMOS are all used to access the first control signal, the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the third PMOS tube, the gate of the fourth PMOS tube and the gate of the fifth NMOS tube are all used to access the second control signal, and the first control signal and the second control signal are complementary control signals.

6. The analog switch according to claim 3 or 5, characterized in that: When the first control signal is at a high level, the second control signal is at a low level; when the first control signal is at a low level, the second control signal is at a high level.

7. The analog switch according to claim 1, wherein: One of the first voltage terminal and the second voltage terminal is a voltage input terminal, and the other of the first voltage terminal and the second voltage terminal is a voltage output terminal.

8. The analog switch according to claim 7, characterized in that: The first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are all turned on, and when the first voltage terminal is a voltage input terminal and the second voltage terminal is a voltage output terminal, the on-state potential at the first circuit node is determined through the third NMOS tube, and the on-state potential at the second circuit node is determined through the third PMOS tube.

9. The analog switch according to claim 7, characterized in that: The first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are all turned on, and when the second voltage end is a voltage input end and the first voltage end is a voltage output end, the on-state potential at the first circuit node is determined through the fourth NMOS tube, and the on-state potential at the second circuit node is determined through the fourth PMOS tube.

10. The analog switch according to claim 1, wherein: The first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are all deep N-well MOS transistors.

Images