Substrate switching circuit, electronic equipment

Abstract

The present application relates to the field of integrated circuits, and discloses a substrate switching circuit and an electronic device. The circuit includes: a first switch circuit, a second switch circuit, a first control circuit, and a second control circuit. The input end of the first switch circuit is connected to a first preset power supply, and the output end is configured to be connected to the substrate of the power tube; the input end of the second switch circuit is connected to a second preset power supply, and the output end is configured to be connected to the substrate of the power tube; the first end of the first control circuit is connected to the control end of the first switch circuit and the output end of the first switch circuit; the second end of the first control circuit is connected to the start signal supply end of the first switch circuit; the control end of the first control circuit is configured to receive an inverted power comparison signal; the first end of the second control circuit is connected to the control end of the second switch circuit; the second end of the second control circuit is connected to the start signal supply end of the second switch circuit; the control end of the second control circuit is configured to receive a power comparison signal. In this way, current backflow will not occur in the power tube.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a substrate switching circuit and an electronic device. Background Art

[0002] At present, there may be a situation in which current backflow in power tubes causes damage to internal working devices. For example, when the power tube is a PMOS tube (positive channel Metal Oxide Semiconductor, P-type metal oxide semiconductor field effect transistor), since the source and drain of the PMOS tube are P-type semiconductor materials, and the substrate is N-type semiconductor materials. If the substrate is connected to a low potential, the current may flow directly from the source or drain to the substrate, causing the phenomenon of current backflow.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Utility Model Content

[0004] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0005] The embodiments of the present application provide a substrate switching circuit and an electronic device to prevent current backflow in a power tube.

[0006] An embodiment of the present application provides a substrate switching circuit, including: a first switch circuit, wherein the input end of the first switch circuit is connected to a first preset power supply; the output end of the first switch circuit is configured to be connected to the substrate of a power tube; a second switch circuit, wherein the input end of the second switch circuit is connected to a second preset power supply; the output end of the second switch circuit is configured to be connected to the substrate of the power tube; a first control circuit, wherein the first end of the first control circuit is connected to the control end of the first switch circuit and the output end of the first switch circuit; the second end of the first control circuit is connected to the start signal supply end of the first switch circuit; the control end of the first control circuit is configured to receive an inverted power comparison signal; the power comparison signal is a result of comparing the first preset power supply with the second preset power supply; a second control circuit, wherein the first end of the second control circuit is connected to the control end of the second switch circuit; the second end of the second control circuit is connected to the start signal supply end of the second switch circuit; the control end of the second control circuit is configured to receive the power comparison signal.

[0007] In the above embodiment, the first switch circuit is connected to the first preset power supply, the second switch is connected to the second preset power supply, and the first control circuit and the second control circuit control the substrate of the power tube to connect to the first preset power supply or the second preset power supply according to the voltage of the first preset power supply and the voltage of the second preset power supply, so that the substrate of the power tube is always connected to a high potential, so that the current directly flows directly from the source or drain to the substrate due to the substrate being connected to a low potential. In addition, the phenomenon of current backflow in the power tube can be prevented, so as to protect the working components of the circuit board where the power tube is located from being damaged due to current backflow.

[0008] Optionally, the first switch circuit includes: a first controlled switch, a first end of the first controlled switch is connected to the first preset power supply, and a control end of the first controlled switch is connected to the first end of the first control circuit; and a second end of the first controlled switch is configured to be connected to a substrate of the power tube.

[0009] In the above embodiment, the first preset power supply and the substrate of the power tube can be controlled to be connected or disconnected through the first controlled switch, so that when the first preset power supply is greater than the second preset power supply, the substrate of the power tube is connected to the first preset power supply to keep the substrate of the power tube at a high potential.

[0010] Optionally, the second switch circuit includes: a second controlled switch, the second end of the second controlled switch is connected to the second preset power supply, and the control end of the second controlled switch is connected to the first end of the second control circuit; the first end of the second controlled switch is configured to be connected to the substrate of the power tube.

[0011] In the above embodiment, the second preset power supply and the substrate of the power tube can be controlled to be connected or disconnected through the second controlled switch, so that when the second preset power supply is greater than the first preset power supply, the substrate of the power tube is connected to the second preset power supply to keep the substrate of the power tube at a high potential.

[0012] Optionally, the second switch circuit further includes: a third controlled switch, wherein a first end of the third controlled switch is connected to a first end of the second controlled switch; a control end of the third controlled switch is connected to a control end of the second controlled switch; a second end of the third controlled switch is configured to be connected to a control end of a preset external PMOS tube; the external PMOS tube is used to control the on and off of the power tube; a fourth controlled switch, wherein a first end of the fourth controlled switch is connected to a first end of the second controlled switch; a control end of the fourth controlled switch is connected to a control end of the second controlled switch; and a second end of the fourth controlled switch is configured to be connected to the control end of the power tube.

[0013] In the above embodiment, after the fourth controlled switch is turned on, the gate voltage of the power tube is pulled up to control the power tube to be turned off. After the third controlled switch is turned on, the second end of the third controlled switch outputs a high level. Since the second end of the third controlled switch is connected to the gate of the PMOS in the external module, the PMOS in the external module is turned off, so that the external module will not affect the power tube.

[0014] Optionally, the first control circuit includes: a fifth controlled switch, wherein the control end of the fifth controlled switch is configured to receive the inverted power comparison signal; the second end of the fifth controlled switch is connected to the control end of the first switch circuit; a sixth controlled switch, wherein the control end of the sixth controlled switch is configured to receive a preset voltage; the second end of the sixth controlled switch is connected to the first end of the fifth controlled switch; the first end of the sixth controlled switch is connected to the start-up signal supply end of the first switch circuit; a first resistor, wherein one end of the first resistor is connected to the output end of the first switch circuit; and the other end of the first resistor is connected to the second end of the fifth controlled switch.

[0015] In the above embodiment, the signal connected to the gate of the first controlled switch can be controlled by turning on and off the fifth controlled switch, and the current in the first control circuit can be controlled by changing the preset voltage received by the control end of the sixth controlled switch and the resistance value of the first resistor, thereby changing the voltage transmitted to the gate of the first controlled switch to realize turning on and off of the first controlled switch.

[0016] Optionally, the second control circuit includes: a seventh controlled switch, a control end of the seventh controlled switch is configured to receive the power comparison signal; a second end of the seventh controlled switch is connected to the control end of the second switch circuit; an eighth controlled switch, a control end of the eighth controlled switch is configured to receive a preset voltage; a second end of the eighth controlled switch is connected to the first end of the seventh controlled switch; a first end of the eighth controlled switch is connected to a start-up signal supply end of the second switch circuit; a second resistor, one end of the second resistor is connected to the first preset power supply; and the other end of the second resistor is connected to the second end of the seventh controlled switch.

[0017] In the above embodiment, the signal connected to the gate of the second controlled switch can be controlled by turning on and off the seventh controlled switch, and the current in the second control circuit can be controlled by changing the preset voltage received by the control end of the eighth controlled switch and the resistance value of the second resistor, thereby changing the voltage transmitted to the gate of the second controlled switch to realize turning on and off of the second controlled switch.

[0018] Optionally, the substrate switching circuit further includes: a first clamping circuit, one end of the first clamping circuit is connected to the substrate of the power tube, and the other end of the first clamping circuit is connected to the first control circuit.

[0019] In the above implementation, by providing the first clamping circuit, the turn-on voltage of the first controlled switch can be controlled not to be too large, so as to avoid the first controlled switch from being broken down.

[0020] Optionally, the substrate switching circuit further includes: a second clamping circuit, one end of the second clamping circuit is connected to the first preset power supply, and the other end of the first clamping circuit is connected to the second control circuit.

[0021] In the above implementation, by providing the second clamping circuit, the turn-on voltage of the second controlled switch can be controlled not to be too large, so as to avoid the second controlled switch from being broken down.

[0022] Optionally, the substrate switching circuit further includes: an inverting circuit, an output end of the inverting circuit is connected to the control end of the first control circuit; and an input end of the inverting circuit is configured to receive the power comparison signal.

[0023] In the above implementation, the power comparison signal can be inverted by providing an inverting circuit, so that the control end of the first control circuit can receive the inverted power comparison signal.

[0024] An embodiment of the present application provides an electronic device, comprising the above-mentioned substrate switching circuit.

[0025] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0027] Figure 1 is a structural schematic diagram of a first substrate switching circuit provided in an embodiment of the present application;

[0028] Figure 2 is a structural schematic diagram of a second substrate switching circuit provided in an embodiment of the present application;

[0029] Figure 3 is a structural schematic diagram of a third substrate switching circuit provided in an embodiment of the present application;

[0030] Figure 4It is a structural schematic diagram of the fourth substrate switching circuit provided in an embodiment of the present application.

[0031] Reference numerals:

[0032] 1: first switch circuit; 2: second switch circuit; 3: first control circuit; 4: second control circuit; 5: first preset power supply; 6: substrate of power tube; 7: second preset power supply; 8: first start signal supply end; 9: second start signal supply end; 10: first PMOS tube; 11: first resistor; 12: first NMOS tube; 13: second NMOS tube; 14: third NMOS tube; 15: fourth NMOS tube; 16: second resistor; 17: second PMOS tube; 18: inverter; 19: third PMOS tube; 20: fourth PMOS tube; 21: fifth PMOS tube; 22: sixth PMOS tube; 23: seventh PMOS tube; 24: eighth PMOS tube; 25: ninth PMOS tube; 26: tenth PMOS tube. DETAILED DESCRIPTION

[0033] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0034] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0035] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0036] Unless otherwise stated, the term "plurality" means two or more.

[0037] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0038] Embodiment 1

[0039] Combination Figure 1 As shown, in an embodiment of the present application, a substrate switching circuit is provided, including: a first switch circuit 1, a second switch circuit 2, a first control circuit 3, and a second control circuit 4. Among them, the input end of the first switch circuit 1 is connected to the first preset power supply 5, and the output end of the first switch circuit 1 is configured to be connected to the substrate 6 of the power tube. The input end of the second switch circuit 2 is connected to the second preset power supply 7, and the output end of the second switch circuit 2 is configured to be connected to the substrate 6 of the power tube. The first end of the first control circuit 3 is connected to the control end of the first switch circuit 1 and the output end of the first switch circuit 1, and the second end of the first control circuit 3 is connected to the first start signal supply end 8, and the control end of the first control circuit 3 is configured to receive the inverted power comparison signal. The power comparison signal is the result of comparing the first preset power supply 5 with the second preset power supply 7. The first end of the second control circuit 4 is connected to the control end of the second switch circuit 2, and the second end of the second control circuit 4 is connected to the second start signal supply end 9, and the control end of the second control circuit 4 is configured to receive the power comparison signal. Among them, the start signal supply end of the first switch circuit is the first start signal supply end. The start signal supply end of the second switch circuit is the second start signal supply end.

[0040] In some embodiments, the first switch circuit may include: a first controlled switch, a first end of the first controlled switch connected to a first preset power source, a control end of the first controlled switch connected to a first end of the first control circuit; and a second end of the first controlled switch configured to be connected to a substrate of the power tube.

[0041] Among them, the first controlled switch can be a component in the prior art that is controlled to be turned on and off, such as: MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) tube, triode, relay, optocoupler, thyristor, etc., which is not limited here.

[0042] In some embodiments, the second switch circuit may include: a second controlled switch, wherein the second end of the second controlled switch is connected to the second preset power source, the control end of the second controlled switch is connected to the first end of the second control circuit, and the first end of the second controlled switch is configured to be connected to the substrate of the power tube.

[0043] Among them, the second controlled switch can be a component in the prior art that is controlled to be turned on and off, such as: MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor field effect transistor) tube, triode, relay, optocoupler, thyristor, etc., which is not limited here.

[0044] In some embodiments, the first control circuit may include: a fifth controlled switch, a sixth controlled switch and a first resistor. The control end of the fifth controlled switch is configured to receive the inverted power comparison signal, and the second end of the fifth controlled switch is connected to the control end of the first switch circuit. The control end of the sixth controlled switch is configured to receive a preset voltage, the second end of the sixth controlled switch is connected to the first end of the fifth controlled switch, and the first end of the sixth controlled switch is connected to the start signal supply end of the first switch circuit. One end of the first resistor is connected to the output end of the first switch circuit; the other end of the first resistor is connected to the second end of the fifth controlled switch.

[0045] Engineers can set the resistance of the first resistor according to the required current. For example, when VCC is 5V (volts) and the current on the second NMOS tube is 2.5uA (microamperes), the resistance of the first resistor is 1.5MΩ (megaohms). In this way, the voltage on the first resistor is large and the voltage at point A is low, so the gate-source voltage of the first PMOS tube is large and the pull-up capability is strong.

[0046] In some embodiments, the second control circuit may include: a seventh controlled switch, an eighth controlled switch, and a second resistor. The control end of the seventh controlled switch is configured to receive a power comparison signal, and the second end of the seventh controlled switch is connected to the control end of the second switch circuit. The control end of the eighth controlled switch is configured to receive a preset voltage, the second end of the eighth controlled switch is connected to the first end of the seventh controlled switch, and the first end of the eighth controlled switch is connected to the start signal supply end of the second switch circuit. One end of the second resistor is connected to the first preset power supply, and the other end of the second resistor is connected to the second end of the seventh controlled switch.

[0047] Among them, engineers can set the resistance value of the second resistor according to the required current size.

[0048] In some embodiments, the substrate switching circuit may further include: an inverter circuit, wherein an output terminal of the inverter circuit is connected to a control terminal of the first control circuit, and an input terminal of the inverter circuit is configured to receive a power supply comparison signal.

[0049] The inverting circuit may include an inverter, an output end of the inverter is connected to the control end of the first control circuit, and an input end of the inverter is configured to receive a power supply comparison signal.

[0050] Exemplarily, the first switch circuit may include: a first controlled switch. The second switch circuit may include: a second controlled switch. The first control circuit may include: a fifth controlled switch, a sixth controlled switch and a first resistor. The second control circuit may include: a seventh controlled switch, an eighth controlled switch and a second resistor. The first controlled switch is a first PMOS tube, the second controlled switch is a second PMOS tube, the fifth controlled switch is a first NMOS tube, the sixth controlled switch is a second NMOS tube, the seventh controlled switch is a third NMOS tube, and the eighth controlled switch is a fourth NMOS tube. The first preset power supply is 5V DC, and the second preset power supply is a battery. Combined with Figure 2 As shown, the source of the first PMOS tube 10 is connected to the first preset power supply (VCC), the gate of the first PMOS tube 10 is connected to the drain of the first NMOS tube 12, the drain of the first PMOS tube 10 is connected to one end of the first resistor 11, and the other end of the first resistor 11 is connected to the drain of the first NMOS tube 12. The drain of the first PMOS tube 10 is also configured to be connected to the substrate (BULK) of the power tube. The gate of the first NMOS tube 12 is connected to the output end of the inverter 18, and the input end of the inverter 18 is configured to receive the power comparison signal (bat_vin_con). The power supply end of the inverter 18 is connected to the third preset power supply (VDD), and the ground end of the inverter 18 is grounded (GND). The source of the first NMOS tube 12 is connected to the drain of the second NMOS tube 13, the gate of the second NMOS tube 13 is configured to receive the preset voltage (vbn1), and the source of the second NMOS tube 13 is grounded. The drain of the second PMOS tube 17 is connected to the second preset power supply (VBAT), the source of the second PMOS tube 17 is configured to be connected to the substrate of the power tube, and the gate of the second PMOS tube 17 is connected to one end of the second resistor 16 and the drain of the third NMOS tube 14. The other end of the second resistor 16 is connected to the first preset power supply. The gate of the third NMOS tube 14 is configured to receive a power comparison signal. The source of the third NMOS tube 14 is connected to the drain of the fourth NMOS tube 15, the gate of the fourth NMOS tube 15 is configured to receive a preset voltage, and the source of the fourth NMOS tube 15 is grounded. It can be understood that since the PMOS tube is turned on at a low level, the start signal supply end of the first switch circuit can be grounded, and similarly, the start signal supply end of the second switch circuit can also be grounded.

[0051] In some embodiments, the second switch circuit further includes: a third controlled switch and a fourth controlled switch. The first end of the third controlled switch is connected to the first end of the second controlled switch, the control end of the third controlled switch is connected to the control end of the second controlled switch, and the second end of the third controlled switch is configured to be connected to the control end of a preset external PMOS tube. The first end of the fourth controlled switch is connected to the first end of the second controlled switch, the control end of the fourth controlled switch is connected to the control end of the second controlled switch, and the second end of the fourth controlled switch is configured to be connected to the control end of the power tube. The external PMOS tube is used to shut down other circuits that affect the power tube, thereby controlling the on and off of the power tube.

[0052] Among them, the third controlled switch can be a component in the prior art that is controlled to be turned on and off, such as: MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor field effect transistor) tube, triode, relay, optocoupler, thyristor, etc., which is not limited here.

[0053] Among them, the fourth controlled switch can be a component in the prior art that is controlled to be turned on and off, such as: MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor field effect transistor) tube, triode, relay, optocoupler, thyristor, etc., which is not limited here.

[0054] It can be understood that the third controlled switch and the fourth controlled switch can be high-voltage independent devices to prevent the circuit from being broken down by the high voltage.

[0055] Exemplary, combined Figure 3 As shown, it is assumed that the first switch circuit may include: a first controlled switch. The second switch circuit may include: a second controlled switch. The first control circuit may include: a fifth controlled switch, a sixth controlled switch and a first resistor. The second control circuit may include: a seventh controlled switch, an eighth controlled switch and a second resistor. The first controlled switch is a first PMOS tube, the second controlled switch is a second PMOS tube, the third controlled switch is a third PMOS tube, and the fourth controlled switch is a fourth PMOS tube. The fifth controlled switch is a first NMOS tube, the sixth controlled switch is a second NMOS tube, the seventh controlled switch is a third NMOS tube, and the eighth controlled switch is a fourth NMOS tube. The first preset power supply is 5V DC, and the second preset power supply is a battery. Combined with Figure 3As shown, the source of the first PMOS tube 10 is connected to the first preset power supply, the gate of the first PMOS tube 10 is connected to the drain of the first NMOS tube 12, the drain of the first PMOS tube 10 is connected to one end of the first resistor 11, and the other end of the first resistor 11 is connected to the drain of the first NMOS tube 12. The drain of the first PMOS tube 10 is also configured to be connected to the substrate of the power tube. The gate of the first NMOS tube 12 is connected to the output end of the inverter 18, and the input end of the inverter 18 is configured to receive a power comparison signal. The power supply end of the inverter 18 is connected to the third preset power supply, and the ground end of the inverter 18 is grounded. The source of the first NMOS tube 12 is connected to the drain of the second NMOS tube 13, the gate of the second NMOS tube 13 is configured to receive a preset voltage, and the source of the second NMOS tube 13 is grounded. The drain of the second PMOS tube 17 is connected to the second preset power supply 7, the source of the second PMOS tube 17 is configured to be connected to the substrate of the power tube, and the source of the second PMOS tube 17 is also connected to the source of the third PMOS tube 19 and the source of the fourth PMOS tube 20. The gate of the second PMOS tube 17 is connected to the gate of the third PMOS tube 19, the gate of the fourth PMOS tube 20, one end of the second resistor 16 and the drain of the third NMOS tube 14. The other end of the second resistor 16 is connected to the first preset power supply 5. The gate of the third NMOS tube 14 is configured to receive a power comparison signal. The source of the third NMOS tube 14 is connected to the drain of the fourth NMOS tube 15, the gate of the fourth NMOS tube 15 is configured to receive a preset voltage, and the source of the fourth NMOS tube 15 is grounded. The drain of the third PMOS tube 19 is connected to the control end of the preset external PMOS tube. The drain of the fourth PMOS tube 20 is connected to the control end of the power tube.

[0056] In some embodiments, the substrate switching circuit further includes: a first clamping circuit, one end of which is connected to the substrate of the power tube, and the other end of which is connected to the first control circuit.

[0057] The first clamping circuit is composed of a plurality of PMOS transistors connected by diodes. It is understood that the number of PMOS transistors connected by diodes in the first clamping circuit can be set by engineers according to actual use requirements.

[0058] In some embodiments, the substrate switching circuit further includes: a second clamping circuit, one end of which is connected to the first preset power supply, and the other end of which is connected to the second control circuit.

[0059] The second clamping circuit is composed of a plurality of PMOS transistors connected by diodes. It is understood that the number of PMOS transistors connected by diodes in the second clamping circuit can be set by engineers according to actual use requirements.

[0060] Exemplarily, it is assumed that the first switch circuit may include: a first controlled switch. The second switch circuit may include: a second controlled switch. The first control circuit may include: a fifth controlled switch, a sixth controlled switch and a first resistor. The second control circuit may include: a seventh controlled switch, an eighth controlled switch and a second resistor. The first controlled switch is a first PMOS tube, the second controlled switch is a second PMOS tube, the third controlled switch is a third PMOS tube, and the fourth controlled switch is a fourth PMOS tube. The fifth controlled switch is a first NMOS tube, the sixth controlled switch is a second NMOS tube, the seventh controlled switch is a third NMOS tube, and the eighth controlled switch is a fourth NMOS tube. The first clamping circuit includes: a fifth PMOS tube, a sixth PMOS tube and a seventh PMOS tube. The second clamping circuit includes: an eighth PMOS tube, a ninth PMOS tube and a tenth PMOS tube. The first preset power supply is 5V DC, and the second preset power supply is a battery. Combined with Figure 4As shown, the source of the first PMOS tube 10 is connected to the first preset power supply, the gate of the first PMOS tube 10 is connected to the drain of the first NMOS tube 12, the drain of the first PMOS tube 10 is connected to one end of the first resistor 11, and the other end of the first resistor 11 is connected to the drain of the first NMOS tube 12. The drain of the first PMOS tube 10 is also configured to be connected to the substrate of the power tube. The source of the fifth PMOS tube 21 is connected to the drain of the first PMOS tube 10, the gate of the fifth PMOS tube 21 is connected to the drain of the fifth PMOS tube 21 and the source of the sixth PMOS tube 22, the gate of the sixth PMOS tube 22 is connected to the drain of the sixth PMOS tube 22 and the source of the seventh PMOS tube 23, and the gate of the seventh PMOS tube 23 is connected to the drain of the seventh PMOS tube 23 and the drain of the first NMOS tube 12. The gate of the first NMOS tube 12 is connected to the output end of the inverter 18, and the input end of the inverter 18 is configured to receive the power comparison signal. The power supply terminal of the inverter 18 is connected to the third preset power supply, and the ground terminal of the inverter 18 is grounded. The source of the first NMOS tube 12 is connected to the drain of the second NMOS tube 13, the gate of the second NMOS tube 13 is configured to receive a preset voltage, and the source of the second NMOS tube 13 is grounded. The drain of the second PMOS tube 17 is connected to the second preset power supply, the source of the second PMOS tube 17 is configured to be connected to the substrate of the power tube, and the source of the second PMOS tube 17 is also connected to the source of the third PMOS tube 19 and the source of the fourth PMOS tube 20. The gate of the second PMOS tube 17 is connected to the gate of the third PMOS tube 19, the gate of the fourth PMOS tube 20, one end of the second resistor 16 and the drain of the third NMOS tube 14. The other end of the second resistor 16 is connected to the first preset power supply. The gate of the third NMOS tube 14 is configured to receive a power comparison signal. The source of the third NMOS tube 14 is connected to the drain of the fourth NMOS tube 15, the gate of the fourth NMOS tube 15 is configured to receive a preset voltage, and the source of the fourth NMOS tube 15 is grounded. The drain of the third PMOS tube 19 is connected to the control end of the preset external PMOS tube. The drain of the fourth PMOS tube 20 is connected to the control end of the power tube. The source of the eighth PMOS tube 24 is connected to the first preset power supply, the gate of the eighth PMOS tube 24 is connected to the drain of the eighth PMOS tube 24 and the source of the ninth PMOS tube 25, the gate of the ninth PMOS tube 25 is connected to the drain of the ninth PMOS tube 25 and the source of the tenth PMOS tube 26, and the gate of the tenth PMOS tube 26 is connected to the drain of the tenth PMOS tube 26 and the drain of the third NMOS tube 14. In this way, when VCC is greater than VBAT, bat_vin_con is low, and bat_vin_con becomes high after passing through the inverter, so that the first NMOS tube is turned on.The voltage at point A can be clamped at a suitable potential through the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube so that the gate-source voltage of the first PMOS tube does not need to be too large. At this time, since the potential at point A becomes low, the first PMOS tube is turned on, and the voltage of the substrate of the power tube is equal to the first power supply voltage. At the same time, since bat_vin_con is low, the third NMOS tube is turned off, and the voltage at the B terminal is VCC, then the second PMOS tube, the third PMOS tube and the fourth PMOS tube are turned off. When VCC is less than VBAT, bat_vin_con is high, and bat_vin_con becomes low after passing through the inverter, so that the first NMOS tube is turned off, the voltage at point A is equal to the voltage of VCC, and the first PMOS tube is turned off. At the same time, since bat_vin_con is high, the third NMOS tube is turned on, the potential at point B becomes low, and the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube can clamp the voltage at point B at a suitable potential so that the gate-source voltage of the second PMOS tube does not need to be too large. Since the voltage at point B becomes low, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are turned on. After the second PMOS tube is turned on, the voltage of the substrate of the power tube is equal to the voltage of VBAT, completing the substrate switching. After the fourth PMOS tube is turned on, the GATE signal will be pulled high, and the GATE signal is connected to the gate of the power tube, which turns off the power tube. After the third PMOS tube is turned on, the con_up signal will be pulled high, and this signal is connected to the gate of the PMOS in the external module. After being pulled high, the PMOS in the external module is turned off, ensuring that the external module will not affect the power tube.

[0061] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A substrate switching circuit, characterized in that: include: A first switch circuit, wherein an input end of the first switch circuit is connected to a first preset power source; The output end of the first switch circuit is configured to be connected to the substrate of the power tube; a second switch circuit, wherein an input end of the second switch circuit is connected to a second preset power source; The output end of the second switch circuit is configured to be connected to the substrate of the power tube; a first control circuit, wherein a first end of the first control circuit is connected to a control end of the first switch circuit and an output end of the first switch circuit; a second end of the first control circuit is connected to a start signal supply end of the first switch circuit; the control end of the first control circuit is configured to receive an inverted power comparison signal; the power comparison signal is a result of comparing the first preset power supply with the second preset power supply; a second control circuit, wherein a first terminal of the second control circuit is connected to a control terminal of the second switch circuit; The second end of the second control circuit is connected to the start-up signal supply end of the second switch circuit; and the control end of the second control circuit is configured to receive the power comparison signal.

2. The substrate switching circuit according to claim 1, characterized in that: The first switch circuit comprises: A first controlled switch, wherein a first end of the first controlled switch is connected to the first preset power supply, a control end of the first controlled switch is connected to a first end of the first control circuit; and a second end of the first controlled switch is configured to be connected to a substrate of the power tube.

3. The substrate switching circuit according to claim 1, characterized in that: The second switch circuit comprises: A second controlled switch, wherein the second end of the second controlled switch is connected to the second preset power supply, the control end of the second controlled switch is connected to the first end of the second control circuit; and the first end of the second controlled switch is configured to be connected to the substrate of the power tube.

4. The substrate switching circuit according to claim 3, characterized in that: The second switch circuit further includes: a third controlled switch, wherein a first end of the third controlled switch is connected to a first end of the second controlled switch; a control end of the third controlled switch is connected to a control end of the second controlled switch; a second end of the third controlled switch is configured to be connected to a control end of a preset external PMOS tube; and the external PMOS tube is used to control the on and off of the power tube; a fourth controlled switch, wherein a first end of the fourth controlled switch is connected to a first end of the second controlled switch; a control end of the fourth controlled switch is connected to a control end of the second controlled switch; and a second end of the fourth controlled switch is configured to be connected to a control end of the power tube.

5. The substrate switching circuit according to claim 1, characterized in that: The first control circuit comprises: a fifth controlled switch, wherein the control end of the fifth controlled switch is configured to receive the inverted power comparison signal; and a second end of the fifth controlled switch is connected to the control end of the first switch circuit; a sixth controlled switch, wherein a control end of the sixth controlled switch is configured to receive a preset voltage; a second end of the sixth controlled switch is connected to a first end of the fifth controlled switch; and a first end of the sixth controlled switch is connected to a start signal supply end of the first switch circuit; A first resistor, one end of the first resistor is connected to the output end of the first switch circuit; the other end of the first resistor is connected to the second end of the fifth controlled switch.

6. The substrate switching circuit according to claim 1, characterized in that: The second control circuit comprises: a seventh controlled switch, wherein a control end of the seventh controlled switch is configured to receive the power comparison signal; and a second end of the seventh controlled switch is connected to a control end of the second switch circuit; an eighth controlled switch, wherein the control end of the eighth controlled switch is configured to receive a preset voltage; the second end of the eighth controlled switch is connected to the first end of the seventh controlled switch; and the first end of the eighth controlled switch is connected to the start signal supply end of the second switch circuit; A second resistor, one end of the second resistor is connected to the first preset power source; the other end of the second resistor is connected to the second end of the seventh controlled switch.

7. The substrate switching circuit according to any one of claims 1 to 5, characterized in that: The substrate switching circuit further includes: A first clamping circuit, one end of the first clamping circuit is connected to the substrate of the power tube, and the other end of the first clamping circuit is connected to the first control circuit.

8. The substrate switching circuit according to any one of claims 1 to 5, characterized in that: The substrate switching circuit further includes: A second clamping circuit, one end of the second clamping circuit is connected to the first preset power supply, and the other end of the second clamping circuit is connected to the second control circuit.

9. The substrate switching circuit according to any one of claims 1 to 5, characterized in that: The substrate switching circuit further includes: An inverting circuit, wherein the output end of the inverting circuit is connected to the control end of the first control circuit; and the input end of the inverting circuit is configured to receive the power supply comparison signal.

10. An electronic device, characterized in that: Comprising the substrate switching circuit according to any one of claims 1 to 9.

Images