Network-on-chip structure, processor and electronic equipment

Abstract

The utility model provides a network-on-chip structure, a processor and an electronic device. The network-on-chip structure comprises a plurality of bare chip structures; the bare core structure comprises a plurality of routers arranged in an array; a plurality of boundary routers are arranged in routers included in each bare core structure; the plurality of boundary routers are located on a target side edge of the bare core structure; the total number of the bearing routers on the target side edge is the same as the number of the boundary routers; any two bare core structures form a bare core group; for any bare core group, the boundary routers on the target side edge of one bare core structure correspond to the boundary routers on the target side edge of the other bare core structure in the bare core group in a one-to-one mode and are connected with the boundary routers on the target side edge of the other bare core structure in the bare core group. And the transmission direction is changed only once at most, so that the deadlock problem of data transmission of a cross-bare core structure is avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of computers, and in particular to an on-chip network structure, a processor and an electronic device. Background Art

[0002] On-chip network is a key technology of multi-processor architecture. It is the interconnection path and communication network inside the processor, responsible for message transmission, and is the basis for processor collaboration.

[0003] At present, the on-chip network includes multiple bare core structures, each of which is composed of multiple nodes arranged in an array. The nodes are processor cores, caches or other IP cores. Each node is associated with a router, and the nodes communicate through the router. When transmitting data between multiple bare core structures, an XY routing strategy can be used to reduce the probability of deadlock. The XY routing strategy means that data can only be transmitted between routers arranged in an array in the bare core structure in a horizontal and vertical transmission direction. When data is transmitted between any two routers in the bare core structure, a change in the transmission direction will occur at most once. When there is a knotted ring between the paths of multiple messages, the transmission of the message is blocked, and deadlock will occur. However, the XY routing strategy in the related art can only solve the deadlock problem during internal transmission of the bare core structure. For transmission between multiple bare core structures, there is still a high probability of deadlock. Utility Model Content

[0004] In view of the above problems, embodiments of the present utility model are proposed to provide a network-on-chip structure, a processor, and an electronic device that overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect, an embodiment of the utility model discloses a network-on-chip structure, the network-on-chip structure comprising:

[0006] A plurality of bare core structures; the bare core structure comprises a plurality of routers arranged in an array; each of the bare core structures comprises a plurality of border routers; the plurality of border routers are located on a target side of the bare core structure; the total number of routers carried on the target side is the same as the number of border routers; any two bare core structures constitute a bare core group;

[0007] For any die group, a border router on a target side of one die structure corresponds one-to-one to a border router on a target side of another die structure in the die group and they are connected to each other.

[0008] In a second aspect, an embodiment of the utility model discloses a processor, wherein the processor includes an on-chip network structure.

[0009] In a third aspect, an embodiment of the utility model further discloses an electronic device, comprising a processor.

[0010] In the embodiment of the utility model, multiple border routers can be set in the routers included in each bare core structure, and the multiple border routers are all on a target side of the bare core structure; the total number of routers carried on the target side is the same as the number of border routers. For any bare core group, the border router on the target side of one bare core structure corresponds to and is connected to the border router on the target side of another bare core structure in the bare core group. Under such a structural design, by deploying enough border routers on the target side of each bare core structure, the XY routing strategy is no longer limited to a single bare core structure, but is implemented based on the overall on-chip network structure, so that when data is transmitted between two bare core structures based on the XY routing strategy, there is only one change in the transmission direction at most, so that data transmission across bare core structures will not cause deadlock problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of a network-on-chip structure provided by an embodiment of the utility model;

[0012] Figure 2 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;

[0013] Figure 3 It is a schematic diagram for comparing transmission directions of on-chip networks provided by a related technology;

[0014] Figure 4 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;

[0015] Figure 5 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;

[0016] Figure 6 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;

[0017] Figure 7 It is a partial structural diagram of a network-on-chip structure provided by an embodiment of the utility model;

[0018] Figure 8 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;

[0019] Fig. 9 is a schematic diagram of a processor provided by an embodiment of the utility model;

[0020] Fig.10It is a schematic diagram of an electronic device provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0021] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0022] refer to Figure 1 , which shows a schematic diagram of an on-chip network structure provided by an embodiment of the utility model, including: multiple bare core structures 10; the bare core structure 10 includes a processor core (or other IP), and multiple array-arranged routers 11; each processor core is associated with a router; the router 11 included in each bare core structure 10 has multiple border routers 12; the multiple border routers 12 are all on a target side of the bare core structure 10; the total number of routers 11 carried on the target side is the same as the number of border routers 12; any two bare core structures 10 constitute a bare core group; for any bare core group, the border router 12 on the target side of one bare core structure 10 corresponds one-to-one to the border router 12 on the target side of another bare core structure 10 in the bare core group and is connected to each other.

[0023] In practical applications, although the multiple processor cores in a multi-core processor chip each execute their own code, data needs to be shared and synchronized between the processor cores. Therefore, the hardware structure of the multi-core processor must support efficient inter-core communication, and the performance of the on-chip communication structure will directly affect the performance of the processor.

[0024] Therefore, the Network on Chip (NoC) aims to solve the communication problem within the multi-core processor. The NoC is an integrated circuit on a communication subsystem based on a router network. The NoC is a packet switching network based on routers between systems on chip. The NoC technology draws on the interconnection network structure of parallel computers, integrating a large number of computing resources and an on-chip communication network connecting these resources on a single chip. Each processor core has an independent router and its private cache, and is connected together through an on-chip communication network. The processor cores use a message communication mechanism, and use routers and packet switching technology to replace the on-chip bus of related technologies to complete the communication task, thereby solving various bottleneck problems caused by bus interconnection in related technologies.

[0025] After determining the topology of the on-chip network, the routing algorithm can be used to determine the path that the message takes through the network to reach the destination. The goal of the routing algorithm is to evenly distribute traffic in the paths provided by the network topology, avoid hot spots, minimize contention, and improve network latency and throughput. While achieving these performance goals, design constraints must be observed to avoid critical paths that are too long and too large in area.

[0026] Among them, the bare core structure is also called a chiplet, which refers to a pre-manufactured chip (Die) with specific functions and can be combined and integrated. The bare core structure can divide the processor into multiple independent Dies, and then manufacture large chips through advanced packaging technology. This technology can reduce the manufacturing cost of large-scale chips, improve the reuse of a single Die, and reduce development costs. And when selecting or designing a routing algorithm, not only its impact on latency, power consumption, throughput and reliability must be considered, but also the network must be guaranteed to be deadlock-free.

[0027] Specifically, Figure 1 The figure shows a network-on-chip structure including two bare core structures 10, each bare core structure 10 includes a router 11 of 4×4 specification, and an XY routing strategy can be used to solve the deadlock problem for data transmission between the routers 11 included in each bare core structure 10. That is, the XY routing strategy avoids the occurrence of deadlock by limiting the transmission of data to be carried out along the longitudinal and transverse transmission directions.

[0028] For example, refer to Figure 2 , in a bare core structure 10, an XY routing strategy is implemented. Assuming that data is transmitted from router A to router B, there are two transmission paths: transmission path m1, first horizontal transmission and then vertical transmission; transmission path m2, first vertical transmission and then horizontal transmission. Regardless of the transmission path, the transmission direction will change (turn) at most once, thus avoiding the deadlock problem.

[0029] However, the XY routing strategy can only solve the deadlock problem during transmission within the bare core structure 10, and cannot avoid the deadlock problem for transmission between multiple bare core structures 10. The deadlock problem refers to the blocking of message transmission when there are knotted loops between the paths of multiple messages.

[0030] For example, refer to Figure 3 , data is transmitted between two bare core structures 10, and the XY routing strategy is executed. Assuming that data is exchanged between router C in one bare core structure 10 and router D in another bare core structure 10, the transmission path includes n1 and n2, which makes the data transmission produce a circular dependency, resulting in a deadlock problem, thereby blocking the data transmission.

[0031] In order to solve the above problems, in the embodiment of the present utility model, based on Figure 1 design, any two bare core structures 10 in all bare core structures 10 in the on-chip network can form a bare core group ( Figure 1 1 shows a bare core group), each bare core structure 10 includes a router 11 that may have multiple border routers 12, and the border router 12 is used to perform data transmission between bare core structures 10, that is, the routers in the bare core structure 10 except the border router 12 can only perform data transmission within the bare core structure 10, while the border router 12 can perform data transmission across the bare core structure 10. In addition, the multiple border routers 12 are all located on a target side of the bare core structure (the target side of the left bare core structure 10 is the right side, and the target side of the right bare core structure 10 is the left side); the total number of routers carried on the target side ( Figure 1 4) is the same as the number of border routers; any two bare core structures constitute a bare core group.

[0032] For any die group, a border router 12 on the target side of one die structure 10 corresponds one-to-one to a border router 12 on the target side of another die structure 10 in the die group and they are connected to each other.

[0033] Since the core idea of ​​the XY routing strategy is: in the process of transmitting data in the topology structure, at most one change in the transmission direction is allowed to occur to avoid deadlock, the embodiment of the utility model Figure 1 The design is to deploy enough border routers 12 on the target side so that the XY routing strategy is no longer limited to a single bare core structure, but is implemented based on the overall on-chip network structure. Based on this design, it can be ensured that when data is transmitted between two bare core structures 10 based on the XY routing strategy, there is at most one change in the transmission direction, so that data transmission across bare core structures will not cause deadlock problems.

[0034] For example, refer to Figure 4 For the communication between two bare core structures 10, assuming that router E in one bare core structure 10 sends data to router F in another bare core structure 10, the transmission paths include h1 and h2; assuming that router G in one bare core structure 10 sends data to router H in another bare core structure 10, the transmission paths include h3 and h4. It can be seen that no matter which transmission path, only one change of transmission direction occurs (from longitudinal to transverse or from transverse to longitudinal), making data transmission conform to the core idea of ​​XY routing strategy, thereby avoiding the occurrence of deadlock problem.

[0035] It should be noted that the number of routers included in each bare core structure may also be n×m, and n and m may be different, which is not limited in the embodiment of the present utility model.

[0036] Reference Figure 5 , which shows a network-on-chip structure including two bare core structures 10, each bare core structure 10 includes a router 11 of 4×8 specifications. If the target side of the border router 12 is set to the long side of the bare core structure 10, the number of border routers set on the target side of each bare core structure 10 is 8. For any bare core group, the 8 border routers 12 on the target side of one bare core structure 10 correspond to the 8 border routers 12 on the target side of another bare core structure 10 in the bare core group and are connected to each other. Therefore, the embodiment of the utility model deploys enough border routers 12 on the target side, so that the XY routing strategy is no longer limited to a single bare core structure, but is implemented based on the overall network-on-chip structure. Based on this design, it can be ensured that when data is transmitted between two bare core structures 10 based on the XY routing strategy, there is only one change in the transmission direction at most, so that the data transmission across the bare core structure will not cause deadlock problems.

[0037] Reference Figure 6 , which shows a network-on-chip structure including two bare die structures 10, each bare die structure 10 includes a router 11 of 8×4 specifications, and if the target side of the border router 12 is the short side of the bare die structure 10, the number of border routers set on the target side of each bare die structure 10 is 4. For any bare die group, the four border routers 12 on the target side of one bare die structure 10 correspond one-to-one to the four border routers 12 on the target side of another bare die structure 10 in the bare die group and are connected to each other.

[0038] In summary, the solution of the utility model can set multiple border routers in the routers included in each bare core structure, and the multiple border routers are all on a target side of the bare core structure; the total number of routers carried on the target side is the same as the number of border routers. For any bare core group, the border router on the target side of one bare core structure corresponds to and is interconnected with the border router on the target side of another bare core structure in the bare core group. Under such a structural design, by deploying enough border routers on the target side of each bare core structure, the XY routing strategy is no longer limited to a single bare core structure, but is implemented based on the overall on-chip network structure, so that when data is transmitted between two bare core structures based on the XY routing strategy, there is at most only one change in the transmission direction, so that data transmission across bare core structures will not cause deadlock problems.

[0039] Optional, see Figure 1 , Figure 5 and Figure 6, when each die structure 10 includes n×n routers 11, the number of edge routers 12 included in each die structure 10 is n; when each die structure 10 includes n×m routers 11, the number of edge routers 12 included in each die structure 10 is n or m. That is, when each die structure 10 includes n×m routers 11, if the edge router 12 is set on the target side with a length of n, the number of edge routers 12 included in each die structure 10 is n; if the edge router 12 is set on the target side with a length of m, the number of edge routers 12 included in each die structure 10 is m.

[0040] In the embodiment of the present utility model, the border router 12 can be arranged on any side of the bare core structure 10, such as Figure 1 The four border routers 12 are arranged on the left or right side of the bare core structure 10. Figure 5 The eight edge routers 12 are arranged on the long sides of the bare core structure 10. Figure 6 The four border routers 12 are arranged on the short sides of the bare core structure 10. Regardless of the structure, the border routers 12 all cover a target side of the bare core structure 10, thereby ensuring that when data is transmitted between two bare core structures 10 based on the XY routing strategy, there is at most only one change in the transmission direction, so that the data transmission across the bare core structure will not cause deadlock problems.

[0041] Optional, see Figure 1 , Figure 5 and Figure 6 The bare core structure 10 includes routers 11 arranged in an array to form a grid structure. The routers 11 are located at the corner points of the grid in the grid structure, so that the data forwarded by the routers 11 are transmitted horizontally or vertically in the grid structure.

[0042] Specifically, refer to Figure 7 , which shows a partial structural diagram of an on-chip network structure, which shows a grid structure 50 formed by four routers 11 in the on-chip network structure. The grid structure 50 has four corner points 51, and a corresponding router 11 is arranged at each corner point.

[0043] In an embodiment of the utility model, the array-arranged routers 11 included in the bare core structure 10 can be formed into a grid structure, and each router 11 can be placed at a corner point of the grid in the grid structure, so that the horizontal transmission direction and the vertical transmission direction are realized in the bare core structure 10, that is, the transmission direction between the routers in the bare core structure is only horizontal and vertical, which provides a structural basis for the implementation of the XY routing strategy.

[0044] Optional, see Figure 1 , Figure 5and Figure 6 , the border router 12 is located at the periphery of the bare core structure 10 .

[0045] In the embodiment of the present utility model, preferably, the border router 12 can be located at the periphery of the bare core structure 10, so as to reduce the communication distance between the border routers.

[0046] Optional, see Figure 1 , Figure 5 and Figure 6 , each bare core structure 10 includes the same number of edge routers 12.

[0047] In the embodiment of the utility model, each bare core structure 10 includes the same number of border routers 12, so that when multiple bare core structures 10 are interacting with each other, the border router on the target side of one bare core structure can correspond one-to-one with the border router on the target side of another bare core structure and be connected to each other, thereby ensuring that when data is transmitted between two bare core structures 10 based on the XY routing strategy, there is at most only one change in transmission direction, so that data transmission across bare core structures will not cause deadlock problems.

[0048] Optional, see Figure 1 , Figure 5 and Figure 6 , the number of bare core structures 10 is an even number.

[0049] In the embodiment of the utility model, preferably, the number of bare core structures is an even number, so that the on-chip network structure can form a symmetrical structure that is easy to process and produce. Figure 1 , Figure 5 and Figure 6 The number of bare core structures 10 is 2. Figure 8 , also shows the case where the number of bare core structures 10 is 4, each bare core structure is of 4×4 specifications, it can be seen that, Figure 8 In the on-chip network structure, there is a pair of oppositely disposed target sides between any two bare core structures 10, and the boundary routers 12 included in the oppositely disposed target sides correspond to each other one by one and are connected to each other.

[0050] Optional, see Figure 1 , Figure 5 and Figure 6 For any one die group, a target side edge of one die structure 10 is arranged opposite to a target side edge of another die structure 10 in the die group.

[0051] In the embodiment of the utility model, the target sides of any two bare core structures 10 are arranged relative to each other, so that the communication distance between the boundary routers 12 respectively included in the relatively arranged target sides can be shortened, and the processing difficulty when connecting the boundary routers respectively included in the target sides is reduced.

[0052] In addition, for the on-chip network structure of the embodiment of the utility model, only a single virtual channel is used, that is, the physical channel reflected by the connection between the routers in the on-chip network structure is the virtual channel. The virtual channel is a virtual channel divided from the physical channel by time-division multiplexing. It has an independent buffer and does not interfere with each other, but shares a physical link. From the perspective of the data packet, there are multiple virtual channels between the two routers, but the actual physical links are the same. One of the purposes of the utility model is to solve the deadlock problem by designing the position of the border router under the premise of using only a single virtual channel. A single virtual channel can reduce power consumption, reduce area, and reduce design complexity. By constraining the number, position, and connection relationship of the border routers, the purpose of deadlock-free under a single channel is achieved.

[0053] Reference Fig. 9 , which shows a schematic diagram of a processor provided by an embodiment of the utility model, and the processor includes the on-chip network structure provided by the above embodiment.

[0054] Reference Fig.10 , which shows a schematic diagram of an electronic device provided by an embodiment of the utility model, the electronic device may include Fig. 9 processor.

[0055] In summary, the solution of the utility model can set multiple border routers in the routers included in each bare core structure, and the multiple border routers are all on a target side of the bare core structure; the total number of routers carried on the target side is the same as the number of border routers. For any bare core group, the border router on the target side of one bare core structure corresponds to and is interconnected with the border router on the target side of another bare core structure in the bare core group. Under such a structural design, by deploying enough border routers on the target side of each bare core structure, the XY routing strategy is no longer limited to a single bare core structure, but is implemented based on the overall on-chip network structure, so that when data is transmitted between two bare core structures based on the XY routing strategy, there is at most only one change in the transmission direction, so that data transmission across bare core structures will not cause deadlock problems.

[0056] Those skilled in the art will readily come up with other embodiments of the present invention after considering the specification and practicing the utility model disclosed herein. The present invention is intended to cover any variation, use or adaptation of the present invention, which follows the general principles of the present invention and includes common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

[0057] It should be understood that the present invention is not limited to the precise structure described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A network-on-chip structure, characterized in that: The network-on-chip structure comprises: A plurality of bare core structures; the bare core structure comprises a plurality of routers arranged in an array; each of the bare core structures comprises a plurality of border routers; the plurality of border routers are located on a target side of the bare core structure; the total number of routers carried on the target side is the same as the number of border routers; any two bare core structures constitute a bare core group; For any die group, a border router on a target side of one die structure corresponds one-to-one to a border router on a target side of another die structure in the die group and they are connected to each other.

2. The network-on-chip structure according to claim 1, characterized in that: In the case where each of the bare core structures includes n×n routers; the number of edge routers included in each of the bare core structures is n; In the case that each of the bare core structures includes n×m routers, the number of edge routers included in each of the bare core structures is n or m.

3. The network-on-chip structure according to claim 1, characterized in that: The border router is located at a peripheral position of the bare core structure.

4. The network-on-chip structure according to claim 1, characterized in that: The bare core structure includes routers arranged in an array to form a grid structure. The routers are located at corner points of the grid in the grid structure, so that data forwarded by the routers are transmitted horizontally or vertically in the grid structure.

5. The network-on-chip structure according to claim 1, characterized in that: Each of the bare core structures includes the same number of border routers.

6. The network-on-chip structure according to claim 1, characterized in that: The number of the bare core structures is an even number.

7. The network-on-chip structure according to claim 1, characterized in that: For any one die group, a target side edge of one die structure is arranged opposite to a target side edge of another die structure in the die group.

8. A processor, characterized in that: The processor comprises: a network-on-chip structure as described in any one of claims 1-7.

9. An electronic device, characterized in that: The processor according to claim 8 is included.

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