Integrated circuit transistor device

Abstract

The utility model relates to an integrated circuit transistor device. An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region in the semiconductor substrate providing a source, and a second doped region buried in the semiconductor substrate providing a body. A trench extends into the semiconductor substrate and through the first and second doped regions. An insulating polysilicon gate region within the trench surrounds the polycrystalline oxide region. The polysilicon gate region is formed by a first gate lobe and a second gate lobe on opposite sides of the polycrystalline oxide region and a gate bridge on the polycrystalline oxide region. In the first region, the gate bridge has a first thickness, and in the second region, the gate bridge has a second thickness (greater than the first thickness). At the second region, a gate contact is provided at each trench to partially extend into a second thickness of the gate bridge. Technical solutions according to the present disclosure advantageously support providing devices with reduced pitches.

Description

Technical Field

[0001] Embodiments herein relate generally to metal oxide semiconductor field effect transistor (MOSFET) devices, and more particularly to a gate contact structure for a trench power MOSFET having a split gate configuration including a pair of polysilicon gate lobes laterally spaced apart by a polycrystalline oxide region and electrically coupled by a polysilicon gate bridge. Background Art

[0002] Figure 1 A cross section of a power metal oxide semiconductor field effect transistor (MOSFET) device 50 is shown. In this example, the MOSFET is an n-channel (nMOS) type device formed in and on a semiconductor substrate 52 doped with an n-type dopant, which provides the drain of the transistor 50. The substrate 52 has a front side 54 and a back side 56. A plurality of trenches 58 extend along a depth from the front side 54 into the substrate 52. The trenches 58 extend longitudinally (i.e., lengthwise) parallel to each other along a direction perpendicular to the cross section (i.e., into and out of the illustrated page) and form strips (this type of transistor device is generally referred to in the art as a strip FET type transistor).

[0003] A region 64 doped with a p-type dopant is buried in the substrate 52 at a depth offset from (i.e., below) the front side 54 and is positioned on opposite sides of each trench 58 extending parallel to the front side 54. The doped region 64 forms the body (channel) region of the transistor, with the trench 58 passing completely through the doped body region 64 and into the substrate 52 below the doped body region 64. A region 66 doped with an n-type dopant is provided on the front side 54 of the substrate 52 and is positioned on opposite sides of each trench 58 extending parallel to the front side 54 and in contact with the top of the doped body region 64. The doped region 66 forms the source of the transistor, with the trench 58 passing completely through the doped source region 66 and, as mentioned above, extending completely through the doped body region 64 further into the substrate 52 below the doped body region 64.

[0004] The sidewalls and bottom of each trench 58 are lined with a first (thick) insulating layer 60a. For example, the insulating layer 60a may include a thick oxide layer. The trench 58 is then filled with a first polysilicon material 62a, wherein the insulating layer 60a insulates the first polysilicon material 62a from the substrate 52. The polysilicon material 62a is a heavily n-type doped polysilicon material (e.g., phosphorus doped, with a doping concentration of 5x10 20 at / cm 3 During the process for fabricating transistor 50, an upper portion of insulating layer 60a (which will be adjacent to both doped body region 64 and doped region 66) is removed from trench 58 to expose a corresponding upper portion 61 of polysilicon material 62a (see Figure 2A ). The exposed upper portion 61 of the polysilicon material 62a is then converted (e.g., using a thermal oxidation process) to form a polycrystalline oxide region 68 that is vertically aligned with the remaining (lower) portion 63 of the polysilicon material 62a in the trench 58 (see Figure 2B ). This remaining lower portion 63 of polysilicon material 62a forms the field plate electrode of transistor 50 (also referred to as the polysilicon source region, as it is typically electrically shorted to source region 66 - this electrical connection is not explicitly shown in the drawings). The sidewalls and bottom of the upper portion of the oxide liner of each trench 58 are then lined with a second (thin) insulating layer 60b (see Figure 2C ). For example, the insulating layer 60b may include a thermally grown thin oxide layer. The upper portion of each trench 58 is then filled with a second polysilicon material 62b, wherein the insulating layer 60b insulates the second polysilicon material 62b from the substrate 52 (including regions 64 and 66). The second polysilicon material 62b forms the gate (also referred to as a polysilicon gate region) of the transistor 50, and includes a first (e.g., left) gate convex corner 621 and a second (e.g., right) gate convex corner 622 extending on opposite sides of the polycrystalline oxide region 68. The first gate convex corner and the second gate convex corner are electrically coupled by a gate bridge portion 623 extending above the polycrystalline oxide region 68. The insulating layer 60b forms a gate oxide layer.

[0005] A stack of layers 70 is formed over the upper surface of the substrate. The stack 70 includes an undoped oxide (e.g., tetraethyl orthosilicate (TEOS)) layer 72 and a glass (e.g., borophosphosilicate glass (BPSG)) layer 74. The stack 70 may also include additional insulating layers and / or barrier layers if desired. For example, a thin silicon nitride layer (not explicitly shown) may be provided between the TEOS layer 72 and the upper surface 54 of the substrate 52.

[0006] Reference Figure 1 , source metal contacts 80 extend through the layers of stack 70, positioned between the locations of adjacent trenches 58 to make electrical contact with doped source regions 66. Each source metal contact 80 extends into the substrate along the depth to pass through doped source region 66 and partially into doped body region 64 (thereby providing a body contact for transistor 50 bound to the source). A source metal layer 82 extends over both stack 70 and source metal contacts 80 to provide electrical connections to and between all source metal contacts 80. The layers of stack 70 insulate both source metal layer 82 and source metal contacts 80 from the polysilicon gate (second polysilicon region 62b).

[0007] Now refer to Figure 1, gate metal contacts 86 extend through the layers of stack 70 and are positioned to align with the locations of trenches 58 to form electrical contact with the second polysilicon region 62b in each trench 58 (e.g., by contacting at the location of bridge portion 623). It is noted that gate metal contacts 86 preferably extend at least partially into the filled trench along the depth, for example, into at least the upper portion of bridge portion 623 (and may extend completely through the bridge portion). Gate metal layer 88 extends over both stack 70 and gate metal contacts 86 to provide electrical connections to and between all gate metal contacts 86. The layers of stack 70 insulate both gate metal layer 88 and gate metal contacts 86 from the source metal contacts and source regions. Polycrystalline oxide region 68 insulates polysilicon source region 62a from gate metal contacts 86.

[0008] Figure 1 The cross sections on the left and right sides of FIG. 8 are actually offset longitudinally from each other in a direction perpendicular to the cross sections (ie, into and out of the illustrated page). In this configuration, an insulating separation is provided between the source metal layer 82 and the gate metal layer 88.

[0009] Drain metal layer 84 extends over back side 56 of substrate 52 to provide a metal connection to the drain.

[0010] Transistor 50 may alternatively be a pMOS type transistor, in which both substrate 52 and doped source region 56 are p-type doped and body region 54 is n-type doped.

[0011] Figure 3A Shows the corresponding Figure 1 A scanning electron micrograph (SEM) cross-sectional image of a single cell of transistor 50 is shown on the left.

[0012] In the polycrystalline oxide region 68 (see Figure 2B During the formation of the polycrystalline silicon material 62a, there is lateral and vertical material expansion as the polycrystalline silicon material 62a is converted to the polycrystalline oxide region 68. This expansion causes tension that can create voids (or seams or cavities) within the polycrystalline oxide material. The presence and location of such voids in the polycrystalline oxide region 68 is unpredictable. Figure 3B A scanning electron micrograph (SEM) cross-sectional image focused on the region where the groove 58 is located is shown to illustrate by way of example the presence of such voids (see also Figure 2B Depending on the width of trench 58 and the size of the polysilicon gate formed by convex corners 621, 622 and bridge 623, the void in polycrystalline oxide region 68 may extend close to the inner surface of the polysilicon gate (see Figure 2C), and this may have an impact on the formation of gate contact 86 and, as will be discussed below, increase the risk of short circuit and / or current leakage to the source through polysilicon source region 62a.

[0013] The process for forming the gate contact 86 uses a mask having a mask opening aligned with the center of the trench 58. The etching performed using the mask produces a gate opening that extends through the stack 70 and at least partially into (if not completely through) the bridge 623 of the second polysilicon region 62b that forms the polysilicon gate. The etching can include multiple discrete etching steps, including a first etching to remove the layers of the stack 70 and a second etching extending to a desired depth in the bridge 623. The size of the mask opening and the corresponding gate opening is typically designed to be approximately (more preferably less than) one-half the size (width) of the trench 58, and is generally preferably aligned with the center of the trench. A barrier layer 92 formed of a titanium-titanium nitride (Ti-TiN) material is then conformally deposited into the etched gate opening, and the gate opening is then filled with a plug made of a conductive material (such as, for example, tungsten) to form the gate contact 86. Figure 3C A scanning electron micrograph (SEM) cross-sectional image is shown focused on the gate contact 86 and illustrates that the gate opening has completely passed through the gate bridge 623 to reach the poly oxide region 68 .

[0014] Control over the depth of the second etch is difficult to ensure, and the possible presence and location of voids in the poly-oxide region 68 is difficult to predict. There is therefore a non-negligible risk that the second etch will completely pass through the bridge 623, where the gate opening partially extends into the poly-oxide region 68 to reach the void. Furthermore, the etched opening may extend at least partially around the poly-oxide region 68. The conformally deposited Ti-TiN barrier layer may not be able to adequately cover this location because of the topological difficulties presented by the possible void in combination with the gate opening, and thus the conductive material for the plug deposited in the gate opening may present a leakage path or short circuit between the poly-Si gate and the poly-Si source provided by the field plate (which is electrically connected to the source region as mentioned above).

[0015] U.S. Patent Publication No. 2022 / 0320332 (incorporated herein by reference) presents a technical solution to solve the aforementioned problems in power MOSFET devices and provides a better solution for making electrical contact with a split gate configuration including a pair of polysilicon gate lobes that are laterally separated by polysilicon regions and electrically coupled by a polysilicon gate bridge.

[0016] Now refer to Figure 4 , Figure 4A lateral cross-section of a power metal oxide semiconductor field effect transistor (MOSFET) device 110 is shown in accordance with the teachings of U.S. Patent Publication No. 2022 / 0320332. In this example, the MOSFET is an n-channel (nMOS) type device formed in and on a semiconductor substrate 112 doped with an n-type dopant, which provides a drain of the transistor 110. The substrate 112 has a front side 114 and a back side 116. A plurality of trenches 118 extend from the front side 114 along a depth into the substrate 112. The trenches 118 extend longitudinally parallel to each other for a desired length along a direction perpendicular to the cross-section (i.e., into and out of the illustrated page), and form strips (this type of transistor device is generally referred to in the art as a strip FET type transistor).

[0017] Regions 124 doped with p-type dopants are buried in the substrate 112 at a depth offset from (i.e., below) the front side 114 and are positioned to extend laterally parallel to the front side 114 on opposite sides of each trench 118. The doped regions 124 form the body (channel) region of the transistor, with the trenches 118 passing completely through the doped body regions 124 and into the substrate 112 below the doped body regions 124. Surface implant regions 126 doped with n-type dopants are provided on the front side 114 of the substrate 112 and are positioned to extend parallel to the front side 114 on opposite sides of each trench 118 and in contact with the tops of the doped body regions 124. The doped regions 126 form the sources of the transistor, with the trenches 118 passing completely through the doped source regions 126 and, as mentioned above, extending completely through the doped body regions 124 further into the substrate 112 below the doped body regions 124.

[0018] The sidewalls and bottom of each trench 118 are lined with a first insulating layer 120a. For example, the insulating layer 120a may include a thick oxide layer. The trench 118 is then filled with a first polysilicon material 122a, wherein the insulating layer 120a insulates the first polysilicon material 122a from the substrate 112. The first polysilicon material 122a is a heavily n-type doped polysilicon material (e.g., phosphorus doped, with a doping concentration of 5×10 20 at / cm 3 ). Also refer to FIG. 2A to FIG. 2CDuring the process of manufacturing transistor 110, an upper portion of insulating layer 120a (which will be adjacent to both doped body region 124 and doped region 126) is removed from trench 118 to expose a corresponding upper portion of first polysilicon material 122a. This exposed upper portion of first polysilicon material 122a is then converted (e.g., using a thermal oxidation process) to form a polycrystalline oxide region 128, which is vertically aligned with the remaining (lower) portion of first polysilicon material 122a in trench 118. This remaining lower portion of first polysilicon material 122a forms a field plate electrode (also referred to as a polysilicon source region because it is typically electrically shorted to source region 126 - this electrical connection is not explicitly shown in the drawings) of transistor 110. The sidewalls and bottom of the upper portion of each trench 118 are then lined with a second insulating layer 120b. For example, insulating layer 120b may include a thermally grown oxide layer. The upper portion of each trench 118 is then filled with a second polysilicon material 122b, wherein an insulating layer 120b insulates the second polysilicon material 122b from the substrate 112 (including regions 124 and 126). The second polysilicon material 122b forms the gate (also referred to as a polysilicon gate region) of the transistor 110, and includes a first (e.g., left) gate lobes 621 and a second (e.g., right) gate lobes 622 extending longitudinally in the trench on opposite sides of the polycrystalline oxide region 128. The first gate lobes and the second gate lobes are connected by a gate bridge portion 623 extending laterally above the polycrystalline oxide region 128. The insulating layer 120b forms a gate oxide layer.

[0019] A layer stack 130 is formed over the upper surface of the substrate. The stack 130 includes an undoped oxide (e.g., tetraethyl orthosilicate (TEOS)) layer 132 and a glass (e.g., borophosphosilicate glass (BPSG)) layer 134. The stack 130 may also include additional insulating layers and / or barrier layers if desired. For example, a thin silicon nitride layer (not explicitly shown) may be provided between the TEOS layer 132 and the upper surface 114 of the substrate 112.

[0020] Reference Figure 4 , source metal contacts 140 extend through the layers of stack 130, positioned between the locations of adjacent trenches 118 to make electrical contact with doped source regions 126. Each source metal contact 140 extends along the depth into the substrate to pass through doped source regions 136 and partially into doped body regions 134 (thereby providing body contact for transistors 110 tied to the source). A source metal layer 142 extends over both stack 130 and source metal contacts 140 to provide electrical connections to and between all source metal contacts 140. The layers of stack 130 insulate both source metal layer 142 and source metal contacts 140 from the polysilicon gate (second polysilicon region 122b).

[0021] Now refer to Figure 4 1 , the gate metal contact of each polysilicon gate is formed by a pair of contacts 861 and 862, wherein each contact 861, 862 extends through the layers of the stack 130, and is positioned vertically aligned with the location of the corresponding convex corner 621, 622 (respectively) of the polysilicon gate to make electrical contact with the corresponding convex corner of the second polysilicon region 122b in each trench 118. In a preferred embodiment, each gate metal contact 861, 862 extends at least partially along the depth into the upper portion of the corresponding convex corner 621, 622 on either side of the bridge 623. The gate metal layer 148 extends over both the stack 130 and the gate metal contacts 861, 862 to provide electrical connections to and between all the gate metal contacts 861, 862. The layers of the stack 130 insulate the gate metal layer 148 and the gate metal contacts 861, 862 from the source metal contacts and source regions. It is noted that a portion of the stack is used to laterally insulate contact 861 from contact 862 at the level of a layer within the stack.

[0022] In practice, Figure 4 The left and right cross sections of are actually offset longitudinally from each other in a direction perpendicular to the cross sections (ie, into and out of the illustrated page). In this configuration, an insulating separation is provided between the source metal layer 142 and the gate metal layer 148.

[0023] A drain metal layer 144 extends over the back side 116 of the substrate 112 to provide a metal connection to the drain.

[0024] The transistor 110 may alternatively be a pMOS type transistor, in which both the substrate 112 and the doped source region 126 are p-type doped and the body region 124 is n-type doped.

[0025] Figure 5A and Figure 5B is a plan view (i.e., looking down toward the front surface of the substrate) of the layout for comparing transistors 50 and 110, with particular focus showing the relative positions of contact 86 and contact pairs 861 and 862. The dashed lines indicate the centerline of each longitudinally extending trench, and the dash-dotted lines indicate the approximate location of the longitudinal center of each convex corner of the polysilicon gate. Figure 5A roughly corresponds to Figure 1 The implementation shown on the right side, Figure 5B roughly corresponds to Figure 4 The implementation shown on the right. Figure 5B Only one pair of contacts 861 and 862 per trench is shown in FIG, but it is understood that this is merely an example and more than one pair of contacts per trench may be used if desired.

[0026] Utilizing a pair of contacts 861 and 862 arranged side by side Figure 4 The gate contact structure shown addresses concerns about problems that may arise with the polycrystalline oxide region 148 that may include voids. The combined size of a pair of contacts 861 and 862 is preferably substantially equal to Figure 1 The size of the gate contacts 86 shown will therefore provide substantially the same performance in terms of gate resistance. Separating each gate contact into two parts (contacts 861 and 862) and vertically aligning each part with a corresponding salient corner 621, 622 of the polysilicon gate avoids polysilicon gate contact with the central part of the trench (i.e., at the location of the gate bridge region), thereby minimizing the risk of the etch used to form the contact opening reaching the void location.

[0027] In this Figure 4 In embodiments, each contact 861 , 862 may have a length dimension (in the longitudinal direction) between 0.1 μm and 10 μm and a width dimension (in the lateral direction, perpendicular to the length dimension) between 0.1 μm and 1 μm.

[0028] It should be noted that in Figure 4 In the illustrated embodiment, in the case of a lateral side-by-side arrangement of a pair of contacts 861, 862, a cross section at a given position passes longitudinally through the two contacts 861, 862 along the length of the groove. The manufacture of a device having such an embodiment requires that the gate mask include a very thin resist portion that is aligned with the spacing between adjacent contacts at the given position. This very thin resist portion may peel off during manufacture and adversely affect the accuracy of the etching operation that forms each pair of gate contact openings. For example, a deformed opening for each gate contact in the gate contact may occur, or a merged opening (merger) that merges two separate openings of a pair of contacts side by side into one large opening may occur. The solution to this concern is to design the gate mask so that the individual mask openings used to produce the contacts 861, 862 are longitudinally offset from each other in a direction perpendicular to the cross section (i.e., into and out of the illustrated page).

[0029] The transistor 110' structure resulting from this arrangement of mask openings is as follows Figure 6 shown. Figure 6 The same reference numerals in the Figure 4 The same or similar parts. Figure 6 The left side corresponds to Figure 4 on the left side. Figure 6 The middle and right portions of illustra tively illustrate the longitudinal offset gate contacts 861 and 862 for a given trench, which is caused by the corresponding longitudinal offset of the mask opening. Figure 6The middle portion of shows a cross section at a location where a mask opening for forming a first gate contact 861 has been utilized to make electrical contact with a corresponding first (left side) lobe 621 of the polysilicon gate. Figure 6 The right portion of shows a cross section at a location where a mask opening for forming a second gate contact 862 has been utilized to make electrical contact with a corresponding second (right) lobed corner 622 of the polysilicon gate. Although the respective gate openings are longitudinally offset, it is noted that each gate contact of the polysilicon gate within the trench is still formed by a pair of contacts 861 and 862.

[0030] In this Figure 6 In an embodiment, each contact 861, 862 may have a length dimension (in the longitudinal direction) between 0.1 μm and 10 μm and a width dimension (in the transverse direction perpendicular to the length dimension) between 0.1 μm and 1 μm. Figure 6 The longitudinal offset of the contacts 861, 862 in each individual contact can be made to have a ratio of Figure 4 The corresponding contacts of the embodiments have a wider width, where a side-by-side arrangement may impose constraints on the contact width.

[0031] Fig. 7A A scanning electron micrograph (SEM) cross-sectional image of a single cell of transistor 110' is shown, corresponding to Figure 6 and focuses on the gate contact 861 of the convex corner 621 for the polysilicon gate.

[0032] Figure 7B A scanning electron micrograph (SEM) cross-sectional image of a single cell of transistor 110' is shown, corresponding to Figure 6 , and focuses on the gate contact 862 of the salient corner 622 for the polysilicon gate.

[0033] Fig. 8A and Figure 8B is a plan view (i.e., looking down toward the front surface of the substrate) for comparing the layouts of transistors 110 and 110', with particular focus showing the relative positions of contact pairs 861 and 862. The dashed lines indicate the centerline of each longitudinally extending trench, and the dash-dotted lines indicate the approximate location of the center of each lobes of the polysilicon gate. It is noted that the longitudinal center of each contact 861, 862 is located between the longitudinal center of the corresponding gate lobes and the longitudinal center of the trench. This ensures that the placement of the contacts does not risk bridging across the gate oxide and shorting the polysilicon gate to the doped source region. Fig. 8A roughly corresponds to Figure 4 (as well as Figure 5B ) is shown on the right side, and Figure 8B roughly corresponds to Figure 6 The embodiment shown in the middle and right side. Although only one pair of contacts 861 and 862 per groove is Fig. 8A and Figure 8B , it will be appreciated that this is merely an example and more than one pair of contacts per trench may be used if desired. Figure 8B It is noted that the longitudinal offset of a pair of contacts 861 and 862 of a given trench is such that no cross section of the trench in a plane perpendicular to the longitudinal direction of the trench passes through both the first gate contact and the second gate contact. This is achieved by providing a sufficient longitudinal offset distance D between the end of the first gate contact and the adjacent end of the second gate contact in the longitudinal direction of the trench.

[0034] and Figure 4 and Figure 6 The solution is difficult to implement in conjunction with transistors having a reduced pitch or transistors designed for lower voltage levels. The reason for this is that the reduced pitch with a smaller trench opening presents a smaller area at the gate lobes, and as the device scales, it becomes increasingly difficult to fit the off-center contacts 861, 862 into the gate lobes 621, 622, respectively.

[0035] Therefore, there is a need in the art to provide a further improved gate contact and method of manufacturing the same for use in conjunction with a trench power MOSFET having a split gate structure, the split gate structure comprising a pair of polysilicon gate lobes electrically coupled by a polycrystalline oxide. Utility Model Content

[0036] The purpose of the present disclosure is to provide an integrated circuit transistor device to at least partially solve the above-mentioned problems existing in the prior art.

[0037] An aspect of the present disclosure provides an integrated circuit transistor device, comprising: a semiconductor substrate providing a drain; a first doped region in the semiconductor substrate providing a source; a second doped region buried in the semiconductor substrate below the first doped region and providing a body; a trench extending into the semiconductor substrate and passing through the first doped region and the second doped region; a converted region within the trench; and a gate region within the trench, the gate region comprising: a first gate lobes on a first side of the converted region, a second gate lobes on a second side of the converted region opposite to the first side, and a gate bridge extending over the converted region; wherein, at the first region of the semiconductor substrate, the converted region is recessed within the trench to a first level, and the first gate lobes and the second gate lobes extend within the trench to a first depth; wherein, at the second region of the semiconductor substrate, the converted region is recessed within the trench to a second level, and the first gate lobes and the second gate lobes extend within the trench to a second depth; and wherein the second level is greater in depth than the first level, and the second depth is greater than the first depth.

[0038] According to one or more embodiments, the gate bridge has a first thickness in the first region and a second thickness in the second region, and the second thickness is greater than the first thickness.

[0039] According to one or more embodiments, the integrated circuit transistor device further includes a source region within the trench, wherein the source region is longitudinally aligned with the switched region.

[0040] In accordance with one or more embodiments, wherein the converted region is an oxidized portion of the source region.

[0041] According to one or more embodiments, the integrated circuit transistor device further includes: an insulating layer stack covering the transistor gate electrode, the trench and the semiconductor substrate; an opening at the second region, the opening aligned with the trench and extending through the insulating layer stack and partially extending into the gate bridge; and a gate contact in the opening.

[0042] According to one or more embodiments, the integrated circuit transistor device further includes: an insulating layer stack covering the transistor gate electrode, the trench and the semiconductor substrate; an opening at the first region, extending through the insulating layer stack, through the first doped region and partially extending into the second doped region; and a source contact in the opening.

[0043] Another aspect of the present disclosure provides an integrated circuit transistor device, comprising: a semiconductor substrate, providing a drain; a first doped region in the semiconductor substrate, providing a source; a second doped region buried in the semiconductor substrate below the first doped region and providing a body; a trench, extending into the semiconductor substrate and passing through the first doped region and the second doped region; a converted region within the trench; a gate region within the trench, the gate region comprising: a first gate convex corner on a first side of the converted region, a second gate convex corner on a second side of the converted region opposite to the first side, and a gate bridge extending over the converted region; wherein, at the first region of the semiconductor substrate, the gate bridge has a first thickness; wherein, at the second region of the semiconductor substrate, the gate bridge has a second thickness greater than the first thickness; a stack of insulating layers covering the transistor gate electrode, the trench and the semiconductor substrate; an opening at the second region of the semiconductor substrate, the opening being aligned with the trench and extending through the stack of insulating layers and partially extending into the second thickness of the gate bridge; and a gate contact in the opening.

[0044] According to one or more embodiments, the integrated circuit transistor device further includes a source region within the trench, wherein the source region is longitudinally aligned with the switched region.

[0045] In accordance with one or more embodiments, wherein the converted region is an oxidized portion of the source region.

[0046] The technical solution according to the present disclosure advantageously supports providing devices with reduced pitch. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0048] Figure 1 is a cross-sectional view of a power metal oxide semiconductor field effect transistor (MOSFET) device;

[0049] Figure 2A - Figure 2C Shows Figure 1 The manufacturing process steps of the power MOSFET device;

[0050] Figure 3A - Figure 3C yes Figure 1 Scanning electron microscopy image of a cross section of a power MOSFET device;

[0051] Figure 4 is a cross-sectional view of a power MOSFET device;

[0052] Figure 5A and Figure 5B They are shown respectively Figure 1 and 4The gate contact layout structure of the power MOSFET device;

[0053] Figure 6 is a cross-sectional view of a power MOSFET device;

[0054] Fig. 7A - Figure 7B yes Figure 6 Scanning electron microscopy image of a cross section of a power MOSFET device;

[0055] Fig. 8A and 8B They are shown respectively Figure 4 and Figure 6 The gate contact layout structure of the power MOSFET device;

[0056] Fig. 9 is a cross-sectional view of a power MOSFET device;

[0057] FIG. 10A-1 to FIG. 10G-2 show Fig. 9 The manufacturing process steps of the power MOSFET device; and

[0058] Fig.11 Shows Fig. 9 Gate and source contact layout for a power MOSFET device. DETAILED DESCRIPTION

[0059] Reference now Fig. 9 , which shows a cross-section of a power metal oxide semiconductor field effect transistor (MOSFET) device 210. In this example, the MOSFET is an n-channel (nMOS) type device formed in and on a semiconductor substrate 212 doped with an n-type dopant that provides a drain of the transistor 210. The substrate 212 has a front side 214 and a back side 216. A plurality of trenches 218 extend from the front side 214 into the substrate 212 in a depth direction. The trenches 218 extend longitudinally in a direction perpendicular to the cross-section (i.e., the direction into and out of the illustrated page) with a desired length parallel to each other and form strips (this type of transistor device is generally referred to in the art as a strip FET type transistor).

[0060] A region 224 doped with a p-type dopant is buried in the substrate 212 at a depth offset from (i.e., below) the front side 214 and is positioned to extend laterally parallel to the front side 214 on opposite sides of each trench 218. The doped region 224 forms the body (channel) region of the transistor, with the trench 218 extending completely through the doped body region 224 and into the substrate 212 below the doped body region 224. A surface implant region 226 doped with an n-type dopant is provided at the front side 214 of the substrate 212 and is positioned to extend parallel to the front side 214 on opposite sides of each trench 218 and contact the top of the doped body region 224. The doped region 226 forms the source of the transistor, with the trench 218 extending completely through the doped source region 226 and, as described above, further extending completely through the doped body region 224 into the substrate 212 below the doped body region 224.

[0061] The sidewalls and bottom of each trench 218 are lined with a first insulating layer 220a. For example, the insulating layer 220a may include a thick oxide layer. The trench 218 is then filled with a first polysilicon material 222a, which insulates the first polysilicon material 222a from the substrate 212. The first polysilicon material 222a is a heavily n-type doped polysilicon material (e.g., a doping concentration of 5×10 20 at / cm 3Phosphorus). During the manufacture of transistor 210, a region 301 of the upper surface of substrate 212 is covered by mask 300 (FIG. 10A-1). However, the mask includes an opening at a region 302 where a transistor gate contact is to be formed (FIG. 10A-2). A first selective recessing of an upper portion 361 of first polysilicon material 222a at region 302 is then performed by selectively removing a first portion of first polysilicon material 222a at region 302 to produce an opening 303 (see FIGS. 10B-1 and 10B-2). This recessing operation can be achieved, for example, using dry polysilicon selective etching. Mask 300 is then removed (see FIGS. 10C-1 and 10C-2). A second selective recessing of the upper portion 361 of the first polysilicon material 222a at regions 301 and 302 is then performed by selectively removing a second portion of the first polysilicon material 222a at region 301 and further selectively removing a third portion of the first polysilicon material 222a at region 302 to produce openings 304a and 304b (see FIGS. 10D-1 and 10D-2 ), wherein the opening 304b is an extension of the depth of the opening 303. The recessing operation can be achieved, for example, using dry polysilicon selective etching. As a result of the selective recessing operation, the first polysilicon material 222a at region 301 is recessed to a first level, while the first polysilicon material 222a at region 302 is recessed to a second level (with a depth greater than the first level). An upper portion of insulating layer 220a (which will be adjacent to both doped body region 124 and doped region 126) is removed from trench 218 to expose a corresponding upper portion 361a of first polysilicon material 222a in region 301 and a corresponding upper portion 361b of first polysilicon material 222a in region 302 (see FIGS. 10E-1 and 10E-2). Removal of the upper portion of insulating layer 220a may be accomplished, for example, using a wet buffered oxide etch (BOE) that selectively removes the oxide material of insulating layer 220a while leaving first polysilicon material 222a and substrate 212 in place. It should be noted that due to the difference in depths of the openings 304a, 304b resulting from the recessing of the first polysilicon material 222a in regions 301 and 302, respectively, there will be corresponding differences in the depths of the openings 305a and 305b in regions 301 and 302 resulting from the wet BOE, respectively (where opening 305a has a first depth and opening 305b has a second depth greater than the first depth). The exposed upper portions 361a, 361b of the first polysilicon material 222a are then converted (e.g., using a thermal oxidation process) to form polycrystalline oxide regions 228a, 228b that are vertically aligned with the remaining (lower) portions of the first polycrystalline silicon material 222a in the trench 218 (see FIGS. 10F-1 and 10F-2). For reasons previously mentioned herein, this thermal oxidation process may, in some cases, produce voids in the polycrystalline oxide regions 228a, 228b.It should be noted that the upper surfaces of the polycrystalline oxide regions 228a, 228b are recessed to different levels in the first and second regions 301, 302, respectively. The remaining lower portion of the first polysilicon material 222a forms the field plate electrode of the transistor 210 (also referred to as the polysilicon source region because it is typically electrically shorted to the source region 226 - this electrical connection is not explicitly shown in the figure). The sidewalls and bottom of the upper portion of each trench 218 are then lined with a second insulating layer 220b. For example, the insulating layer 220b can include a thermally grown oxide layer. The upper portion of each trench 218 is then filled with a second polysilicon material 222b, which insulates the second polysilicon material 222b from the substrate 212 (including regions 224 and 226). See Figures 10G-1 and 10G-2. The second polysilicon material 222b forms the gate of the transistor 210 (referred to as the polysilicon gate region) and includes a first (e.g., left) gate lobes 321 and a second (e.g., right) gate lobes 322 extending longitudinally in the trenches on opposite sides of the polycrystalline oxide regions 228a, 228b. The first and second gate lobes are connected by a gate bridge portion 323 extending laterally on the polycrystalline oxide regions 228a, 228b. It should be noted that the vertical thickness of the bridge portion 323 is different in the regions 301 and 302. Specifically, the bridge portion 323 in the region 302 where the transistor gate contact is to be formed is thicker than the bridge portion 323 in the region 301. The reasons and advantages of this will be apparent from the discussion of the gate contact provided later below. It will also be noted that the first and second gate lobes 321, 322 extend to different depths in the first and second regions 301, 302, respectively (the depth in the region 302 is greater than the depth in the region 301). The insulating layer 220b forms a gate oxide layer.

[0062] A stack 230 is formed over the upper surface of the substrate. The stack 230 includes an undoped oxide (e.g., tetraethyl orthosilicate (TEOS)) layer 232 and a glass (e.g., borophosphosilicate glass (BPSG)) layer 234. The stack 230 may also include additional insulating and / or barrier layers if desired. For example, a thin silicon nitride layer (not explicitly shown) may be provided between the TEOS layer 232 and the upper surface 214 of the substrate 212.

[0063] See also Fig. 9, source metal contacts 240 extend through the layers of stack 230, positioned between locations adjacent trench 218, to make electrical contact with doped source regions 226. Each source metal contact 240 extends in the depth direction into the substrate to pass through doped source regions 236 and partially into doped body regions 234 (thus providing a body contact for transistor 210 connected to the source). A source metal layer 242 extends over both stack 230 and source metal contacts 240 to provide electrical connection between all source metal contacts 240. The layers of stack 230 insulate both source metal layer 242 and source metal contacts 240 from the polysilicon gate (second polysilicon region 222b).

[0064] Reference now Fig. 9 2, the gate metal contact 250 of each polysilicon gate extends through the layers of the stack 230, positioned to be vertically aligned with the location of the trench 218 to electrically contact the bridge portion 323 in the region 302. Each gate metal contact 250 extends only partially into the upper portion of the (thicker) bridge portion 323 at the region 302 in the depth direction. The gate metal layer 248 extends over both the stack 230 and the gate metal contacts 250 to provide electrical connections to and between all the gate metal contacts 250. The layers of the stack 230 insulate both the gate metal layer 248 and the gate metal contacts 250 from the source metal contacts and source regions.

[0065] The process for forming the gate contact 250 utilizes a mask having a mask opening aligned with the center of the trench 218 in the region 302. The etching performed using this mask produces a gate opening extending through the stack 230 and partially into the bridge 323 of the second polysilicon region 222b forming the polysilicon gate. The etching may include multiple discrete etching steps, including a first etching to remove the layers of the stack 230, and a second etching to extend into the bridge 323 to a desired depth (taking advantage of the extra thickness available for the bridge 323 in the region 302). The size of the mask opening and the corresponding gate opening is typically designed to be approximately half the size (width) of the trench 218, and more preferably less than half the size (width) of the trench 218, and is generally preferably aligned with the center of the trench. A barrier layer 292 formed of a titanium-titanium nitride (Ti-TiN) material is then conformally deposited into the etched gate opening, and the gate opening is then filled with a plug 294 made of a conductive material (e.g., tungsten) to form the gate contact 250. It should be noted that the gate opening for inserting the gate contact 250 has a depth that partially extends into the gate bridge 323 without reaching the polycrystalline oxide region 228 or the included voids. The double-ended arrow in FIG10G-2 shows the safe offset distance generated in the region 302 due to the extension depth of the first polysilicon material 222a that is recessed in the region 302 compared to the region 301. See the process steps shown in FIG10B-2, FIG10C-2, FIG10D-2, and FIG10E-2.

[0066] It should be noted that due to the increased thickness of bridge portion 323 in region 302, there is a significantly reduced risk that the depth of the contact opening etched to extend partially into bridge portion 323 will reach polycrystalline oxide region 228b. In addition, the etched opening will have a more uniform topology (compared to Figure 3C As compared to the non-uniform shape of the contact opening shown in FIG. 1 ). As a result, the conformally deposited Ti—TiN barrier layer will completely cover the location and provide the necessary insulating presence and thickness. In addition, there is a correspondingly reduced risk that the conductive material deposited in the gate opening for the contact 250 will present a leakage path or short circuit between the polysilicon gate and the polysilicon source provided by the field plate. In addition, because the contact 250 can be aligned with the center of the trench, rather than as Figure 4 and Figure 6 As the center of the trench is offset as in the example above, this structure supports providing devices with reduced pitch.

[0067] In fact, Fig. 9 The cross sections on the left and right sides of FIG. 2 are actually offset longitudinally from each other in a direction perpendicular to the cross sections (ie, into and out of the illustrated page). In this configuration, an insulating separation is provided between the source metal layer 242 and the gate metal layer 248 .

[0068] A drain metal layer 244 extends over the back side 216 of the substrate 212 to provide a metal connection to the drain.

[0069] The transistor 210 may also be a pMOS transistor, in which the substrate 212 and the doped source regions 226 are both p-type doped, and the body region 224 is n-type doped.

[0070] Fig.11 is a plan view showing the layout of transistor 210 with a particular focus (ie, looking down toward the front surface of the substrate), showing the relative positions of contacts 240 and 250. Dashed lines indicate the centerline of each longitudinally extending trench. Dashed lines 310 indicate Fig. 9 The approximate location of the cross section on the left. The dashed line 312 indicates all Figure 10A-1 - Figure 10G-2 The general location of the cross section is shown with a suffix "-1" associated with area 301. Dashed line 314 indicates Fig. 9 The general location of the cross section on the right, and all the suffixes "-2" associated with area 302 Figure 10A-1 - Figure 10G-2 General location of cross section shown.

[0071] In one embodiment, a method includes: forming a trench in a semiconductor substrate; lining the sidewalls and bottom of the trench with a first insulating layer; filling the trench with a first polysilicon material; forming a mask covering the trench at a first region of the semiconductor substrate, the mask including a first opening above the trench at a second region of the semiconductor substrate; etching using the first opening to selectively remove a first portion of the first polysilicon material at the second region of the semiconductor substrate; removing the mask; etching to selectively remove the second portion of the first polysilicon material at the first region of the semiconductor substrate and to remove a third portion of the first polysilicon material at the second region of the semiconductor substrate; etching to selectively remove an upper portion of the first insulating layer in the trench to a first depth at the first region of the semiconductor substrate and to a second depth at the second region of the semiconductor substrate, the second depth being greater than the first depth, to expose an upper portion of the first polysilicon material in an upper portion of the trench; converting the exposed upper portion of the first polysilicon material in the trench to a polycrystalline oxide material; lining the sidewalls and bottom of the upper portion of the trench with a second insulating layer; and filling the upper portion of the trench with a second polysilicon material.

[0072] In one embodiment, a method includes: forming a trench in a semiconductor substrate; lining the sidewalls and bottom of the trench with a first insulating layer; filling the trench with a first polysilicon material; selectively recessing the first polysilicon material in the trench to a first level at a first region of the semiconductor substrate; selectively recessing the first polysilicon material in the trench to a second level at a second region of the semiconductor substrate, the second level having a depth greater than the first level; selectively recessing an upper portion of the first insulating layer in the trench to a first depth in the first region and a second depth in the second region so as to expose an upper portion of the recessed first polysilicon material in an upper portion of the trench; converting the exposed upper portion of the first polysilicon material in the trench into a polycrystalline oxide material; lining the sidewalls and bottom of the upper portion of the trench with a second insulating layer; and filling the upper portion of the trench with a second polysilicon material.

[0073] In one embodiment, an integrated circuit transistor device includes: a semiconductor substrate providing a drain; a first doped region in the semiconductor substrate providing a source; a second doped region buried in the semiconductor substrate below the first doped region and providing a body; a trench extending into the semiconductor substrate and passing through the first and second doped regions; a polycrystalline oxide region within the trench; and a polycrystalline silicon gate region within the trench, the polycrystalline silicon gate region including: a first gate lobes on a first side of the polycrystalline oxide region, a second gate lobes on a second side of the polycrystalline oxide region opposite to the first side, and a gate bridge extending over the polycrystalline oxide region; wherein, at the first region of the semiconductor substrate, the polycrystalline oxide region is recessed to a first level within the trench, and the first and second gate lobes extend to a first depth within the trench; wherein, at the second region of the semiconductor substrate, the polycrystalline oxide region is recessed to a second level within the trench, and the first and second gate lobes extend to a second depth within the trench; and wherein the second level is greater in depth than the first level, and the second depth is greater than the first depth.

[0074] In one embodiment, an integrated circuit transistor device includes: a semiconductor substrate providing a drain; a first doped region in the semiconductor substrate providing a source; a second doped region buried in the semiconductor substrate below the first doped region and providing a body; a trench extending into the semiconductor substrate and passing through the first and second doped regions; a polycrystalline oxide region within the trench; a polycrystalline silicon gate region within the trench, the polycrystalline silicon gate region including: a first gate lobes on a first side of the polycrystalline oxide region, a second gate lobes on a second side of the polycrystalline oxide region opposite the first side, and a gate bridge extending over the polycrystalline oxide region; wherein, in the first region of the semiconductor substrate, the gate bridge has a first thickness; wherein, in the second region of the semiconductor substrate, the gate bridge has a second thickness greater than the first thickness; a stack of insulating layers covering the transistor gate electrode, the trench, and the semiconductor substrate; an opening at the second region of the semiconductor substrate, the opening aligned with the trench and extending through the insulating layer stack and partially into the second thickness of the gate bridge; and a gate contact in the opening.

[0075] One aspect of the present disclosure provides a method, comprising: forming a trench in a semiconductor substrate; lining the sidewalls and bottom of the trench with a first insulating layer; filling the trench with a first polysilicon material; forming a mask covering the trench at a first region of the semiconductor substrate, the mask comprising a first opening above the trench at a second region of the semiconductor substrate; etching to selectively remove a first portion of the first polysilicon material at the second region of the semiconductor substrate using the first opening; removing the mask; etching to selectively remove the second portion of the first polysilicon material at the first region of the semiconductor substrate and to selectively remove a third portion of the first polysilicon material at the second region of the semiconductor substrate; etching to selectively remove an upper portion of the first insulating layer in the trench to a first depth at the first region of the semiconductor substrate and to a second depth at the second region of the semiconductor substrate to expose an upper portion of the first polysilicon material in an upper portion of the trench, the second depth being greater than the first depth; converting the exposed upper portion of the first polysilicon material in the trench into a polycrystalline oxide material; lining the sidewalls and bottom of the upper portion of the trench with a second insulating layer; and filling the upper portion of the trench with a second polysilicon material.

[0076] According to one or more embodiments, wherein the remaining portion of the first polysilicon material in the trench forms a transistor field plate electrode, and wherein the second polysilicon material forms a transistor gate electrode.

[0077] According to one or more embodiments, wherein the semiconductor substrate is doped with a first conductivity type, the method further includes: implanting a first doped region doped with the first conductivity type into the upper surface of the semiconductor substrate; burying a second doped region below the first doped region, the second doped region being doped with a second conductivity type opposite to the first conductivity type; and wherein the trench extends completely in depth through both the first doped region and the second doped region.

[0078] According to one or more embodiments, the semiconductor substrate forms a transistor drain, the first doped region forms a transistor source, and the second doped region forms a transistor body.

[0079] According to one or more embodiments, the method further includes: forming an insulating layer stack covering the transistor gate electrode, the trench and the semiconductor substrate; forming a second opening at the first region, the second opening extending through the insulating layer stack, through the first doped region and partially extending into the second doped region; and forming a source contact in the second opening.

[0080] According to one or more embodiments, the second polysilicon material forming the transistor gate electrode includes a first gate lobe on one side of the polycrystalline oxide material, a second gate lobe on an opposite side of the polycrystalline oxide material, and a gate bridge extending over the polycrystalline oxide material.

[0081] According to one or more embodiments, the method further includes: forming an insulating layer stack covering the transistor gate electrode, the trench and the semiconductor substrate; forming a third opening at the second region, the third opening being aligned with the trench and extending through the insulating layer stack and partially extending into the gate bridge; and forming a gate contact in the third opening.

[0082] Another aspect of the present disclosure provides a method, including: forming a trench in a semiconductor substrate; lining the sidewalls and bottom of the trench with a first insulating layer; filling the trench with a first polysilicon material; selectively recessing the first polysilicon material in the trench to a first level at a first region of the semiconductor substrate; selectively recessing the first polysilicon material in the trench to a second level at a second region of the semiconductor substrate, the depth of the second level being greater than the first level; selectively recessing an upper portion of the first insulating layer in the trench to a first depth in the first region and a second depth in the second region so as to expose an upper portion of the recessed first polysilicon material in the upper portion of the trench; converting the exposed upper portion of the first polysilicon material in the trench into a polycrystalline oxide material; lining the sidewalls and bottom of the upper portion of the trench with a second insulating layer; and filling the upper portion of the trench with a second polysilicon material.

[0083] According to one or more embodiments, wherein the remaining portion of the first polysilicon material in the trench forms a transistor field plate electrode, and wherein the second polysilicon material forms a transistor gate electrode.

[0084] According to one or more embodiments, the second polysilicon material forming the transistor gate electrode includes a first gate lobe on one side of the polycrystalline oxide material, a second gate lobe on an opposite side of the polycrystalline oxide material, and a gate bridge extending over the polycrystalline oxide material.

[0085] According to one or more embodiments, the method further includes: forming an insulating layer stack covering the transistor gate electrode, the trench and the semiconductor substrate; forming an opening at the second region aligned with the trench and extending through the insulating layer stack and partially extending into the gate bridge; and forming a gate contact in the opening.

[0086] For the discussion here, it should be noted that the term "longitudinal" refers to a first direction extending, for example, along the length of the trench, and the term "lateral" refers to a second direction extending, for example, along the width of the trench. The longitudinal and lateral directions extend perpendicular to each other and parallel to the upper surface of the semiconductor substrate.

[0087] Although the present invention has been described and illustrated in detail in the drawings and the foregoing description, such description and illustration are considered to be illustrative or exemplary rather than restrictive; the present invention is not limited to the disclosed embodiments. By studying the drawings, the disclosure and the appended claims, those skilled in the art can understand and implement other variations of the disclosed embodiments when practicing the claimed invention.

Claims

1. An integrated circuit transistor device, characterized in that: include: A semiconductor substrate providing a drain; The first doped region in the semiconductor substrate provides a source; a second doped region buried in the semiconductor substrate below the first doped region and providing a body; a trench extending into the semiconductor substrate and passing through the first doped region and the second doped region; through a conversion region, within said groove; as well as a gate region within the trench, the gate region comprising: a first gate lobe on a first side of the converted region, a second gate lobe on a second side of the converted region opposite the first side, and a gate bridge extending over the converted region; wherein, at a first region of the semiconductor substrate, the converted region is recessed to a first level within the trench, and the first gate lobes and the second gate lobes extend to a first depth within the trench; wherein, at a second region of the semiconductor substrate, the converted region is recessed to a second level within the trench, and the first gate lobes and the second gate lobes extend to a second depth within the trench; and Wherein the second level is greater in depth than the first level, and the second depth is greater than the first depth.

2. The integrated circuit transistor device according to claim 1, characterized in that: The gate bridge has a first thickness in the first region and a second thickness in the second region, the second thickness being greater than the first thickness.

3. The integrated circuit transistor device according to claim 1, characterized in that: Also included is a source region within the trench, wherein the source region is longitudinally aligned with the switched region.

4. The integrated circuit transistor device according to claim 3, characterized in that: The converted region is an oxidized portion of the source region.

5. The integrated circuit transistor device according to claim 1, characterized in that: Further including: an insulating layer stack covering the transistor gate electrode, the trench and the semiconductor substrate; an opening at the second region, the opening aligned with the trench and extending through the insulating layer stack and partially into the gate bridge; as well as A gate contact is provided in the opening.

6. The integrated circuit transistor device according to claim 1, characterized in that: Further including: an insulating layer stack covering the transistor gate electrode, the trench and the semiconductor substrate; an opening at the first region extending through the insulating layer stack, through the first doped region and partially into the second doped region; as well as A source contact is provided in the opening.

7. An integrated circuit transistor device, characterized in that: include: A semiconductor substrate providing a drain; The first doped region in the semiconductor substrate provides a source; a second doped region buried in the semiconductor substrate below the first doped region and providing a body; a trench extending into the semiconductor substrate and passing through the first doped region and the second doped region; a converted region within the groove; a gate region within the trench, the gate region comprising: a first gate lobe on a first side of the converted region, a second gate lobe on a second side of the converted region opposite the first side, and a gate bridge extending over the converted region; Wherein, at a first region of the semiconductor substrate, the gate bridge has a first thickness; Wherein, at a second region of the semiconductor substrate, the gate bridge has a second thickness greater than the first thickness; a stack of insulating layers covering the transistor gate electrode, the trench and the semiconductor substrate; an opening at the second region of the semiconductor substrate, the opening being aligned with the trench and extending through the insulating layer stack and partially into the second thickness of the gate bridge; and A gate contact is provided in the opening.

8. The integrated circuit transistor device according to claim 7, characterized in that: Also included is a source region within the trench, wherein the source region is longitudinally aligned with the switched region.

9. The integrated circuit transistor device according to claim 8, characterized in that: The converted region is an oxidized portion of the source region.

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