VDMOS capable of improving avalanche tolerance

Abstract

The utility model relates to the technical field of MOS semiconductors, and discloses a VDMOS capable of improving avalanche tolerance, which comprises a VDMOS device formed by a plurality of VDMOS cells arranged in parallel, and each VDMOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer. The semiconductor epitaxial layer comprises a sinking layer, a diffusion layer, a P well layer, an N well layer and a drift layer, and the N well layer is isolated from the diffusion layer and the drift layer through the P well layer; the N-well layer comprises a highly-doped N-well layer and a lowly-doped N-well layer; the P-well layer comprises a first low-doped P-well layer, a first high-doped P-well layer and a second high-doped P-well layer. According to the VDMOS device, phosphorus ions with different concentrations are injected into the diffusion layer between the grid electrode and the drain electrode to form the multi-level drift layer, and the multi-level drift layer can effectively reduce the possibility that a semiconductor epitaxial layer is punctured by peak voltage under the condition that the existence of a grid electric field is not intervened, so that the avalanche tolerance of the VDMOS device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, in particular to a VDMOS with improved avalanche tolerance. Background Art

[0002] VDMOS (Vertical Double-diffused MOS) device is a vertical double-diffused MOS (metal oxide semiconductor) device, usually referred to as VDMOSFET (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor). This device is known for its structural characteristics and is mainly used in power electronics applications. Its main features include: vertical structure, double diffusion, metal gate and oxide insulation layer.

[0003] The existing patent discloses a VDMOS device structure with enhanced avalanche tolerance and its manufacturing method (publication number CN108281486A), which belongs to the field of power semiconductor device technology, including: a drain region; an epitaxial layer located on the drain region; a first adjustment region and a second adjustment region located in the epitaxial layer; a first well region located in the first adjustment region and a source region embedded in the first well region; a second well region located in the second adjustment region; a lateral channel located in the first well region; a gate oxide layer located on the epitaxial layer, a polysilicon layer located on the gate oxide layer; a dielectric layer located on the polysilicon layer; a contact hole region located on the first well region and the second well region; and a metal electrode region located above the contact hole. In the technology disclosed in the patent, when the gate is connected to the gate voltage and encounters a peak voltage state, the charge of the drain is rapidly and massively gathered toward the gate under the action of the gate electric field, and it is very easy to break down the oxide layer that acts as a partition. Summary of the invention

[0004] The main technical problem solved by the utility model is to provide a VDMOS with improved avalanche tolerance, thereby solving the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the utility model, more specifically, a VDMOS with improved avalanche tolerance includes a VDMOS device composed of a plurality of VDMOS cells arranged in parallel, wherein the VDMOS cell includes a drain, a source, a gate, and a semiconductor epitaxial layer;

[0006] The semiconductor epitaxial layer includes a sink layer, a diffusion layer, a P-well layer, an N-well layer and a drift layer, wherein the N-well layer is isolated from the diffusion layer and the drift layer by the P-well layer;

[0007] The N-well layer includes a high-doped N-well layer and a low-doped N-well layer;

[0008] The P-well layer includes a low-doped P-well layer 1, a highly-doped P-well layer 1 and a highly-doped P-well layer 2;

[0009] The drift layer includes a low drift layer 1, a low drift layer 2, a low drift layer 3 and a high drift layer;

[0010] When the gate is connected to a gate voltage, charges inside the low-doped P-well layer gather near the gate to form a charge channel, and the N-well layer and the drift layer are connected through the charge channel.

[0011] Furthermore, an oxide layer is deposited between the surface of the gate and the source and the semiconductor epitaxial layer.

[0012] Furthermore, when a gate voltage is applied to the gate, a depletion layer of a JFET region is formed inside the diffusion layer, and the JFET region is located below the drift layer.

[0013] Furthermore, the cross-sectional profile of the low-doped P-well layer 1 is in an 'L' shape, wherein an N-well layer is formed inside the profile of the low-doped P-well layer 1 by ion implantation.

[0014] Furthermore, the high-doped N-well layer and the low-doped N-well layer divide the N-well layer into two equal layers, wherein the low-doped N-well layer suppresses the charges in the N-well layer from drifting toward the edge of the P-well layer.

[0015] Furthermore, the highly doped P-well layers 2 of adjacent VDMOS cells are integrated with each other, wherein the highly doped P-well layer 2 inhibits the charges of the N-well layer from diffusing to the N-well layer of the adjacent VDMOS cell.

[0016] Furthermore, the cross-sectional profile thicknesses of the low drift layer 1, the low drift layer 2, the low drift layer 3 and the high drift layer decrease step by step.

[0017] Furthermore, the doping concentration of the low drift layer 1 is 6 to 8×10 16 mol / cm 3 ;

[0018] The doping concentration of the diffusion layer and the low drift layer 2 is 2-4×10 16 mol / cm 3 ;

[0019] The doping concentrations of the low-doped N-well layer and the low drift layer 3 are both 6 to 8×10 17 mol / cm 3 ;

[0020] The doping concentrations of the highly doped N-well layer and the high drift layer are both 2 to 4×10 18 mol / cm 3 .

[0021] Furthermore, the doping concentration of the low-doped P-well layer 1 is 7-8.6×10 16 mol / cm 3 ;

[0022] The doping concentration of the highly doped P well layer 1 is 2 to 6.3×10 18 mol / cm 3 ;

[0023] The doping concentration of the highly doped P well layer 2 is 5 to 8×10 18 mol / cm 3 .

[0024] Furthermore, only the highly doped N-well layer in the N-well layer is ohmically shorted to the source electrode, and only the highly doped P-well layer 2 in the P-well layer is ohmically shorted to the source electrode.

[0025] The beneficial effects of the VDMOS with improved avalanche tolerance of the utility model are as follows:

[0026] 1. The utility model forms a multi-level drift layer by injecting phosphorus ions of different concentrations into the diffusion layer between the gate and the drain. The multi-level drift layer can effectively reduce the possibility of peak voltage breakdown of the semiconductor epitaxial layer without interfering with the gate electric field, thereby improving the avalanche tolerance of the VDMOS device.

[0027] 2. The utility model injects more phosphorus ions into the drift layer and near the gate position to ensure that the doping concentration of the formed high drift layer region is the same as that of the highly doped N-well layer, which can effectively reduce the on-resistance of the charge channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The utility model is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0029] Figure 1 A schematic diagram of VDMOS cells in the present invention arranged in parallel;

[0030] Figure 2 It is a schematic diagram of the structure of a single VDMOS cell in the utility model;

[0031] Figure 3 It is a partial schematic diagram of a single VDMOS cell in the utility model;

[0032] Figure 4 This is a schematic diagram of the VDMOS device structure of the utility model.

[0033] In the figure: 1. drain; 2. source; 3. gate; 4. oxide layer; 5. substrate layer; 6. diffusion layer; 7. highly doped N-well layer; 8. low doped N-well layer; 9. low doped P-well layer 1; 10. highly doped P-well layer 1; 11. highly doped P-well layer 2; 12. low drift layer 1; 13. low drift layer 2; 14. low drift layer 3; 15. high drift layer; 16. charge channel. DETAILED DESCRIPTION

[0034] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0035] like Figure 1-4 As shown, according to one aspect of the utility model, a VDMOS with improved avalanche tolerance is provided, including a VDMOS device composed of a plurality of VDMOS cells arranged in parallel, the VDMOS cell including a drain 1, a source 2, a gate 3 and a semiconductor epitaxial layer, the semiconductor epitaxial layer including a sink layer 5, a diffusion layer 6, a P-well layer, an N-well layer and a drift layer, wherein the N-well layer is isolated from the diffusion layer 6 and the drift layer by the P-well layer (such as Figure 2 , 3 As shown), when the gate 3 is connected to the gate voltage state, the internal charges of the low-doped P-well layer 9 gather near the gate 3 to form a charge channel 16, and the N-well layer and the drift layer are connected through the charge channel 16. At this time, the diffusion layer 6 and the N-well layer are in a connected state, that is, the drain 1 and the source 2 are connected.

[0036] In this embodiment, the N-well layer includes a high-doped N-well layer 7 and a low-doped N-well layer 8 , and the P-well layer includes a low-doped P-well layer 1 9 , a high-doped P-well layer 1 10 and a high-doped P-well layer 2 11 .

[0037] The doping concentration of the low-doped P-well layer 9 is 7 to 8.6×10 16 mol / cm 3 .

[0038] The doping concentration of the highly doped P well layer 10 is 2 to 6.3×10 18 mol / cm 3 .

[0039] The doping concentration of the highly doped P well layer 11 is 5 to 8×10 18 mol / cm 3 .

[0040] Since the doping concentration of the highly doped N-well layer 7 and the high drift layer 15 is the same, the on-resistance between the highly doped N-well layer 7 and the high drift layer 15 can be greatly reduced after the charge channel 16 connects the highly doped N-well layer 7 and the high drift layer 15. In addition, the P-well layer is designed as a multi-level design, which can prevent the gate electric field from causing excessive interference to the internal charge of the P-well layer.

[0041] In this embodiment, the drift layer includes a low drift layer 12, a low drift layer 2 13, a low drift layer 3 14 and a high drift layer 15 (eg, Figure 2 As shown in FIG. 1 , the cross-sectional profile thicknesses of the low drift layer 12 , the low drift layer 13 , the low drift layer 14 , and the high drift layer 15 decrease step by step.

[0042] The doping concentration of the low drift layer 12 is 6 to 8×10 16 mol / cm 3 .

[0043] The doping concentration of the diffusion layer 6 and the low drift layer 13 is 2-4×10 16 mol / cm 3 .

[0044] The doping concentrations of the low-doped N-well layer 8 and the low drift layer 14 are both 6 to 8×10 17 mol / cm 3 .

[0045] The doping concentration of the high-doped N-well layer 7 and the high drift layer 15 is 2 to 4×10 18 mol / cm 3 .

[0046] This method forms a multi-level drift layer by injecting phosphorus ions of different concentrations into the diffusion layer between the gate and the drain. The multi-level drift layer can effectively reduce the possibility of peak voltage breakdown of the semiconductor epitaxial layer without interfering with the gate electric field.

[0047] In this embodiment, an oxide layer 4 is deposited between the surface of the gate 3 and the source 2 and the semiconductor epitaxial layer. When the gate 3 is subjected to a gate voltage, a depletion layer of a JFET region is formed inside the diffusion layer 6 thereof, and the JFET region is located below the drift layer (e.g. Figure 4 The characteristics of the JFET region depend on the gate electric field. By controlling the gate voltage, the conductivity of the JFET region can be adjusted. The JFET region plays a key role in the MOS structure and affects the overall performance and function of the device.

[0048] In this embodiment, the cross-sectional profile of the low-doped P-well layer 9 is in an 'L' shape, wherein an N-well layer is formed inside the profile of the low-doped P-well layer 9 by ion implantation, and the high-doped N-well layer 7 and the low-doped N-well layer 8 divide the N-well layer into two equal layers, the low-doped N-well layer 8 suppresses the drift of the charge of the N-well layer toward the edge of the P-well layer, and the low-doped P-well layer 9 is designed into an 'L' shape to avoid contact between the N-well layer and the diffusion layer 6, and also to increase the concentration of the charge of the P-well layer near the oxide layer 4 to form a charge channel 16.

[0049] In this embodiment, the highly doped P-well layers 11 of adjacent VDMOS cells are integrated, wherein the highly doped P-well layer 11 inhibits the diffusion of charges in the N-well layer to the N-well layer of the adjacent VDMOS cell, and only the highly doped N-well layer 7 in the N-well layer is short-circuited with the source 2 in ohms, and only the highly doped P-well layer 11 in the P-well layer is short-circuited with the source 2 in ohms. The highly doped P-well layer 11 can isolate the phenomenon of charge mutual diffusion between the N-well layers of adjacent VDMOS cells.

[0050] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.

Claims

1. A VDMOS having improved avalanche withstand capability, characterized in that: A VDMOS device is provided which is composed of a plurality of VDMOS cells arranged in parallel with each other, wherein the VDMOS cell comprises a drain (1), a source (2), a gate (3) and a semiconductor epitaxial layer; The semiconductor epitaxial layer comprises a sink layer (5), a diffusion layer (6), a P-well layer, an N-well layer and a drift layer, wherein the N-well layer is isolated from the diffusion layer (6) and the drift layer by the P-well layer; The N-well layer comprises a high-doped N-well layer (7) and a low-doped N-well layer (8); The P-well layer comprises a low-doped P-well layer 1 (9), a high-doped P-well layer 1 (10) and a high-doped P-well layer 2 (11); The drift layer comprises a low drift layer 1 (12), a low drift layer 2 (13), a low drift layer 3 (14) and a high drift layer (15); When the gate (3) is connected to a gate voltage, charges inside the low-doped P-well layer (9) are gathered near the gate (3) to form a charge channel (16), and the N-well layer and the drift layer are connected via the charge channel (16).

2. The VDMOS with improved avalanche withstand capability according to claim 1, characterized in that: An oxide layer (4) is deposited between the surface of the gate (3), the source (2) and the semiconductor epitaxial layer.

3. The VDMOS with improved avalanche withstand capability according to claim 1, characterized in that: When the gate (3) is in a state where a gate voltage is applied, a depletion layer of a JFET region is formed inside the diffusion layer (6), and the JFET region is located below the drift layer.

4. The VDMOS with improved avalanche withstand capability according to claim 1, characterized in that: The cross-sectional profile of the low-doped P-well layer 1 (9) is in an 'L' shape, wherein an N-well layer is formed inside the profile of the low-doped P-well layer 1 (9) by ion implantation.

5. The VDMOS with improved avalanche withstand capability according to claim 4, characterized in that: The high-doped N-well layer (7) and the low-doped N-well layer (8) divide the N-well layer into two equal layers, the upper and lower layers, wherein the low-doped N-well layer (8) suppresses the drift of charges in the N-well layer toward the edge of the P-well layer.

6. The VDMOS with improved avalanche withstand capability according to claim 1, characterized in that: The highly doped P well layers 2 (11) of adjacent VDMOS cells are integrated with each other, wherein the highly doped P well layer 2 (11) inhibits the N well layer charges from diffusing to the N well layer of the adjacent VDMOS cells.

7. The VDMOS with improved avalanche withstand capability according to claim 1, characterized in that: The cross-sectional profile thicknesses of the low drift layer 1 (12), the low drift layer 2 (13), the low drift layer 3 (14) and the high drift layer (15) decrease gradually.

8. The VDMOS with improved avalanche withstand capability according to claim 7, characterized in that: The doping concentration of the low drift layer 1 (12) is 6 to 8×10 16 mol / cm 3 ; The doping concentrations of the diffusion layer (6) and the second low drift layer (13) are both 2 to 4×10 16 mol / cm 3 ; The doping concentrations of the low-doped N-well layer (8) and the low drift layer 3 (14) are both 6 to 8×10 17 mol / cm 3 ; The doping concentrations of the highly doped N-well layer (7) and the high drift layer (15) are both 2 to 4×10 18 mol / cm 3 .

9. The VDMOS with improved avalanche withstand capability according to claim 1, characterized in that: The doping concentration of the low-doped P well layer 1 (9) is 7 to 8.6×10 16 mol / cm 3 ; The doping concentration of the highly doped P well layer 1 (10) is 2 to 6.3×10 18 mol / cm 3 ; The doping concentration of the highly doped P well layer 2 (11) is 5 to 8×10 18 mol / cm 3 .

10. The VDMOS with improved avalanche withstand capability according to claim 1, characterized in that: In the N-well layer, only the highly doped N-well layer (7) is ohmically short-circuited with the source electrode (2), and in the P-well layer, only the highly doped P-well layer 2 (11) is ohmically short-circuited with the source electrode (2).

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