Light emitting device

Abstract

The utility model provides a light-emitting device. The light-emitting device comprises a substrate; the box dam is arranged on the substrate; the at least one series chip group is arranged on the substrate and located in the area defined by the box dam, and the series chip group comprises more than two chip units and a circuit part for realizing series connection between the adjacent chip units of the same series chip group, a first isolation part is arranged between every two adjacent chip units of the same series chip set to isolate the adjacent chip units, a groove part is formed in each first isolation part, and a circuit part between every two adjacent chip units is arranged in the corresponding groove part in a penetrating mode; the signal transmission part comprises an input electrode and an output electrode, one end of the series chip set is electrically connected with the input electrode, and the other end of the series chip set is electrically connected with the output electrode; the optical part is arranged at the end, away from the substrate, of the box dam. The light-emitting device is small in light loss and high in photoelectric conversion efficiency, meanwhile, the multi-path flexible control effect can be achieved at the same time, and the wiring design between the chip units is smooth and concise.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor light sources, in particular to a light-emitting device. Background Art

[0002] For some scenarios with high optical power requirements, multiple chip units are usually set in the light-emitting device to meet the optical power requirements. The current common practice is to put multiple chip units in the same packaging cavity. The problems with this type of light-emitting device are:

[0003] 1. Large light loss: Multiple chip units are packaged in the same packaging cavity. The light emitted from the side of each chip unit will be blocked by other chips in the same packaging cavity and cannot be reflected, resulting in large light loss and reduced light output rate;

[0004] 2. Low photoelectric conversion efficiency: The photoelectric conversion efficiency of the chip unit will decrease as the temperature of the chip unit rises. Since multiple chip units are packaged in the same packaging chamber, the chip units are exposed to each other's sides, which causes heat to accumulate faster, the temperature of the chip unit to rise, and the photoelectric efficiency to decrease, which will also reduce the service life of the chip unit. Utility Model Content

[0005] One purpose of the utility model is to propose a light-emitting device that can significantly improve the problem of heat accumulation between chip units, so that the photoelectric conversion efficiency of the chip units is higher and the life is longer. The light-emitting device realizes multi-channel flexible control, while also ensuring the simplicity and smoothness of the product routing design, thereby simplifying the product processing technology and reducing product costs.

[0006] In order to solve the above technical problems, the utility model adopts the following technical solutions:

[0007] The technical solution of one aspect of the utility model proposes a light-emitting device, comprising: a substrate; a dam, arranged on the substrate; at least one series chip group, arranged on the substrate and located in the area surrounded by the dam, the series chip group comprising more than two chip units and a circuit portion for realizing series connection between adjacent chip units of the same series chip group, wherein a first isolation portion is provided between adjacent chip units of the same series chip group to separate adjacent chip units, each of the first isolation portions is provided with a groove portion, and the circuit portion between adjacent chip units is passed through the groove portion; at least one signal transmission portion, comprising an input electrode and an output electrode, one end of the series chip group being electrically connected to the input electrode, and the other end of the series chip group being electrically connected to the output electrode; an optical portion, arranged at one end of the dam away from the substrate.

[0008] According to some technical solutions of the present application, for the series chipset arranged adjacent to the dam, the groove portion on the first isolation portion is arranged at an end of the first isolation portion close to the dam.

[0009] According to some technical solutions of the present application, the first isolation portion extends from the substrate toward the optical portion, and one end of the first isolation portion away from the substrate is connected to the optical portion.

[0010] According to some technical solutions of the present application, the optical part includes: a first lens, the first lens is located at an end of the dam away from the substrate, the edge of the first lens is connected to the dam, and the end of the first isolation part away from the substrate is opposite to the surface of the first lens and connected to the first lens; or a compound eye lens array, including a plurality of second lenses arranged in an array, the second lens is arranged on a side of the chip unit facing away from the substrate, and the dam and the first isolation part are respectively connected to the second lens.

[0011] According to some technical solutions of the present application, the light-emitting device includes more than two of the series-connected chip groups, wherein a second isolation portion is provided between any adjacent series-connected chip groups to separate the chip units of the adjacent series-connected chip groups.

[0012] According to some technical solutions of the present application, the second isolation portion extends from the substrate toward the optical portion, and one end of the second isolation portion away from the substrate is connected to the optical portion.

[0013] According to some technical solutions of the present application, the dam is integrally formed with the first isolation portion; and / or the dam is integrally formed with the second isolation portion.

[0014] According to some technical solutions of the present application, a side surface of one or more of the dam, the first isolation portion and the second isolation portion is configured as a reflective surface that is vertical or inclined relative to the substrate.

[0015] According to some technical solutions of the present application, the series chipset is arranged on one side of the substrate along the wall thickness direction, a heat dissipation pad is arranged on the side of the substrate facing away from the series chipset, and one or more chip units of the series chipset are correspondingly connected to the heat dissipation pad along the wall thickness direction of the substrate.

[0016] According to some technical solutions of the present application, the input electrode and the output electrode are both arranged on the side of the substrate facing away from the series chip group, and the input electrode and the output electrode are distributed at positions around the heat dissipation pad and are spaced apart from the heat dissipation pad.

[0017] In the light-emitting devices provided by some technical solutions of the present application, a first isolation portion is arranged between two adjacent chip units. The two adjacent chip units are separated by the first isolation portion, so that light leakage between the two adjacent chip units can be prevented. In this way, on the one hand, the two adjacent chip units will not block light from each other's sides, so that the light of each chip unit can be better reflected, reducing light loss and improving light output. On the other hand, the temperature of the chip units will not rise too high due to mutual irradiation between the two adjacent chip units, thereby improving the problem of heat accumulation between the chip units, making the photoelectric conversion efficiency of the chip units higher and the service life of the chip units longer.

[0018] Among them, a groove is set on the first isolation part, and the groove avoids the routing space of the series line (i.e., the line part) of the adjacent chip units, and the line part of the series connection of two adjacent chip units can be placed in the groove for routing. In this way, on the basis of using the first isolation part to solve the problems of light leakage and heat accumulation, the routing design between the chip units is smoother and simpler by using the groove for routing, and there is no need to use the punching method to set the line from the side of the substrate facing away from the dam. The production and processing technology of the product is correspondingly simplified and the cost is lower; and this structural setting only needs to connect the input electrode and the output electrode to control the entire series chip group set in series, and achieve the effect of multi-channel flexible control.

[0019] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0021] Figure 1 It is a schematic diagram of the main structure of the light-emitting device in Example 1 of the present application.

[0022] Figure 2 yes Figure 1 Schematic diagram of the structure of the AA section.

[0023] Figure 3 It is a schematic diagram of the rear view structure of the light emitting device in Example 1 of the present application.

[0024] Figure 4 It is a schematic diagram of the main structure of the dam in Example 1 of the present application.

[0025] Figure 5 yes Figure 4 Schematic diagram of the structure of the BB section.

[0026] Figure 6 It is a schematic diagram of the cross-sectional structure of the light-emitting device in the second embodiment of the present application.

[0027] Figure 7 It is a schematic diagram of the cross-sectional structure of the light-emitting device in Example 3 of the present application.

[0028] Figure 8 It is a schematic diagram of the main structure of the light-emitting device in Example 4 of the present application.

[0029] Fig. 9 yes Figure 8 Schematic diagram of the structure of the CC section.

[0030] Fig.10 It is a schematic diagram of the main structure of the light-emitting device in Example 5 of the present application.

[0031] Fig.11 It is a schematic diagram of the main structure of the light-emitting device in Example 6 of the present application.

[0032] Fig.12 It is a schematic diagram of the rear view structure of the light emitting device in Example 6 of the present application.

[0033] Fig.13 It is a schematic diagram of the main structure of the light-emitting device in Example 7 of the present application.

[0034] Fig.14 It is a schematic diagram of the rear view structure of the light-emitting device in Example 7 of the present application.

[0035] Fig.15 It is a schematic diagram of the main structure of the light-emitting device in Example 8 of the present application.

[0036] Fig.16 It is a schematic diagram of the rear view structure of the light-emitting device in Example 8 of the present application.

[0037] The reference numerals are as follows:

[0038] 1. light emitting device; 10. substrate; 11. heat dissipation pad; 20. dam; 21. first isolation portion; 211. inclined surface; 212. step; 213. groove portion; 22. second isolation portion; 61. first lens; 62. second lens; 70. first metallization layer; 71. second metallization layer;

[0039] 30a, first series chip group; 31a, first chip unit; 32a, second chip unit; 40a, first line portion; 511a, first input electrode; 512a, first output electrode;

[0040] 30b, second series chip group; 31b, third chip unit; 32b, fourth chip unit; 33b, fifth chip unit; 40b, second line unit; 41b, third line unit; 511b, second input electrode; 512b, second output electrode;

[0041] 30c, third series chip group; 31c, sixth chip unit; 32c, seventh chip unit; 33c, eighth chip unit; 34c, ninth chip unit; 40c, fourth line unit; 41c, fifth line unit; 42c, sixth line unit; 511c, third input electrode; 512c, third output electrode;

[0042] 30d, fourth series chip group; 31d, tenth chip unit; 32d, eleventh chip unit; 41d, seventh line portion; 511d, fourth input electrode; 512d, fourth output electrode. DETAILED DESCRIPTION

[0043] Although the present invention can be easily embodied in different forms of embodiments, only some of the specific embodiments are shown in the drawings and described in detail in this specification. It should be understood that this description should be regarded as an exemplary description of the principles of the present invention and is not intended to limit the present invention to that described herein.

[0044] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the utility model, rather than implying that each embodiment of the utility model must have the described feature. In addition, it should be noted that this specification describes many features. Although certain features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting. The multiple referred to in this specification can be understood as two or more.

[0045] In the embodiments shown in the drawings, the indications of directions (such as up, down, left, right, front, back, etc.) used to explain the structure and movement of various elements of the utility model are not absolute but relative. These descriptions are appropriate when these elements are in the positions shown in the drawings. If the descriptions of the positions of these elements change, the indications of these directions also change accordingly.

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of the utility model will be more comprehensive and complete, and the concepts of the example embodiments will be fully conveyed to those skilled in the art. The accompanying drawings are only schematic illustrations of the utility model and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0047] Embodiment 1

[0048] like Figures 1 to 5As shown, this embodiment provides a light emitting device 1.

[0049] The light emitting device 1 can be used to convert electrical energy into light for output. For example, the light emitting device 1 can be specifically an integrated LED (light-emitting diode) device, more specifically an integrated UV-LED (Ultraviolet-light-emitting diode) device that can be used to output ultraviolet light. Specifically, the light emitting device 1 includes a plurality of chip units integrated therein, and the chip units can be specifically LED chips, UV-LED chips, etc. The light emitting device 1 integrates a plurality of chip units and utilizes the plurality of chip units to emit light to obtain a higher light emitting efficiency.

[0050] For example, in more detail, Figure 1 and Figure 2 It can be understood that the light emitting device 1 includes: a substrate 10, a dam 20, a plurality of chip units, at least one signal transmission part, and an optical part.

[0051] The material of the substrate 10 can be selected as a ceramic substrate material, such as aluminum nitride ceramic (ALN), gallium nitride ceramic (GaN), aluminum oxide ceramic (Al2O3), silicon carbide ceramic (SiC), etc.

[0052] The substrate 10 may be configured to be in the shape of a plate with a certain wall thickness. A surface of the substrate 10 at one end along the wall thickness direction is defined as a first surface, and a surface of the substrate 10 at the other end along the wall thickness direction is defined as a second surface.

[0053] The dam 20 is disposed on the first surface of the substrate 10. When viewed from a direction perpendicular to the substrate 10, the shape of the dam 20 may be as follows: Figure 1 Of course, it is understood that the shape design of the dam 20 can have many implementation schemes and is not limited to the following Figure 1 The displayed rectangle.

[0054] Optionally, the dam 20 can be made together with the substrate 10 as a part of the substrate 10. Alternatively, the dam 20 and the substrate 10 can also be made separately, and then the dam 20 and the substrate 10 are combined together by bonding or welding. For example, in some optional examples, the dam 20 and the substrate 10 can be bonded together by glue, and the glue can be silicone, epoxy resin, and fluororesin. Or, in some optional examples, such as Figure 5As shown, after the bottom of the dam 20 is metallized to form a second metallization layer 71 (for example, after the bottom is gold-plated to form a gold-plated layer), the dam 20 is soldered to the substrate 10 by soldering, and the solder for soldering can be tin paste or gold-tin alloy. Optionally, in the case where the dam 20 is independently manufactured, the material of the dam 20 is not limited to metal, and can also be non-metallic materials such as silicon, quartz, Teflon, etc.

[0055] like Figure 1 and Figure 2 As shown, multiple chip units are respectively arranged on the substrate 10, and the multiple chip units are located in the area surrounded by the dam 20. The optical part is arranged at one end of the dam 20 away from the substrate 10, and the optical part can be used to encapsulate the chip units in the dam 20 and the substrate 10.

[0056] A step 212 may be provided at one end of the dam 20 away from the substrate 10 . The step 212 may be provided for embedded installation of the optical part, thereby achieving a better positioning effect of the optical part.

[0057] Multiple chip units are arranged to form at least one series chip group. For example, each series chip group includes more than two chip units and a circuit portion for realizing series connection between adjacent chip units of the same series chip group, wherein a first isolation portion 21 is arranged between adjacent chip units of the same series chip group to separate adjacent chip units, and each first isolation portion 21 is provided with a groove portion 213, and the circuit portion between adjacent chip units is passed through the groove portion 213.

[0058] At least one signal transmission unit is disposed on the second surface of the substrate 10 . The signal transmission unit includes an input electrode and an output electrode. One end of the series chip group is electrically connected to the input electrode, and the other end of the series chip group is electrically connected to the output electrode.

[0059] In this embodiment, a first isolating portion 21 is provided between two adjacent chip units, and the two adjacent chip units are separated by the first isolating portion 21, so that light leakage between the two adjacent chip units can be prevented. Thus, on the one hand, the two adjacent chip units will not block light from each other's sides, so that the light of each chip unit can be better reflected, thereby reducing light loss and improving light output efficiency. On the other hand, the temperature of the chip units will not rise too high due to mutual irradiation between the two adjacent chip units, thereby improving the problem of heat accumulation between the chip units, making the photoelectric conversion efficiency of the chip units higher and the service life of the chip units longer.

[0060] Among them, a groove 213 is set on the first isolation part 21, and the groove 213 avoids the routing space of the series circuit (i.e., the circuit part) of the adjacent chip units, and the circuit part of the series connection of two adjacent chip units can be inserted into the groove 213 for routing. In this way, on the basis of using the first isolation part 21 to solve the problems of light crosstalk and heat accumulation, the groove 213 is used for routing, so that the routing design between the chip units is smoother and simpler, and there is no need to use a punching method to set the circuit from the side of the substrate 10 facing away from the dam 20, and the production and processing technology of the product is correspondingly simplified and the cost is lower; and this structural setting only needs to connect the input electrode and the output electrode to control the entire series chip group set in series, and achieve the effect of multi-channel flexible control.

[0061] Optionally, the light emitting device 1 includes more than two series-connected chip groups, wherein a second isolating portion 22 is provided between any adjacent series-connected chip groups to separate the chip units of the adjacent series-connected chip groups. In this way, the second isolating portion 22 can be used to prevent light from crossing and to insulate the chip units of the adjacent series-connected chip groups, thereby further improving the light extraction rate and the photoelectric conversion efficiency, and extending the life of the chip units. Accordingly, more than two signal transmission portions are provided, so that the series-connected chip group and the signal transmission portion form a one-to-one arrangement, and the series-connected chip group corresponding to the signal transmission portion can be controlled accordingly through the signal transmission portion, and the multi-channel flexible control effect is better.

[0062] For a more detailed example, a 2*2 array of dual-channel independently controlled light emitting devices 1 is used as an example. Figure 1 The light emitting device 1 specifically includes four chip units, which are arranged into two first series chip groups 30a, each of which includes two chip units, which are named as the first chip unit 31a and the second chip unit 32a, respectively, and each of which includes a first circuit portion 40a that connects the first chip unit 31a and the second chip unit 32a in series.

[0063] Two corresponding first circuit portions 40a are arranged on the first surface of the substrate 10. For example, the circuit copper material is sintered on the substrate 10, so that the two first circuit portions 40a are formed on the first surface of the substrate 10. The first chip unit 31a and the second chip unit 32a of one first series chip group 30a are arranged on one first circuit portion 40a to realize the first chip unit 31a and the second chip unit 32a are connected in series; the first chip unit 31a and the second chip unit 32a of another first series chip group 30a are arranged on another first circuit portion 40a to realize the first chip unit 31a and the second chip unit 32a are connected in series.

[0064] See also Figure 1 and Figure 2The dam 20 is a vertical cavity square copper dam 20 with a step 212. The dam 20 is substantially vertically disposed on the first surface of the substrate 10, and encloses a packaging cavity together with the substrate 10. Optionally, the respective molding of the circuit portion and the dam 20, and the connection between the substrate 10 and the circuit portion and the dam 20, can adopt a DPC (direct plating copper) process, and the general steps include: 1. Sintering the circuit copper material on the ceramic substrate 10; 2. Making the circuit; 3. Electroplating the dam 20; 4. Surface treatment. The DPC process is well known to those skilled in the art and will not be repeated here.

[0065] Optionally, the side surface of the dam 20 close to the packaging cavity is set to be substantially perpendicular to the reflective surface of the substrate 10. Of course, in other embodiments, the side surface of the dam 20 close to the packaging cavity can also be set to be a reflective surface inclined relative to the substrate 10, that is, an inclined surface (such as Fig. 9 shown).

[0066] Optionally, the first chip unit 31a and / or the second chip unit 32a are flip-chip UV-LED chips, and the electrodes of the first chip unit 31a and / or the second chip unit 32a can be selected as gold-tin alloys. The first chip unit 31a and / or the second chip unit 32a can be welded on the substrate 10 using a eutectic process, and the eutectic temperature can be selected to be greater than or equal to 280°C. Optionally, in other embodiments, flux can also be applied to the first circuit portion 40a of the substrate 10, and the first chip unit 31a and / or the second chip unit 32a can be fixed to the place where the flux is applied. The role of the flux is to act as a medium for eutectic, so that the chip unit and the substrate 10 can be better bonded during eutectic welding. Of course, the chip unit and the substrate 10 can be directly eutectic welded without using flux. Optionally, in eutectic welding, the temperature zone of the eutectic furnace is 280°C-340°C. Optionally, a vacuum is maintained or nitrogen is filled in the eutectic process for protection.

[0067] See also Figure 2 The optical part can be optionally a first lens 61, which is located at one end of the dam 20 away from the substrate 10 to encapsulate the packaging chamber, wherein the edge of the first lens 61 is located on the step 212 of the dam 20 to achieve embedded installation of the first lens 61, thereby achieving a better positioning effect of the first lens 61.

[0068] Optionally, the first lens 61 may be configured as follows: Figure 2The plane lens shown in the figure can be specifically a glass lens, and its material can be selected from quartz or sapphire, etc. The positions where the bottom of the first lens 61 contacts the dam 20 are connected to each other to achieve a more reliable fixation of the first lens 61. For example, the position where the bottom of the first lens 61 contacts the dam 20 is metallized to form a first metallization layer 70, and the first metallization layer 70 can be a gold-tin alloy plating layer. For example, the gold content in the gold-tin alloy plating layer is 80%, the tin content is 20%, and the melting point is 280°C. The gold-tin alloy plating layer of the first lens 61 is welded to the dam 20 of the substrate 10 by welding, for example, applying flux or coating gold-tin solder on the first metallization layer 70, and then placing the first lens 61 on the step 212 of the dam 20 for eutectic welding. Of course, the connection method between the first lens 61 and the dam 20 is not limited to the welding method exemplified above. In other embodiments, the first lens 61 may not be metallized, and the bottom edge of the first lens 61 may be directly bonded to the step 212 of the dam 20 using glue.

[0069] A plurality of first isolation parts 21 and second isolation parts 22 are distributed in the dam 20. The first isolation parts 21 and the second isolation parts 22 can be Figure 1 As shown, the first isolating portion 21 and / or the second isolating portion 22 are arranged on the dam 20 and are formed integrally with the dam 20. Of course, the present application is not limited thereto, and in other embodiments, the first isolating portion 21 and / or the second isolating portion 22 may also be arranged on the dam 20 and are formed separately from the dam 20, or the first isolating portion 21 and / or the second isolating portion 22 may also be arranged on the substrate 10 and are formed integrally with or separately from the substrate 10.

[0070] See also Figure 4 The second isolation portion 22 divides the packaging cavity in the dam 20 into two left and right areas. The two first series chip groups 30a are arranged in the left and right areas, so that the two first series chip groups 30a are separated by the second isolation portion 22 to achieve light leakage prevention and heat insulation between the two first series chip groups 30a.

[0071] A first isolation portion 21 is respectively provided in the left and right areas of the packaging cavity, and the first chip unit 31a and the second chip unit 32a of the first series chip group 30a in the left area of ​​the packaging cavity are separated by the first isolation portion 21 in the left area, and the first circuit portion 40a of the first series chip group 30a in the left area of ​​the packaging cavity is passed through the groove portion 213 of the first isolation portion 21 in the left area for routing; the first chip unit 31a and the second chip unit 32a of the first series chip group 30a in the right area of ​​the packaging cavity are separated by the first isolation portion 21 in the right area, and the first circuit portion 40a of the first series chip group 30a in the right area of ​​the packaging cavity is passed through the groove portion 213 of the first isolation portion 21 in the right area for routing.

[0072] Two signal transmission parts are respectively arranged on the second surface of the substrate 10 corresponding to the two first series chip groups 30a. The two signal transmission parts are roughly arranged on the back of the left and right areas of the packaging cavity. Each signal transmission part includes a first input electrode 511a and a first output electrode 512a. The first input electrode 511a and the first output electrode 512a on the back of the left area of ​​the packaging cavity are respectively electrically connected to the first chip unit 31a and the second chip unit 32a in the left area of ​​the packaging cavity; the first input electrode 511a and the first output electrode 512a on the back of the right area of ​​the packaging cavity are respectively electrically connected to the first chip unit 31a and the second chip unit 32a in the right area of ​​the packaging cavity. Thus, the first chip unit 31a and the second chip unit 32a in the first series chip group 30a can be controlled to emit light or turn off at the same time without separately setting a set of input electrodes and output electrodes for the first chip unit 31a and separately setting a set of input electrodes and output electrodes for the second chip unit 32a, thereby simplifying the electrode setting of the product and making the control of the multi-channel series chip group more flexible.

[0073] Optionally, the first isolation portion 21 in the left area and the first isolation portion 21 in the right area are both arranged orthogonally to the second isolation portion 22, and the first isolation portion 21 in the left area and the first isolation portion 21 in the right area are symmetrically arranged with the second isolation portion 22 as the center, so that the first isolation portion 21, the second isolation portion 22 and the dam 20 enclose 4 independent rectangular or square chambers, and each first chip unit 31a and each second chip unit 32a are accommodated in a separate chamber to form a single crystal single cavity structure. Compared with the structure of multiple crystals with the same cavity, it is convenient to install and position the chip unit, and can avoid the heat collection phenomenon caused by mutual shielding between the chip units. Under the same conditions, the heat dissipation effect of the single crystal single cavity structure is better than that of the multiple crystals with the same cavity structure. The chip unit temperature of the single crystal single cavity structure is lower than that of the multiple crystals with the same cavity structure, which can effectively improve the service life and luminous efficiency of the chip unit and reduce light loss. Furthermore, the layout of the first isolation portion 21 and the second isolation portion 22 can also enhance the strength and structural stability of the first isolation portion 21 and / or the second isolation portion 22, and is conducive to simplifying product molds and reducing costs.

[0074] Combination Figure 4 and Figure 5 It can be understood that the groove 213 of the first isolation part 21 in the left area is arranged at the left end so as to be close to the dam 20 and away from the second isolation part 22, and the groove 213 of the first isolation part 21 in the right area is arranged at the right end so as to be close to the dam 20 and away from the second isolation part 22. With such a design, when the hot air on both sides of the first isolation part 21 in the left area is intercommunicated along the groove 213 at the left end, or when the hot air on both sides of the first isolation part 21 in the right area is intercommunicated along the groove 213 at the right end, since the groove 213 is close to the dam 20, the heat of the hot air can be efficiently dissipated through the dam 20 in large quantities, avoiding heat accumulation, so as to further improve the photoelectric conversion efficiency, improve the working environment temperature of the chip unit, and extend the life of the chip unit.

[0075] Optionally, the first isolation portion 21 extends from the substrate 10 toward the first lens 61, and one end of the first isolation portion 21 away from the substrate 10 is opposite to the surface of the first lens 61 and connected to the first lens 61. For specific examples, see Figure 2 , the position of the first lens 61 corresponding to the first isolation portion 21 is also metallized to form a first metallized layer 70, and the first lens 61 is welded to the first isolation portion 21 through the first metallized layer 70 at the position corresponding to the first isolation portion 21. Of course, in other embodiments, the position of the first lens 61 corresponding to the first isolation portion 21 may not be metallized, and the position of the first lens 61 corresponding to the first isolation portion 21 may be directly bonded to the first isolation portion 21 using glue.

[0076] Connecting the position of the first lens 61 corresponding to the first isolation portion 21 to the first lens 61 (such as bonding or welding) can further improve the mounting stability of the first lens 61, and can improve the sealing isolation between adjacent single cavities, reduce heat interference between adjacent chip units, further reduce heat accumulation, and improve the photoelectric conversion rate.

[0077] Optionally, the second isolation portion 22 extends from the substrate 10 toward the first lens 61, and one end of the second isolation portion 22 away from the substrate 10 is opposite to the surface of the first lens 61 and connected to the first lens 61. For example, the position of the first lens 61 corresponding to the second isolation portion 22 is also metallized to form a first metallization layer 70, and the first lens 61 is welded to the second isolation portion 22 through the first metallization layer 70 corresponding to the position of the second isolation portion 22. Of course, in other embodiments, the position of the first lens 61 corresponding to the second isolation portion 22 may not be metallized, and the position of the first lens 61 corresponding to the second isolation portion 22 is directly bonded to the second isolation portion 22 using glue.

[0078] Connecting the position of the first lens 61 corresponding to the second isolation portion 22 to the first lens 61 (such as bonding or welding) can further improve the mounting stability of the first lens 61, and can reduce heat interference between chip units of adjacent series chip components, further reduce heat accumulation, and improve photoelectric conversion efficiency.

[0079] See also Figure 3 A heat dissipation pad 11 is also provided on the second surface of the substrate 10. In the two first series chip groups 30a, the two first chip units 31a and the two second chip units 32a are correspondingly connected to the heat dissipation pad 11 along the wall thickness direction of the substrate 10. In this way, each first chip unit 31a and the second chip unit 32a can dissipate heat through the heat dissipation pad 11, thereby further reducing the heat accumulation in the packaging cavity and further improving the photoelectric conversion rate.

[0080] More specifically, the heat dissipation pad 11 can be set in the middle position of the second surface of the substrate 10, and the input electrode and the output electrode are dispersed on the surrounding side of the heat dissipation pad 11 and are spaced from the heat dissipation pad 11. In this way, the same heat dissipation pad 11 can correspond to more chip units, thereby achieving heat dissipation of more chip units. Such a design is also beneficial to the heat dissipation of the middle position of the packaging cavity through the heat dissipation pad 11, avoiding heat accumulation in the middle, thereby improving the photoelectric conversion efficiency.

[0081] Optionally, a metal layer is plated on the surface of components such as the circuit portion (such as the first circuit portion 40a) and / or the heat dissipation pad 11, and / or the dam 20 on the surface of the substrate 10. The metal layer is, for example, a nickel-gold layer, wherein the thickness of the nickel can be selected to be greater than or equal to 3 μm, and the thickness of the gold can be selected to be greater than or equal to 0.05 μm. This can facilitate the welding of components such as the chip unit and the first lens 61, and is also beneficial for protecting the circuit portion, the dam 20, etc. from oxidation.

[0082] In summary, in the light-emitting device 1 of the present embodiment, the first chip unit 31a and the second chip unit 32a in the same first series chip group 30a are connected in series through the first line portion 40a, and the input electrode and the output electrode of the same first series chip group 30a are arranged on the back side (and the second surface) of the substrate 10. It is only necessary to connect the input electrode and the output electrode on the back side of the substrate 10 to control the entire first series chip group 30a, and the control is flexible; the first chip unit 31a and the second chip unit 32a in the first series chip group 30a are separated by the first isolation portion 21, and the individual first chip unit 31a or the second chip unit 32a can only emit light and generate heat in its individual area, and will not block the light emission of the adjacent chip units, which can greatly isolate the accumulation of heat. Furthermore, through the heat dissipation pad 11 that occupies most of the area in the middle of the back side of the substrate 10 and is shared by multiple chip units, a small amount of accumulated heat is conducted away, which can completely eliminate the influence caused by the accumulated heat caused by the flow through the grooves 213. Compared with the structure of the polycrystalline same cavity, the light conversion efficiency of the light-emitting device 1 shows an overall upward trend, thereby improving the energy efficiency of the product.

[0083] Embodiment 2

[0084] like Figure 6 As shown, this embodiment provides a light emitting device 1.

[0085] The differences from the above-mentioned embodiment 1 include:

[0086] The optical part of this embodiment includes a first lens 61. The first lens 61 can be arranged as follows Figure 6 The hemispherical lens shown in the figure can be made of quartz or sapphire.

[0087] In addition to the above differences, other features of the light emitting device 1 of this embodiment that have not been described in detail have been recorded in the first embodiment and will not be repeated here.

[0088] Embodiment 3

[0089] like Figure 7 As shown, this embodiment provides a light emitting device 1.

[0090] The differences from the above-mentioned embodiment 1 include:

[0091] The optical part of this embodiment includes a plurality of second lenses 62 . The plurality of second lenses 62 are all disposed on a side of the chip unit facing away from the substrate 10 . The plurality of second lenses 62 are arranged in an array to form a fly-eye lens array.

[0092] Optionally, the second lens 62 and the chip unit are arranged in a one-to-one correspondence, for example Figure 7 As shown, for the first series chip group 30a including the first chip unit 31a and the second chip unit 32a, a second lens 62 is arranged on the side of the first chip unit 31a facing away from the substrate 10, and a second lens 62 is arranged on the side of the second chip unit 32a facing away from the substrate 10. The first chip unit 31a and the second chip unit 32a are separated by the first isolation portion 21, and the two second lenses 62 are not separated and are directly adjacent to each other to form a compound eye lens array. A portion of the edge of each second lens 62 is connected to the step 212 of the dam 20 (such as welding or bonding), and another portion of the edge is connected to the first isolation portion 21 (such as welding or bonding), so that the second lens 62 can be assembled more firmly.

[0093] In addition to the above differences, other features of the light emitting device 1 of this embodiment that have not been described in detail have been recorded in the first embodiment and will not be repeated here.

[0094] Embodiment 4

[0095] like Figure 8 and Fig. 9 As shown, this embodiment provides a light emitting device 1.

[0096] The differences from the above-mentioned embodiment 1 include:

[0097] In this embodiment, the side wall surface of the dam 20 close to the packaging cavity is configured as a reflective surface inclined relative to the substrate 10, namely, an inclined surface 211. The light is reflected by the inclined reflective surface, thereby improving the light extraction efficiency.

[0098] Further optionally, the side surface of the first isolation portion 21 is also configured as a reflective surface inclined relative to the substrate 10, that is, a slope 211, so as to further improve the light extraction efficiency.

[0099] In addition to the above differences, other features of the light emitting device 1 of this embodiment that have not been described in detail have been recorded in the first embodiment and will not be repeated here.

[0100] Embodiment 5

[0101] like Fig.10 As shown, this embodiment provides a light emitting device 1.

[0102] The differences from the above-mentioned embodiment 1 include:

[0103] In this embodiment, viewed from a direction perpendicular to the substrate 10, the dam 20, the first isolating portion 21, and the second isolating portion 22 are all configured with arc portions, so that the arc portions of the dam 20, the arc portions of the first isolating portion 21, and the arc portions of the second isolating portion 22 together form a circular or circular-like chamber. Compared with the square or rectangular chamber in the first embodiment, the circular or circular-like chamber in this embodiment reflects light more evenly, which can further improve the efficiency. Of course, the present design is not limited to this. In other embodiments, viewed from a direction perpendicular to the substrate 10, the shape of the chamber can also be designed to be elliptical, rhombus, pentagonal, etc.

[0104] In addition to the above differences, other features of the light emitting device 1 of this embodiment that have not been described in detail have been recorded in the first embodiment and will not be repeated here.

[0105] Embodiment 6

[0106] like Fig.11 and Fig.12 As shown, this embodiment provides a light emitting device 1.

[0107] The differences from the above-mentioned embodiment 1 include:

[0108] In this embodiment, the light emitting device 1 includes nine chip units. Take the light emitting device 1 with three independent control modes arranged in 3*3 as an example. Fig.11 The nine chip units of the light-emitting device 1 are arranged on the first surface of the substrate 10, and the nine chip units are arranged to form three second series chip groups 30b. The three second series chip groups 30b are arranged in a lateral interval, and a second isolation portion 22 is provided between any adjacent second series chip groups 30b to separate two adjacent second series chip groups 30b.

[0109] Each second series chip group 30b includes a third chip unit 31b, a fourth chip unit 32b, and a fifth chip unit 33b arranged in a longitudinal interval, and a second circuit portion 40b connecting the third chip unit 31b and the fourth chip unit 32b in the same second series chip group 30b in series, and a third circuit portion 41b connecting the fourth chip unit 32b and the fifth chip unit 33b in the same second series chip group 30b in series.

[0110] A first isolation part 21 with a groove 213 is provided between the third chip unit 31b and the fourth chip unit 32b to separate the third chip unit 31b from the fourth chip unit 32b, and the second line part 40b between the third chip unit 31b and the fourth chip unit 32b is arranged in the groove 213 of the first isolation part 21 for routing. A first isolation part 21 with a groove 213 is provided between the fifth chip unit 33b and the fourth chip unit 32b to separate the fifth chip unit 33b from the fourth chip unit 32b, and the third line part 41b between the fifth chip unit 33b and the fourth chip unit 32b is arranged in the groove 213 of the first isolation part 21 for routing.

[0111] The groove 213 of the first isolation part 21 in the second series chipset group 30 b located at the leftmost end in the lateral direction is arranged at the left end of the first isolation part 21 to be close to the dam 20 and away from the second isolation part 22 for heat dissipation.

[0112] The groove 213 of the first isolation part 21 in the second series chip group 30 b located at the rightmost end in the lateral direction is arranged at the right end of the first isolation part 21 to be close to the dam 20 and away from the second isolation part 22 for heat dissipation.

[0113] See also Fig.12 , three signal transmission parts are arranged on the second surface of the substrate 10 to correspond to the three second series chip groups 30b one by one. Each signal transmission part includes a second input electrode 511b and a second output electrode 512b. One end of each second series chip group 30b (such as the third chip unit 31b or the second line part 40b) is electrically connected to the second input electrode 511b of the corresponding signal transmission part, and the other end of each second series chip group 30b (such as the fifth chip unit 33b or the third line part 41b) is electrically connected to the second output electrode 512b of the corresponding signal transmission part. In this way, by connecting the external current signal separately through the three signal transmission parts, the second series chip group 30b can be controlled separately accordingly, realizing the three-way independent control of the 3*3 arrangement.

[0114] A heat dissipation pad 11 is provided on the second surface of the substrate 10, and the second input electrodes 511b of the three signal transmission parts are spaced apart on one side of the heat dissipation pad 11, and the second output electrodes 512b of the three signal transmission parts are spaced apart on the other side of the heat dissipation pad 11, so that the nine chip units can share the heat dissipation pad 11.

[0115] In addition to the above differences, other features of the light emitting device 1 of this embodiment that have not been described in detail have been recorded in the first embodiment and will not be repeated here.

[0116] Embodiment 7

[0117] like Fig.13 and Fig.14 As shown, this embodiment provides a light emitting device 1.

[0118] The differences from the above-mentioned embodiment 1 include:

[0119] In this embodiment, the light emitting device 1 includes sixteen chip units. Take the light emitting device 1 in the form of a 4*4 arrangement with four independent controls as an example. Fig.13 The sixteen chip units of the light-emitting device 1 are arranged on the first surface of the substrate 10, and the sixteen chip units are arranged to form four third series chip groups 30c. The four third series chip groups 30c are arranged in a horizontal interval, and a second isolation portion 22 is provided between any adjacent third series chip groups 30c to separate two adjacent third series chip groups 30c.

[0120] Each third series chip group 30c includes a sixth chip unit 31c, a seventh chip unit 32c, an eighth chip unit 33c, and a ninth chip unit 34c arranged in a longitudinal interval, and a fourth circuit portion 40c connecting the sixth chip unit 31c and the seventh chip unit 32c in series within the same third series chip group 30c, a fifth circuit portion 41c connecting the seventh chip unit 32c and the eighth chip unit 33c in series within the same third series chip group 30c, and a sixth circuit portion 42c connecting the eighth chip unit 33c and the ninth chip unit 34c in series within the same third series chip group 30c.

[0121] A first isolation part 21 with a groove 213 is provided between the sixth chip unit 31c and the seventh chip unit 32c to separate the sixth chip unit 31c from the seventh chip unit 32c, and the fourth line part 40c between the sixth chip unit 31c and the seventh chip unit 32c is arranged in the groove 213 of the first isolation part 21 for routing. A first isolation part 21 with a groove 213 is provided between the seventh chip unit 32c and the eighth chip unit 33c to separate the seventh chip unit 32c from the eighth chip unit 33c, and the fifth line part 41c between the seventh chip unit 32c and the eighth chip unit 33c is arranged in the groove 213 of the first isolation part 21 for routing. A first isolation portion 21 with a groove 213 is disposed between the eighth chip unit 33c and the ninth chip unit 34c to separate the eighth chip unit 33c from the ninth chip unit 34c. The sixth line portion 42c between the eighth chip unit 33c and the ninth chip unit 34c passes through the groove 213 of the first isolation portion 21 for routing.

[0122] The groove 213 of the first isolation part 21 in the third series-connected chipset 30 c located at the leftmost end in the lateral direction is arranged at the left end of the first isolation part 21 to be close to the dam 20 and away from the second isolation part 22 for heat dissipation.

[0123] The groove 213 of the first isolation part 21 in the third series chip group 30c located at the rightmost end in the lateral direction is arranged at the right end of the first isolation part 21 to be close to the dam 20 and away from the second isolation part 22 for heat dissipation.

[0124] See also Fig.14 , four signal transmission parts are arranged on the second surface of the substrate 10 to correspond to the four third series chip groups 30c one by one. Each signal transmission part includes a third input electrode 511c and a third output electrode 512c. One end of each third series chip group 30c (such as the sixth chip unit 31c or the fourth line part 40c) is electrically connected to the third input electrode 511c of the corresponding signal transmission part, and the other end of each third series chip group 30c (such as the ninth chip unit 34c or the sixth line part 42c) is electrically connected to the third output electrode 512c of the corresponding signal transmission part. In this way, by connecting the external current signal separately through the four signal transmission parts, the third series chip group 30c can be controlled separately and correspondingly, realizing four-way independent control of the 4*4 arrangement.

[0125] A heat dissipation pad 11 is provided on the second surface of the substrate 10, and the third input electrodes 511c of the four signal transmission parts are spaced apart on one side of the heat dissipation pad 11, and the third output electrodes 512c of the four signal transmission parts are spaced apart on the other side of the heat dissipation pad 11, so that the sixteen chip units can share the heat dissipation pad 11.

[0126] In addition to the above differences, other features of the light emitting device 1 of this embodiment that have not been described in detail have been recorded in the first embodiment and will not be repeated here.

[0127] Embodiment 8

[0128] like Fig.15 and Fig.16 As shown, this embodiment provides a light emitting device 1.

[0129] The differences from the above-mentioned embodiment 1 include:

[0130] In this embodiment, the light emitting device 1 includes two chip units. Fig.15 The two chip units of the light-emitting device 1 are arranged on the first surface of the substrate 10, and the two chip units are arranged to form a fourth series chip group 30d. The fourth series chip group 30d includes a tenth chip unit 31d and an eleventh chip unit 32d arranged in a longitudinal interval, and a seventh line portion 41d that connects the tenth chip unit 31d and the eleventh chip unit 32d in series.

[0131] A first isolation portion 21 with a groove 213 is disposed between the tenth chip unit 31d and the eleventh chip unit 32d to separate the tenth chip unit 31d from the eleventh chip unit 32d. The seventh circuit portion 41d of the tenth chip unit 31d and the eleventh chip unit 32d passes through the groove 213 of the first isolation portion 21 for routing.

[0132] See also Fig.16 A signal transmission unit is provided on the second surface of the substrate 10, and the signal transmission unit includes a fourth input electrode 511d and a fourth output electrode 512d. One end of the fourth series chip group 30d (such as the tenth chip unit 31d) is electrically connected to the fourth input electrode 511d of the corresponding signal transmission unit, and the other end of the fourth series chip group 30d (such as the eleventh chip unit 32d) is electrically connected to the fourth output electrode 512d of the corresponding signal transmission unit, so that the tenth chip unit 31d and the eleventh chip unit 32d can be controlled simultaneously.

[0133] A heat dissipation pad 11 is disposed on the second surface of the substrate 10 , and the fourth input electrode 511 d and the fourth output electrode 512 d are disposed on opposite sides of the heat dissipation pad 11 , so that the tenth chip unit 31 d and the eleventh chip unit 32 d share the heat dissipation pad 11 .

[0134] In addition to the above differences, other features of the light emitting device 1 of this embodiment that have not been described in detail have been recorded in the first embodiment and will not be repeated here.

[0135] Of course, the number of series chip groups included in the light-emitting device 1 is not limited to the one exemplified in the eighth embodiment, the two exemplified in the first embodiment, the three exemplified in the sixth embodiment, and the four exemplified in the seventh embodiment. It can be understood that in other embodiments, the number of series chip groups included in the light-emitting device 1 can also be set to five, six, seven or even more according to needs.

[0136] Of course, the number of chip units included in each serial chipset is not limited to the two exemplified in Example 1, the three exemplified in Example 6, and the four exemplified in Example 7. It is understandable that in other embodiments, the number of chip units included in the serial chipset can be set to five, six, seven or even more according to needs.

[0137] Even in each light-emitting device 1, the number of chip units of different series chip groups can be set to be different. For example, for the two first series chip groups 30a in Example 1, the number of chip units included in one of them can be set to two, and the number of chip units included in the other can be set to three or four or five, etc., so as to realize different arrangements and combinations of multi-channel independent control to meet more lighting scene requirements.

[0138] Although the utility model has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the utility model can be implemented in a variety of forms without departing from the spirit or essence of the utility model, it should be understood that the above-mentioned embodiments are not limited to any of the aforementioned details, but should be widely interpreted within the spirit and scope defined by the attached claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the attached claims.

Claims

1. A light emitting device, characterized in that: include: substrate; A dam is arranged on the substrate; At least one serial chip group is arranged on the substrate and is located in the area surrounded by the dam, the serial chip group includes more than two chip units and a circuit part that realizes the serial connection between adjacent chip units of the same serial chip group, wherein a first isolation part is arranged between adjacent chip units of the same serial chip group to separate adjacent chip units, each of the first isolation parts is provided with a groove part, and the circuit part between adjacent chip units is passed through the groove part; at least one signal transmission unit, comprising an input electrode and an output electrode, one end of the series-connected chipset being electrically connected to the input electrode, and the other end of the series-connected chipset being electrically connected to the output electrode; The optical part is arranged at an end of the dam away from the substrate.

2. The light emitting device according to claim 1, characterized in that: For the series chip group disposed adjacent to the dam, the groove portion on the first isolation portion is disposed at an end of the first isolation portion close to the dam.

3. The light emitting device according to claim 1 or 2, characterized in that: The first isolation portion extends from the substrate toward the optical portion, and one end of the first isolation portion away from the substrate is connected to the optical portion.

4. The light emitting device according to claim 3, characterized in that: The optical part comprises: a first lens, wherein the first lens is located at an end of the dam away from the substrate, an edge of the first lens is connected to the dam, and an end of the first isolation portion away from the substrate is opposite to a surface of the first lens and connected to the first lens; or The fly-eye lens array comprises a plurality of second lenses arranged in an array, wherein the second lenses are arranged on a side of the chip unit facing away from the substrate, and the dam and the first isolation portion are respectively connected to the second lenses.

5. The light emitting device according to claim 1 or 2, characterized in that: The light emitting device comprises more than two series-connected chip groups, wherein a second isolation portion is disposed between any adjacent series-connected chip groups to separate the chip units of the adjacent series-connected chip groups.

6. The light emitting device according to claim 5, characterized in that: The second isolation portion extends from the substrate toward the optical portion, and one end of the second isolation portion away from the substrate is connected to the optical portion.

7. The light emitting device according to claim 5, characterized in that: The dam is integrally formed with the first isolation portion; and / or The dam and the second isolation portion are integrally formed.

8. The light emitting device according to claim 5, characterized in that: A side surface of one or more of the dam, the first isolation portion, and the second isolation portion is configured as a vertical or inclined reflection surface relative to the substrate.

9. The light emitting device according to claim 1 or 2, characterized in that: The serial chipset is arranged on one side of the substrate along the wall thickness direction, a heat dissipation pad is arranged on the side of the substrate facing away from the serial chipset, and one or more chip units of the serial chipset are correspondingly connected to the heat dissipation pad along the wall thickness direction of the substrate.

10. The light emitting device according to claim 9, characterized in that: The input electrode and the output electrode are both arranged on a side of the substrate facing away from the series chipset, and the input electrode and the output electrode are distributed around the heat dissipation pad and are spaced apart from the heat dissipation pad.

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