Light-emitting driving circuit and display panel

Abstract

The utility model discloses a light-emitting driving circuit and a display panel, the light-emitting driving circuit comprises a plurality of shift registers, the nth-level shift register comprises a first pull-up control transistor, a pull-up transistor, a first pull-down control transistor and a pull-down transistor, the first pole of the first pull-up control transistor is connected with a ground wire, and the second pole of the first pull-down control transistor is connected with a ground wire; the first pull-up control transistor and the first pull-down control transistor transmit zero potential signals in a ground wire to control the pull-up transistor and the pull-down transistor to provide corresponding high potential and low potential for the nth-level light-emitting control line respectively, so that nth-level light-emitting control signals are stably output. Compared with the mode of controlling the conduction of the pull-up transistor and the pull-down transistor by adopting high potential, the power consumption is reduced; compared with the mode that a large capacitor is adopted to stably output the nth-stage light-emitting control signal, the nth-stage light-emitting control signal can be stably output even if the large capacitor is not adopted, and therefore the frame occupied space needed by the large capacitor is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a light-emitting driving circuit and a display panel. Background Art

[0002] As people's tastes improve, higher requirements are placed on panel specifications, such as high refresh rate, high resolution, and long life. Compared with the use of flip film fixed gate driver chip (Gate COF), array substrate row driver (GOA) technology has great advantages in cost and functionality, so it has become the focus of panel development.

[0003] In a self-luminous display panel, a scanning driving circuit is usually required to provide a corresponding compensation driving signal, a scanning driving signal, and an initialization control signal, and a light-emitting driving circuit is generally required to provide a corresponding light-emitting control signal to jointly drive a pixel circuit.

[0004] However, the light-emitting driving circuit has long occupied a large frame space, and therefore, the frame needs to be continuously narrowed. Utility Model Content

[0005] The present application provides a light-emitting driving circuit and a display panel to alleviate the technical problems of high power consumption and large frame space occupation.

[0006] In a first aspect, the present application provides a light-emitting drive circuit, which includes a plurality of shift registers, wherein the nth stage shift register includes a first pull-up control transistor, a pull-up transistor, a first pull-down control transistor and a pull-down transistor, the first electrode of the first pull-up control transistor is connected to a ground line, the gate of the first pull-up control transistor is connected to an n-1th stage light-emitting control line, and the first pull-up control transistor is an N-channel transistor; the gate of the pull-up transistor is connected to a second electrode of the first pull-up control transistor, the first electrode of the pull-up transistor is connected to a first high potential line, the second electrode of the pull-up transistor is connected to the nth stage light-emitting control line, and the pull-up transistor is a P-channel transistor; the first electrode of the first pull-down control transistor is connected to a ground line, the gate of the first pull-down control transistor is connected to an nxth stage scanning drive line, the first pull-down control transistor is an N-channel transistor, and x is an integer greater than or equal to 1; the gate of the pull-down transistor is connected to the second electrode of the first pull-down control transistor, the first electrode of the pull-down transistor is connected to a first low potential line, the second electrode of the pull-down transistor is connected to the nth stage light-emitting control line, and the pull-down transistor is an N-channel transistor; wherein the potential of the ground line is higher than the potential of the first low potential line.

[0007] In some embodiments, the nth-stage shift register further includes a second pull-up control transistor and a second pull-down control transistor, the first electrode of the second pull-up control transistor being connected to the second high potential line, the gate of the second pull-up control transistor being connected to the nx-1th-stage scan drive line, the second electrode of the second pull-up control transistor being connected to the gate of the pull-up transistor, and the second pull-up control transistor being an N-channel transistor; the first electrode of the second pull-down control transistor being connected to the second low potential line, the gate of the second pull-down control transistor being connected to the n+1th-stage scan drive line, the second electrode of the second pull-down control transistor being connected to the gate of the pull-down transistor, and the second pull-down control transistor being an N-channel transistor.

[0008] In some embodiments, the potential of the second high potential line is higher than that of the first high potential line, and the potential of the second low potential line is lower than that of the first low potential line.

[0009] In some embodiments, the n-th level shift register also includes a first transistor, a second transistor, a third transistor and a fourth transistor, the first electrode of the first transistor is connected to the third high potential line, the gate of the first transistor is connected to the nx-th level scan drive line, and the first transistor is an N-channel transistor; the first electrode of the second transistor is connected to the third low potential line, the gate of the second transistor is connected to the n+1-th level scan drive line, and the second transistor is an N-channel transistor; the gate of the third transistor is connected to the second electrode of the first transistor and the second electrode of the second transistor, the first electrode of the third transistor is connected to the gate of the pull-up transistor, and the third transistor is an N-channel transistor; the first electrode of the fourth transistor is connected to the second electrode of the third transistor, the gate of the fourth transistor is connected to the second electrode of the first pull-down control transistor, the second electrode of the fourth transistor is connected to the second high potential line, and the fourth transistor is a P-channel transistor.

[0010] In some embodiments, the potential of the third high potential line is higher than that of the second high potential line, and the potential of the third low potential line is lower than that of the second low potential line.

[0011] In some embodiments, the n-th stage shift register also includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, the first electrode of the fifth transistor is connected to the third high potential line, the gate of the fifth transistor is connected to the first clock line, and the fifth transistor is an N-channel transistor; the first electrode of the sixth transistor is connected to the third low potential line, the gate of the sixth transistor is connected to the second clock line, and the sixth transistor is an N-channel transistor; the gate of the seventh transistor is connected to the second electrode of the fifth transistor and the second electrode of the sixth transistor, the first electrode of the seventh transistor is connected to the second low potential line, and the seventh transistor is an N-channel transistor; the first electrode of the eighth transistor is connected to the second electrode of the seventh transistor, the second electrode of the eighth transistor is connected to the gate of the pull-down transistor, the gate of the eighth transistor is connected to the gate of the pull-up transistor, and the eighth transistor is an N-channel transistor.

[0012] In some embodiments, the first clock line is used to transmit a first clock signal, and the second clock line is used to transmit a second clock signal. When the first clock signal is at a low potential, the second clock signal is at a high potential; and when the first clock signal is at a high potential, the second clock signal is at a low potential.

[0013] In some implementations, the high potential of the first clock signal and the high potential of the second clock signal are both the potentials of the third high potential line; the low potential of the first clock signal and the low potential of the second clock signal are both the potentials of the third low potential line.

[0014] In some implementations, in one frame, the pulse in the nx-1th scan driving line is earlier than the pulse in the nxth scan driving line, and the pulse in the nxth scan driving line is earlier than the pulse in the n+1th scan driving line.

[0015] In a second aspect, the present application provides a display panel, which includes the above-mentioned light-emitting driving circuit.

[0016] The light-emitting drive circuit and display panel provided by the present application control the pull-up transistor and the pull-down transistor to provide corresponding high potential and low potential for the n-th level light-emitting control line respectively through the zero potential signal in the transmission ground line of the first pull-up control transistor and the first pull-down control transistor, thereby stably outputting the n-th level light-emitting control signal, which saves power consumption compared to using a high potential to control the conduction of the pull-up transistor and the pull-down transistor; compared to using a large capacitor to stably output the n-th level light-emitting control signal, the present application can stably output the n-th level light-emitting control signal even without using a large capacitor, which reduces the frame space required by the large capacitor; and the first pull-up control transistor and the first pull-down control transistor can also share the same ground line, which reduces the number of transmission lines required for the light-emitting drive circuit and further reduces the frame space. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0018] Figure 1 It is a structural schematic diagram of a light-emitting driving circuit in the related art.

[0019] Figure 2 for Figure 1 Schematic diagram of the waveform of the nth level light-emitting control signal output by the light-emitting driving circuit.

[0020] Figure 3 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0021] Figure 4 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application.

[0022] Figure 5 A schematic diagram of the cascade structure of the light-emitting driving circuit provided in an embodiment of the present application.

[0023] Figure 6 A schematic diagram of the structure of a light-emitting driving circuit provided in an embodiment of the present application.

[0024] Figure 7 for Figure 6 The timing diagram of the light-emitting driving circuit shown.

[0025] Figure 8 for Figure 6 The schematic diagram of the light-emitting driving circuit shown is a schematic diagram of cyclic use of a clock signal. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0027] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. The features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present utility model, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0028] Figure 1The schematic diagram of the structure of the light-emitting driving circuit in the related art is shown in FIG. In a shift register of the light-emitting driving circuit, the first electrode of the first thin-film transistor T11A is connected to the first low-frequency control line, the second electrode of the first thin-film transistor T11A is connected to the first pull-up node Q1[n], and the gate of the first thin-film transistor T11A is connected to the n+3-th level scanning driving line.

[0029] The first low-frequency control line is used to transmit the first low-frequency control signal LC1. The n+3rd level scan driving line is used to transmit the n+3rd level scan driving signal Scan[n+3].

[0030] A gate of the second thin film transistor T21A is connected to the first pull-up node Q1[n], a first electrode of the second thin film transistor T21A is connected to the high potential line, and a second electrode of the second thin film transistor T21A is connected to the n-th level light emitting control line.

[0031] The high potential line is used to transmit the high potential signal VGH. The n-th level light emitting control line is used to transmit the n-th level light emitting control signal EM[n].

[0032] One end of the first capacitor C1 is connected to the gate of the second thin film transistor T21A, and the other end of the first capacitor C1 is connected to the second electrode of the second thin film transistor T21A.

[0033] A first electrode of the pull-down transistor T31 is connected to the n-th stage light emitting control line, a second electrode of the pull-down transistor T31 is connected to the second low potential line, and a gate of the pull-down transistor T31 is connected to the pull-down node QB[n].

[0034] The second low potential line is used to transmit a second low potential signal VGL2.

[0035] A first electrode of the third thin film transistor T51A is connected to the pull-down node QB[n], a second electrode of the third thin film transistor T51A is connected to the first low potential line, and a gate of the third thin film transistor T51A is connected to the first pull-up node Q1[n].

[0036] The first low potential line is used to transmit a first low potential signal VGL1 .

[0037] A first electrode of the fourth thin film transistor T12 is connected to the pull-down node QB[n], a second electrode of the fourth thin film transistor T12 is connected to the first low potential line, and a gate of the fourth thin film transistor T12 is connected to the n+3th level scanning driving line.

[0038] A first electrode of the fifth thin film transistor T13 is connected to the pull-down node QB[n], and a second electrode of the fourth thin film transistor T12 is connected to a gate of the fourth thin film transistor T12 and the n+4th level scanning driving line.

[0039] The n+4th level scan driving line is used to transmit the n+4th level scan driving signal Scan[n+4].

[0040] A first electrode of the sixth thin film transistor T61_1A is connected to the high potential line, a second electrode of the sixth thin film transistor T61_1A is connected to a first electrode of the seventh thin film transistor T61_2A, a second electrode of the seventh thin film transistor T61_2A is connected to the first node N1[n], and a first pull-up node Q1[n] is connected to the gate of the sixth thin film transistor T61_1A and the gate of the seventh thin film transistor T61_2A.

[0041] The first electrode of the eighth thin film transistor T41A is connected to the first pull-up node Q1[n], the second electrode of the eighth thin film transistor T41A is connected to the first electrode of the ninth thin film transistor T42A and the first node N1[n], the second electrode of the ninth thin film transistor T42A is connected to the first low potential line, and the pull-down node QB[n] is connected to the gate of the eighth thin film transistor T41A and the gate of the ninth thin film transistor T42A.

[0042] A first electrode of the tenth thin film transistor T11B is connected to the second low frequency control line, a second electrode of the tenth thin film transistor T11B is connected to the second pull-up node Q2[n], and a gate of the tenth thin film transistor T11B is connected to the n+3th level scanning driving line.

[0043] The second low-frequency control line is used to transmit a second low-frequency control signal LC2.

[0044] A gate of the eleventh thin film transistor T21B is connected to the second pull-up node Q2[n], a first electrode of the eleventh thin film transistor T21B is connected to the high potential line, and a second electrode of the eleventh thin film transistor T21B is connected to the n-th level light emitting control line.

[0045] One end of the second capacitor C2 is connected to the gate of the eleventh thin film transistor T21B, and the other end of the second capacitor C2 is connected to the second electrode of the eleventh thin film transistor T21B.

[0046] A first electrode of the twelfth thin film transistor T51B is connected to the pull-down node QB[n], a second electrode of the twelfth thin film transistor T51B is connected to the first low potential line, and a gate of the twelfth thin film transistor T51B is connected to the second pull-up node Q2[n].

[0047] A first electrode of the thirteenth thin film transistor T61_1B is connected to the high potential line, a second electrode of the thirteenth thin film transistor T61_1B is connected to a first electrode of the fourteenth thin film transistor T61_2B, a second electrode of the fourteenth thin film transistor T61_2B is connected to a second node N2[n], and a second pull-up node Q2[n] is connected to a gate of the thirteenth thin film transistor T61_1B and a gate of the fourteenth thin film transistor T61_2B.

[0048] The first electrode of the fifteenth thin film transistor T41B is connected to the second pull-up node Q2[n], the second electrode of the fifteenth thin film transistor T41B is connected to the first electrode of the sixteenth thin film transistor T42B and the second node N2[n], the second electrode of the sixteenth thin film transistor T42B is connected to the first low potential line, and the pull-down node QB[n] is connected to the gate of the fifteenth thin film transistor T41B and the gate of the sixteenth thin film transistor T42B.

[0049] It should be noted that the above-mentioned thin film transistors are all N-channel thin film transistors. Among them, the above-mentioned shift register has the following problems:

[0050] 1. In order to prevent the negative drift of the threshold voltage of the transistor, it is necessary to design an anti-negative drift structure, such as the sixth thin film transistor T61_1A and the seventh thin film transistor T61_2A, the thirteenth thin film transistor T61_1B and the fourteenth thin film transistor T61_2B, the eighth thin film transistor T41A and the ninth thin film transistor T42A, the fifteenth thin film transistor T41B and the sixteenth thin film transistor T42B, which increases the number of transistors used, thereby not only increasing the design difficulty of the light emitting drive circuit, but also increasing the space occupied by the frame.

[0051] 2. A first capacitor C1 and a second capacitor C2 with larger areas are required to stably output the n-th level light emitting control signal EM[n], which increases the space occupied by the frame of the light emitting driving circuit.

[0052] 3. Due to Figure 2 The duration of the high potential of the n-th level light-emitting control signal EM[n] in a frame is much longer than the duration of its low potential in a frame, which requires the N-channel second thin film transistor T21A and the eleventh thin film transistor T21B to be turned on for a long time. Since their conduction requires long-term power supply with high potential, this also increases power consumption.

[0053] Figure 3 The structure diagram of the display panel provided in the embodiment of the present application is as follows: The display panel comprises a scan driving circuit 100, a light emitting driving circuit 200, a timing controller 300, a data driver 400 and a pixel unit 500.

[0054] The pixel unit 500 includes a plurality of pixel circuits 510 distributed in an array. The timing controller 300 can generate a scan drive control signal SCS, a data drive control signal DCS and a source drive signal DS based on an externally provided synchronization signal. The data driver 400 can generate corresponding data signals D1, D2...Dm according to the source drive signal DS, and transmit them to the corresponding pixel circuit 510. The scan drive circuit 100 can generate corresponding compensation drive signals REF[1]...REF[n], scan drive signals Scan[1]...Scan[n], and initialization control signals INI[1]...INI[n] to the corresponding pixel circuit 510 based on the scan drive control signal SCS. The light emitting drive circuit 200 can generate corresponding light emitting control signals EM[1]...EM[n] to the corresponding pixel circuit 510 based on the scan drive control signal SCS.

[0055] The pixel circuit 510 may be a 4T1C or 5T1C pixel circuit. Figure 4 As shown, the pixel circuit 510 includes a driving transistor T1, a writing transistor T2, a compensation transistor T3, an initialization transistor T4, a light emitting control transistor T5, a storage capacitor Cst and a light emitting device OLED.

[0056] The first electrode of the light-emitting control transistor T5 is connected to the first power supply signal VDD, the second electrode of the light-emitting control transistor T5 is connected to the first electrode of the driving transistor T1, and the gate of the light-emitting control transistor T5 is connected to the n-th level light-emitting control signal EM[n]. The second electrode of the driving transistor T1 is connected to the anode of the light-emitting device OLED, the first electrode of the initialization transistor T4 and one end of the storage capacitor Cst, the cathode of the light-emitting device OLED is connected to the second power supply signal VSS, the second electrode of the initialization transistor T4 is connected to the initialization signal Vini, and the gate of the initialization transistor T4 is connected to the n-th level initialization control signal INI[n]. The other end of the storage capacitor Cst is connected to the gate of the driving transistor T1, the first electrode of the write transistor T2, and the first electrode of the compensation transistor T3, the second electrode of the write transistor T2 is connected to the data signal Vdata (one of D1, D2...Dm), and the gate of the write transistor T2 is connected to the n-th level scan drive signal Scan[n]. The second electrode of the compensation transistor T3 is connected to the reference voltage signal Vref, and the gate of the compensation transistor T3 is connected to the n-th level compensation drive signal REF[n].

[0057] It should be noted that the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain. For example, when the first electrode is the source, the second electrode may be the drain; or, when the first electrode is the drain, the second electrode may be the source. Vg represents the gate potential of the driving transistor T1. Vs represents the source potential of the driving transistor T1.

[0058] Figure 5 Schematic diagram of the cascade structure of the light-emitting driving circuit 200 provided in an embodiment of the present application. The scanning driving circuit 100 can provide multiple scanning driving signals, such as the nx-1th level scanning driving signal Scan[nx-1], the nxth level scanning driving signal Scan[nx], the n-1th level scanning driving signal Scan[n-1], the nth level scanning driving signal Scan[n], the n+1th level scanning driving signal Scan[n+1], etc.

[0059] The light-emitting driving circuit 200 may include multiple shift registers, for example, an nx-1th shift register 210 for outputting an nx-1th light-emitting control signal EM[nx-1], an nxth shift register 220 for outputting an nxth light-emitting control signal EM[nx], an n-1th shift register 230 for outputting an n-1th light-emitting control signal EM[n-1], an nth shift register 240 for outputting an nth light-emitting control signal EM[n], and an n+1th shift register 250 for outputting an n+1th light-emitting control signal EM[n+1].

[0060] Each shift register is connected to the corresponding first clock signal CK and second clock signal XCK. The nx-1th shift register 210 also generates the nx-1th light emitting control signal EM[nx-1] according to the connected n-2x-2th scan drive signal Scan[n-2x-2], the n-2x-1th scan drive signal Scan[n-2x-1], the nxth scan drive signal Scan[nx] and the nx-2th light emitting control signal EM[nx-2].

[0061] The nx-th shift register 220 also generates the nx-th light emitting control signal EM[nx] based on the connected n-2x-1-th scan drive signal Scan[n-2x-1], the n-2x-th scan drive signal Scan[n-2x], the n-x+1-th scan drive signal Scan[n-x+1] and the nx-1-th light emitting control signal EM[nx-1].

[0062] The n-1th level shift register 230 also generates the n-1th level light emitting control signal EM[n-1] according to the connected nx-2th level scan drive signal Scan[nx-2], the nx-1th level scan drive signal Scan[nx-1], the nth level scan drive signal Scan[n] and the n-2th level light emitting control signal EM[n-2].

[0063] The nth-stage shift register 240 also generates the nth-stage light-emitting control signal EM[n] according to the connected nx-1th-stage scan drive signal Scan[nx-1], the nxth-stage scan drive signal Scan[nx], the n+1th-stage scan drive signal Scan[n+1] and the n-1th-stage light-emitting control signal EM[n-1].

[0064] The n+1th shift register 250 also generates the n+1th light emitting control signal EM[n+1] according to the connected nxth scan drive signal Scan[nx], the n-x+1th scan drive signal Scan[n-x+1], the n+2th scan drive signal Scan[n+2] and the nth light emitting control signal EM[n]. By analogy, the scan drive circuit 100 can provide the light emitting drive circuit 200 with various required scan drive signals.

[0065] This embodiment provides a light-emitting driving circuit 200, which includes a plurality of shift registers. Figures 3 to 8 , wherein the n-th stage shift register 240 includes a first pull-up control transistor T11, a pull-up transistor T21, a first pull-down control transistor T41 and a pull-down transistor T31, the first electrode of the first pull-up control transistor T11 is connected to the ground line, the gate of the first pull-up control transistor T11 is connected to the n-1-th stage light emitting control line, and the first pull-up control transistor T11 is an N-channel transistor; the gate of the pull-up transistor T21 is connected to the second electrode of the first pull-up control transistor T11, the first electrode of the pull-up transistor T21 is connected to the first high potential line, the second electrode of the pull-up transistor T21 is connected to the n-1-th stage light emitting control line, and the pull-up transistor T21 is connected to the first high potential line. The transistor T21 is a P-channel transistor; the first electrode of the first pull-down control transistor T41 is connected to the ground line, the gate of the first pull-down control transistor T41 is connected to the nx-th level scanning drive line, the first pull-down control transistor T41 is an N-channel transistor, and x is an integer greater than or equal to 1; the gate of the pull-down transistor T31 is connected to the second electrode of the first pull-down control transistor T41, the first electrode of the pull-down transistor T31 is connected to the first low-potential line, the second electrode of the pull-down transistor T31 is connected to the n-th level light-emitting control line, and the pull-down transistor T31 is an N-channel transistor; wherein the potential of the ground line is higher than the potential of the first low-potential line.

[0066] It can be understood that the light-emitting driving circuit 200 and the display panel provided in the present embodiment control the pull-up transistor T21 and the pull-down transistor T31 to respectively provide corresponding high potential and low potential for the n-th level light-emitting control line through the zero potential signal GND in the transmission ground line of the first pull-up control transistor T11 and the first pull-down control transistor T41, thereby stably outputting the n-th level light-emitting control signal EM[n]. Compared with using a high potential to control the conduction of the pull-up transistor T21 and the pull-down transistor T31, power consumption is saved; compared with using a large capacitor to stably output the n-th level light-emitting control signal EM[n], the present application can stably output the n-th level light-emitting control signal EM[n] even if a large capacitor is not used, which reduces the frame space required by the large capacitor; in addition, the first pull-up control transistor T11 and the first pull-down control transistor T41 can also share the same ground line, which reduces the number of transmission lines required for the light-emitting driving circuit 200 and further reduces the frame space.

[0067] It should be noted that the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain. For example, when the first electrode is the source, the second electrode is the drain; or when the first electrode is the drain, the second electrode is the source.

[0068] The ground line is used to transmit a zero potential signal GND connected to the ground. The n-1th level light emitting control line is used to transmit the n-1th level light emitting control signal EM[n-1]. The nxth level scan drive line is used to transmit the nxth level scan drive signal Scan[nx]. The nth level light emitting control line is used to transmit the nth level light emitting control signal EM[n]. The first low potential line is used to transmit the first low potential signal VGL1. The potential of the zero potential signal GND is higher than the potential of the first low potential signal VGL1.

[0069] In one embodiment, the n-th stage shift register 240 further includes a second pull-up control transistor T52 and a second pull-down control transistor T51, wherein the first electrode of the second pull-up control transistor T52 is connected to the second high potential line, the gate of the second pull-up control transistor T52 is connected to the nx-1-th stage scan drive line, the second electrode of the second pull-up control transistor T52 is connected to the gate of the pull-up transistor T21, and the second pull-up control transistor T52 is an N-channel transistor; the first electrode of the second pull-down control transistor T51 is connected to the second low potential line, the gate of the second pull-down control transistor T51 is connected to the n+1-th stage scan drive line, the second electrode of the second pull-down control transistor T51 is connected to the gate of the pull-down transistor T31, and the second pull-down control transistor T51 is an N-channel transistor.

[0070] It should be noted that the second high potential line is used to transmit the second high potential signal VGH2. The potential of the second high potential signal VGH2 is higher than the potential of the first high potential signal VGH1, which can make the pull-up transistor T21 shut down more thoroughly or completely. The second low potential line is used to transmit the second low potential signal VGL2. The potential of the second low potential signal VGL2 is lower than the potential of the first low potential signal VGL1, which can make the pull-down transistor T31 shut down more thoroughly or completely, thereby eliminating the need for Figure 1 The anti-negative drift structure required.

[0071] The nx-1th scan driving line is used to transmit the nx-1th scan driving signal Scan[nx-1], and the n+1th scan driving line is used to transmit the n+1th scan driving signal Scan[n+1].

[0072] In one embodiment, the n-th stage shift register 240 further includes a first transistor T61, a second transistor T62, a third transistor T43 and a fourth transistor T42, wherein a first electrode of the first transistor T61 is connected to the third high potential line, a gate of the first transistor T61 is connected to the nx-th stage scan drive line, and the first transistor T61 is an N-channel transistor; a first electrode of the second transistor T62 is connected to the third low potential line, a gate of the second transistor T62 is connected to the n+1-th stage scan drive line, and the second transistor T62 is an N-channel transistor; a gate of the third transistor T43 is connected to the second electrode of the first transistor T61 and the second electrode of the second transistor T62, a first electrode of the third transistor T43 is connected to the gate of the pull-up transistor T21, and the third transistor T43 is an N-channel transistor; a first electrode of the fourth transistor T42 is connected to the second electrode of the third transistor T43, a gate of the fourth transistor T42 is connected to the second electrode of the first pull-down control transistor T41, a second electrode of the fourth transistor T42 is connected to the second high potential line, and the fourth transistor T42 is a P-channel transistor.

[0073] It should be noted that the third high potential line is used to transmit a third high potential signal VGH3. The potential of the third high potential signal VGH3 is higher than that of the second high potential signal VGH2, which can make the third transistor T43 turn off more thoroughly or completely. The third low potential line is used to transmit a third low potential signal VGL3.

[0074] In one embodiment, the n-th stage shift register 240 further includes a fifth transistor T63, a sixth transistor T64, a seventh transistor T44 and an eighth transistor T45, wherein a first electrode of the fifth transistor T63 is connected to the third high potential line, a gate of the fifth transistor T63 is connected to the first clock line, and the fifth transistor T63 is an N-channel transistor; a first electrode of the sixth transistor T64 is connected to the third low potential line, a gate of the sixth transistor T64 is connected to the second clock line, and the sixth transistor T64 is an N-channel transistor; a gate of the seventh transistor T44 is connected to the second electrode of the fifth transistor T63 and the second electrode of the sixth transistor T64, a first electrode of the seventh transistor T44 is connected to the second low potential line, and the seventh transistor T44 is an N-channel transistor; a first electrode of the eighth transistor T45 is connected to the second electrode of the seventh transistor T44, a second electrode of the eighth transistor T45 is connected to the gate of the pull-down transistor T31, a gate of the eighth transistor T45 is connected to the gate of the pull-up transistor T21, and the eighth transistor T45 is an N-channel transistor.

[0075] It should be noted that the first clock line is used to transmit the first clock signal CK. The second clock line is used to transmit the second clock signal XCK. When the first clock signal CK is at a low potential, the second clock signal XCK is at a high potential; and when the first clock signal CK is at a high potential, the second clock signal XCK is at a low potential. Each of the fifth transistor T63, the sixth transistor T64, and the seventh transistor T44 can be turned on alternately more frequently, so that the gate thereof can be improved from being subjected to the same high potential or low potential for a long time, thereby improving the drift amplitude of the threshold voltage.

[0076] The potential of the third low potential signal VGL3 is lower than the potential of the second low potential signal VGL2 , so that the seventh transistor T44 can be turned off more thoroughly or completely.

[0077] Exemplarily, the high potential of the first clock signal CK and the high potential of the second clock signal XCK are both the potential of the third high potential signal VGH3; the low potential of the first clock signal CK and the low potential of the second clock signal XCK are both the potential of the third low potential signal VGL3.

[0078] It should be noted that in Figure 6 In the embodiment, the N-channel transistor may be a low-temperature polysilicon thin film transistor or an indium gallium zinc oxide thin film transistor. The P-channel transistor may be a low-temperature polysilicon thin film transistor, which can still have a higher mobility when its channel width is reduced, and can output the n-th level light emitting control signal EM[n] faster.

[0079] Figure 6 The timing sequence of the nth stage shift register 240 is shown as Figure 7 As shown below:

[0080] When the nx-1th level scan drive signal Scan[nx-1] is at a high potential, the second pull-up control transistor T52 is turned on, the potential of the pull-up node Q[n] is switched from the potential of the zero potential signal GND to the potential of the second high potential signal VGH2, the pull-up transistor T21 is turned off, and the eighth transistor T45 is turned on; the n-1th level light emitting control signal EM[n-1] is at a low potential, the first pull-up control transistor T11; the first clock signal CK is at a low potential, and the fifth transistor T63 is turned off; the second clock signal XCK is at a high potential, the sixth transistor T64 is turned on, and then the seventh transistor T44 is turned off.

[0081] Next, when the nx-th level scan drive signal Scan[nx] is at a high potential, the first pull-down control transistor T41 and the first transistor T61 are both turned on, and the pull-down node QB[n] is at the potential of the zero potential signal GND, so that the pull-down transistor T31 is turned on, and the pull-down transistor T31 outputs the first low potential signal VGL1 as the low potential n-th level light-emitting control signal EM[n]; since the gate of the third transistor T43 is connected to the potential of the third high potential signal VGH3, the third transistor T43 is turned on, and then the potential of the pull-up node Q[n] is maintained at the potential of the second high potential signal VGH2, and the pull-up transistor T21 is turned off.

[0082] The nth level light emitting control signal EM[n] continuously outputs a low potential until the low potential ends after a duration of xH, where 1H=1 / F / P, F is the refresh frequency of the display panel, and P is the number of rows of sub-pixels or pixel circuits in the display panel.

[0083] Then, after the n-1th level light emitting control signal EM[n-1] is switched to a high potential, the potential of the pull-up node Q[n] becomes the potential of the zero potential signal GND, the pull-up transistor T21 is turned on, and starts to output the first high potential signal VGH1 as the high potential nth level light emitting control signal EM[n]; the n+1th level scanning drive signal Scan[n+1] is switched to a high potential, the second pull-down control transistor T51 is turned off, the potential of the pull-down node QB[n] becomes the potential of the second low potential signal VGL2, and the pull-down transistor T31 is turned off.

[0084] Among them, although the fourth transistor T42 is turned on under the control of the second low potential signal VGL2, the turning on of the second transistor T62 will turn off the third transistor T43, thereby preventing the potential of the pull-up node Q[n] from being affected by the potential of the pull-down node QB[n].

[0085] Then, the n-1th level light-emitting control signal EM[n-1] continues to be at a high potential in the subsequent time of a frame, the pull-up node Q[n] is at the potential of the zero potential signal GND, and the pull-up transistor T21 continues to be turned on, so that the n-1th level light-emitting control signal also continues to be at a high potential.

[0086] Among them, when the first clock signal CK and the second clock signal XCK alternately turn on the fifth transistor T63 and the sixth transistor T64, the seventh transistor T44 will also be alternately turned on; because the zero potential of the gate of the eighth transistor T45 is higher than the potential of the second potential signal, the eighth transistor T45 will continue to be turned on, so that the second low potential signal VGL2 will intermittently maintain the potential of the pull-down node QB[n] at the potential of the second low potential signal VGL2 through the seventh transistor T44 and the eighth transistor T45.

[0087] from Figure 7 It can be seen that in one frame, the pulse of the nx-1th level scan drive signal Scan[nx-1] is earlier than the pulse of the nxth level scan drive signal Scan[nx], the pulse in the nxth level scan drive line is earlier than the pulse of the nth level scan drive signal, and the pulse of the nth level scan drive signal Scan[n] is earlier than the pulse of the n+1th level scan drive signal Scan[n+1].

[0088] In one embodiment, four different groups of clock lines need to be configured for the above-mentioned light-emitting driving circuit 200, each group of clock lines includes a first clock line and a second clock line. Among them, the first group of clock lines can provide the corresponding first clock signal CK and the second clock signal XCK for the n-1th stage shift register, the n+3th stage shift register, etc., the second group of clock lines can provide the corresponding first clock signal CK (CK1) and the second clock signal XCK (XCK1) for the nth stage shift register 240, the n+4th stage shift register, etc., the third group of clock lines can provide the corresponding first clock signal CK and the second clock signal XCK for the n+1th stage shift register, the n+5th stage shift register, etc., and the fourth group of clock lines can provide the corresponding first clock signal CK and the second clock signal XCK for the n+2th stage shift register, the n+6th stage shift register, etc.

[0089] Among them, the two adjacent shift registers connected to each group of clock lines are connected to the first clock line and the second clock line in opposite directions. For example, taking the second group of clock lines as an example, the gate of the fifth transistor T63 and the gate of the sixth transistor T64 in the n-th stage shift register 240 are connected to the first clock line and the second clock line respectively, and the gate of the fifth transistor T63 and the gate of the sixth transistor T64 in the n+4-th stage shift register are connected to the second clock line and the first clock line respectively.

[0090] The n-1th shift register outputs the n-1th light emitting control signal EM[n-1]. The nth shift register 240 outputs the nth light emitting control signal EM[n]. The n+1th shift register outputs the n+1th light emitting control signal EM[n+1]. The n+2th shift register outputs the n+2th light emitting control signal EM[n+2]. The n+3th shift register outputs the n+3th light emitting control signal EM[n+3].

[0091] In the present application, a high potential can turn on an N-channel transistor and turn off a P-channel transistor; a low potential can turn on a P-channel transistor and turn off an N-channel transistor.

[0092] In one embodiment, the present embodiment provides a display panel, and the display panel includes the above-mentioned light emitting driving circuit 200 .

[0093] It can be understood that since the display panel provided in this embodiment includes the above-mentioned light-emitting driving circuit 200, it can also control the pull-up transistor T21 and the pull-down transistor T31 to provide corresponding high potential and low potential for the n-th level light-emitting control line through the zero potential signal GND in the transmission ground line of the first pull-up control transistor T11 and the first pull-down control transistor T41, thereby stably outputting the n-th level light-emitting control signal EM[n]. Compared with using a high potential to control the conduction of the pull-up transistor T21 and the pull-down transistor T31, power consumption is saved; compared with using a large capacitor to stably output the n-th level light-emitting control signal EM[n], the present application can stably output the n-th level light-emitting control signal EM[n] even if a large capacitor is not used, which reduces the frame space required by the large capacitor; in addition, the first pull-up control transistor T11 and the first pull-down control transistor T41 can also share the same ground line, which reduces the number of transmission lines required for the light-emitting driving circuit 200 and further reduces the frame space.

[0094] Among them, the display panel can be a self-luminous display panel, and the self-luminous display panel can be exemplarily an organic light emitting diode display panel, a micro light emitting diode display panel, a mini light emitting diode display panel or a quantum dot light emitting diode display panel.

[0095] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0096] The light-emitting driving circuit 200 and the display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A light-emitting driving circuit, characterized in that: The light-emitting driving circuit includes a plurality of shift registers, wherein the n-th stage shift register includes: a first pull-up control transistor, wherein a first electrode of the first pull-up control transistor is connected to a ground line, a gate of the first pull-up control transistor is connected to an n-1th level light emitting control line, and the first pull-up control transistor is an N-channel transistor; A pull-up transistor, wherein the gate of the pull-up transistor is connected to the second electrode of the first pull-up control transistor, the first electrode of the pull-up transistor is connected to the first high potential line, the second electrode of the pull-up transistor is connected to the n-th level light emitting control line, and the pull-up transistor is a P-channel transistor; a first pull-down control transistor, wherein a first electrode of the first pull-down control transistor is connected to the ground line, a gate of the first pull-down control transistor is connected to the nx-th level scanning drive line, the first pull-down control transistor is an N-channel transistor, and x is an integer greater than or equal to 1; a pull-down transistor, wherein the gate of the pull-down transistor is connected to the second electrode of the first pull-down control transistor, the first electrode of the pull-down transistor is connected to the first low potential line, the second electrode of the pull-down transistor is connected to the n-th level light emitting control line, and the pull-down transistor is an N-channel transistor; The potential of the ground line is higher than the potential of the first low-potential line.

2. The light-emitting driving circuit according to claim 1, characterized in that: The n-th stage shift register further includes: a second pull-up control transistor, wherein a first electrode of the second pull-up control transistor is connected to a second high potential line, a gate of the second pull-up control transistor is connected to an nx-1-th level scanning drive line, a second electrode of the second pull-up control transistor is connected to the gate of the pull-up transistor, and the second pull-up control transistor is an N-channel transistor; A second pull-down control transistor, wherein the first electrode of the second pull-down control transistor is connected to the second low potential line, the gate of the second pull-down control transistor is connected to the n+1th level scanning drive line, the second electrode of the second pull-down control transistor is connected to the gate of the pull-down transistor, and the second pull-down control transistor is an N-channel transistor.

3. The light-emitting driving circuit according to claim 2, characterized in that: The potential of the second high potential line is higher than that of the first high potential line, and the potential of the second low potential line is lower than that of the first low potential line.

4. The light-emitting driving circuit according to claim 2, characterized in that: The n-th stage shift register further includes: a first transistor, wherein a first electrode of the first transistor is connected to a third high potential line, a gate of the first transistor is connected to the nx-th level scanning drive line, and the first transistor is an N-channel transistor; a second transistor, wherein a first electrode of the second transistor is connected to a third low potential line, a gate of the second transistor is connected to the n+1th level scanning drive line, and the second transistor is an N-channel transistor; a third transistor, wherein a gate of the third transistor is connected to the second electrode of the first transistor and the second electrode of the second transistor, a first electrode of the third transistor is connected to the gate of the pull-up transistor, and the third transistor is an N-channel transistor; A fourth transistor, wherein a first electrode of the fourth transistor is connected to a second electrode of the third transistor, a gate of the fourth transistor is connected to a second electrode of the first pull-down control transistor, a second electrode of the fourth transistor is connected to the second high potential line, and the fourth transistor is a P-channel transistor.

5. The light-emitting driving circuit according to claim 4, characterized in that: The potential of the third high potential line is higher than that of the second high potential line, and the potential of the third low potential line is lower than that of the second low potential line.

6. The light-emitting driving circuit according to claim 4, characterized in that: The n-th stage shift register further includes: a fifth transistor, wherein a first electrode of the fifth transistor is connected to the third high potential line, a gate of the fifth transistor is connected to the first clock line, and the fifth transistor is an N-channel transistor; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the third low potential line, a gate of the sixth transistor is connected to the second clock line, and the sixth transistor is an N-channel transistor; a seventh transistor, wherein a gate of the seventh transistor is connected to the second electrode of the fifth transistor and the second electrode of the sixth transistor, a first electrode of the seventh transistor is connected to the second low potential line, and the seventh transistor is an N-channel transistor; An eighth transistor, wherein a first electrode of the eighth transistor is connected to a second electrode of the seventh transistor, a second electrode of the eighth transistor is connected to a gate of the pull-down transistor, a gate of the eighth transistor is connected to a gate of the pull-up transistor, and the eighth transistor is an N-channel transistor.

7. The light-emitting driving circuit according to claim 6, characterized in that: The first clock line is used to transmit a first clock signal, and the second clock line is used to transmit a second clock signal. When the first clock signal is at a low potential, the second clock signal is at a high potential; and when the first clock signal is at a high potential, the second clock signal is at a low potential.

8. The light-emitting driving circuit according to claim 7, characterized in that: The high potential of the first clock signal and the high potential of the second clock signal are both the potentials of the third high potential line; the low potential of the first clock signal and the low potential of the second clock signal are both the potentials of the third low potential line.

9. The light-emitting driving circuit according to claim 8, characterized in that: In one frame, the pulse in the nx-1th scanning driving line is earlier than the pulse in the nxth scanning driving line, and the pulse in the nxth scanning driving line is earlier than the pulse in the n+1th scanning driving line.

10. A display panel, characterized in that: The display panel comprises the light emitting driving circuit as described in any one of claims 1-9.

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