Digital sounding chip test circuit

Abstract

The utility model discloses a digital sounding chip test circuit, relates to the technical field of digital sounding, and aims to solve the problem that in the prior art, a circuit structure is complex when an electrical test is carried out on a digital sounding chip. The digital sounding chip test circuit comprises a control module, a driving module and a test module. The test module and the driving module are connected with the control module; the driving module is used for driving the digital sounding chip to work; the test module is used for electrically testing the working digital sounding chip and sending test data obtained by the electrical test to the control module; wherein the driving module comprises a preset number of driving circuits; and each driving circuit is connected with at least two sound production channels in the digital sound production chip.

Description

Technical Field

[0001] The utility model relates to the technical field of digital sound generation, and in particular to a digital sound generation chip testing circuit. Background Art

[0002] The digital sound chip is an array sound device composed of multiple pixel units. In the design of a single pixel speaker, many design principles are different from those of traditional speakers. The sound of the digital sound chip is achieved by digital sound reconstruction, so existing technologies such as traditional dynamic iron ring speaker testing solutions are obviously not suitable for digital sound chips.

[0003] Of course, the existing testing schemes for digital sound chips have complex circuit structures. How to simplify the circuit structure when conducting electrical tests on digital sound chips has become an urgent problem to be solved. Utility Model Content

[0004] The utility model aims to provide a digital sound chip test circuit to solve the problem of complex circuit structure when the digital sound chip is electrically tested in the prior art.

[0005] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0006] The utility model provides a digital sound chip test circuit, comprising: a control module, a drive module and a test module;

[0007] The test module and the driving module are both connected to the control module; the driving module includes a preset number of driving circuits; each of the driving circuits is connected to at least two sound channels in the digital sound chip.

[0008] Compared with the prior art, the utility model provides a digital sound chip test circuit, the test circuit includes a control module, a drive module and a test module; the test module and the drive module are both connected to the control module, and the drive module includes a preset number of drive circuits; each drive circuit is connected to at least two sound channels in the digital sound chip, and when testing is required, the control module receives a test instruction sent by a host computer; based on the test instruction, the control module sends a corresponding set of drive control signals to the drive circuit in the drive module, and sends a test control signal to the test module; based on the set of drive control signals, the drive circuit controls the corresponding sound channel in the digital sound chip to work; the test module performs a test based on the test control signal and obtains test data, and sends the test data to the control module, and the control module obtains a test result based on the test data. Since one drive circuit can drive at least two sound channels at the same time, this not only solves the problem of electrical testing of the digital sound chip, but also simplifies the circuit structure of the digital sound chip when performing electrical testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:

[0010] Figure 1 One of the structural schematic diagrams of a digital sound chip test circuit provided by an embodiment of the utility model;

[0011] Figure 2 A second structural diagram of a digital sound chip test circuit provided by an embodiment of the utility model;

[0012] Figure 3 The third structural schematic diagram of the digital sound chip test circuit provided for one embodiment of the utility model.

[0013] Reference numerals:

[0014] 10-digital sound chip test circuit; 20-digital sound chip; 100-control module; 110-FPGA unit; 120-host computer interface; 130-Ethernet transceiver; 140-port expander; 150-SD card; 200-drive module; 300-test module; 400-contact detection module; 500-power module; 510-first boost circuit; 520-second boost circuit; 530-voltage switching circuit; 531-external high-voltage source interface; 532-first relay module; 533-second relay module; 534-second connector; 535-third connector; 536-third indicator light; 537-fourth indicator light. DETAILED DESCRIPTION

[0015] In order to facilitate the clear description of the technical solutions of the embodiments of the present utility model, in the embodiments of the present utility model, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit their order. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit them to be different.

[0016] It should be noted that in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0017] In the present invention, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist.

[0018] like Figure 1 As shown, the embodiment of the utility model provides a digital sound chip test circuit 10, comprising:

[0019] Control module 100, drive module 200 and test module 300;

[0020] The test module 300 and the driving module 200 are both connected to the control module 100; the driving module 200 is used to drive the digital sound chip 20 to work; the test module 300 is used to perform electrical testing on the working digital sound chip 20, and send the test data obtained by the electrical testing to the control module 100;

[0021] The digital sound chip 20 is an array sound device composed of P sound pixel units. From the perspective of the array, the digital sound chip 20 can be divided into multiple sound channels for the P sound pixel units, whether divided by columns or rows. P is a positive integer greater than 2.

[0022] The driving module 200 includes a preset number (eg Figure 1 M) driving circuits in the digital sound chip; each driving circuit is connected to at least two sound channels in the digital sound chip 20.

[0023] For example Figure 1The driving module 200 may include M driving circuits, each driving circuit may drive N sound channels, so the digital sound chip 20 includes M×N sound channels. Wherein, M and N are both positive integers greater than 2.

[0024] For example, a commonly used digital sound chip 20 includes 96 sound channels. Figure 2 Optionally, corresponding to 96 sound channels, each driving circuit can drive two sound channels, such as Figure 2 , the first driving circuit can drive the sound channel T1 and the sound channel T2.

[0025] As mentioned above, the testing scheme of the prior art for speakers such as traditional dynamic iron rings is obviously not suitable for the digital sound chip 20. The digital sound chip test circuit 10 provided in the embodiment of the utility model, when testing is required, the control module 100 receives the test instruction sent by the host computer; based on the test instruction, the control module 100 sends a corresponding set of drive control signals to the drive circuit in the drive module 200, and sends the test control signal to the test module 300; the drive circuit controls the corresponding sound channel in the digital sound chip 20 based on a set of drive control signals; the test module 300 performs testing based on the test control signal and obtains test data, and sends the test data to the control module 100, and the control module 100 obtains the test result according to the test data. Since one drive circuit can drive at least two sound channels at the same time, this not only solves the problem of electrical testing of the digital sound chip 20, but also simplifies the circuit structure of the digital sound chip 20 during electrical testing.

[0026] From the above content, it can be seen that the digital sound chip test circuit 10 is based on the specific circuit structure of the control module 100, the driving module 200 and the testing module 300, generates corresponding driving signals to traverse and drive multiple channels of the digital sound chip 20 to work, and generates corresponding test signals to perform tests, and feeds back the test results to accurately locate the abnormal position and complete the electrical test of the digital sound chip 20.

[0027] Specifically, Figure 2 and Figure 3 As shown, the control module 100 includes an FPGA unit 110, an interaction unit and a host computer interface 120; the interaction unit includes an Ethernet transceiver 130 and a port expander 140;

[0028] The first end of the Ethernet transceiver 130 is connected to the FPGA unit 110, and the second end of the Ethernet transceiver 130 is connected to the host computer interface 120 on the control module 100; the host computer interface 120 can realize the connection between the FPGA unit 110 and the host computer, and further realize the bidirectional data transmission between the FPGA unit 110 and the host computer, so that the host computer can send test instructions to the FPGA unit 110.

[0029] A first end of the port expander 140 is connected to the FPGA unit 110, and a second end of the port expander 140 is connected to the SD card 150. The SD card 150 is used for storing and updating software programs.

[0030] Among them, the FPGA unit 110 includes at least a plurality of signal output terminals of the FPGA units and a plurality of voltage terminals of the FPGA units, and the signal output terminals of the plurality of FPGA units are used to output a variety of control signals such as a drive control signal and a test control signal, so as to realize a variety of functions such as controlling the execution of electrical tests, power switching, and detection data processing and calculation. The specific circuit structure of the FPGA unit 110 can refer to the relevant technology and will not be described here.

[0031] Alternatively, if Figure 2 As shown, the digital sound chip test circuit 10 may further include a contact detection module 400, which is used to detect the connection relationship between the digital sound chip 20 and the driving module 200. This contact detection step is performed before the driving test, mainly to ensure that each pin of the digital sound chip 20 and the driving module 200 are well electrically connected.

[0032] Specifically, the contact detection module 400 may include a first connector, a fourth current limiting resistor R12, a fifth current limiting resistor R13, a sixth current limiting resistor R14, a seventh current limiting resistor R15, a first voltage stabilizer U9, a second voltage stabilizer U10, a first optical coupler K1, a second optical coupler K2, a first indicator LED1, and a second indicator LED2;

[0033] The first connector is connected to the digital sound chip 20;

[0034] The first end of the first indicator LED1 and the first end of the fourth current limiting resistor R12 are both connected to the first end of the first connector; the second end of the first indicator LED1 is connected to the first end of the fifth current limiting resistor R13, and the second end of the fifth current limiting resistor is grounded;

[0035] The second end of the fourth current limiting resistor R12 is connected to the first end of the first voltage regulator U9, and the second end of the first voltage regulator U9 is connected to the first end of the first optical coupler K1; the second end of the first optical coupler K1 is connected to the FPGA unit 110 in the control module 100;

[0036] The first end of the second indicator LED1 and the first end of the sixth current limiting resistor R14 are both connected to the second end of the first connector; the second end of the second indicator LED1 is connected to the first end of the seventh current limiting resistor R15, and the second end of the seventh current limiting resistor R15 is grounded;

[0037] The second end of the sixth current limiting resistor R14 is connected to the first end of the second voltage regulator U10 , and the second end of the second voltage regulator U10 is connected to the first end of the second optical coupler K2 ; the second end of the second optical coupler K2 is connected to the FPGA unit 110 in the control module 100 .

[0038] Among them, the first connector can be a socket or a pin header. The first connector can further establish an electrical connection with the digital sound chip 20 through a male and female socket, a cable, etc. U9 and U10 are used as voltage stabilizers to protect the circuit and avoid overvoltage. K1 and K2 are optical couplers and are control switches of the contact detection module 400. The first indicator LED1 and the second indicator LED2 are used to indicate the connection between the digital sound chip 20 and the digital sound chip test circuit 10. The fourth current limiting resistor R12, the fifth current limiting resistor R13, the sixth current limiting resistor R14 and the seventh current limiting resistor R15 are used to ensure the normal operation of the circuit. The second end of the first optical coupler K1 is connected to the FPGA unit 110 in the control module 100, and the first feedback signal such as FPGA_R2_1 (for example, logic 1) can be sent to the FPGA unit 110; the second end of the second optical coupler K2 is connected to the FPGA unit 110 in the control module 100, and the second feedback signal such as FPGA_R2_32 can be sent to the FPGA unit 110; FPGA_R2_1 and FPGA_R2_32 are used to record the contact state.

[0039] In a specific embodiment, if the digital sound chip 20 establishes a good electrical connection with the digital sound chip test circuit 10, LED1 lights up, and a high level passes through the current limiting resistor R12 to enter U9 for voltage stabilization. After the voltage stabilization is completed, it is input to K1 to drive the optocoupler to work, and the optocoupler outputs a feedback signal FPGA_R2_1 (for example, logic 1) to the FPGA unit 110. The FPGA unit 110 records that the state is 1 when the contact is good at this time; similarly, if the contact is poor, the light goes out, K1 does not work, and the feedback signal FPGA_R2_1 is logic 0.

[0040] In the specific implementation, Figure 3 As shown, the digital sound chip test circuit 10 also includes a power module 500, wherein the power module 500 includes at least a first step-down circuit, a second step-down circuit, a third step-down circuit, a fourth step-down circuit, Figure 3 The first boost circuit 510, the second boost circuit 520 and the voltage switching circuit 530 are shown;

[0041] The voltage output terminal of the first step-down circuit is connected to the voltage terminal of the FPGA unit 110;

[0042] The voltage output end of the second step-down circuit is connected to the voltage end of the test circuit, and the voltage output end of the second step-down circuit is also connected to the voltage end of the contact detection module 400; the voltage output end of the second step-down circuit is also connected to the voltage input end of the third step-down circuit; the voltage output end of the second step-down circuit is also connected to the first voltage end of the port expander 140;

[0043] The voltage output end of the third step-down circuit is connected to the first voltage end of the Ethernet transceiver 130; the voltage output end of the third step-down circuit is also connected to the second voltage end of the port expander 140;

[0044] The voltage output terminal of the fourth step-down circuit is connected to the second voltage terminal of the Ethernet transceiver 130;

[0045] The voltage output end of the first boost circuit 510 and the voltage output end of the second boost circuit 520 are both connected to the voltage switching circuit 530, and the signal input end of the voltage switching circuit 530 is connected to the FPGA unit 110. The FPGA unit 110 sends a first high-voltage control signal or a second high-voltage control signal to the voltage switching circuit 530 to control it to output high, low or 0 voltage.

[0046] Specifically, the voltage input terminal of the power module 500 is connected to the initial input voltage VIN (for example, 12V). The first buck circuit is used to convert the initial input voltage VIN (for example, 12V) into a first buck value V1 (for example, 5V), the second buck circuit is used to convert the initial input voltage VIN into a second buck value V2 (for example, 3.3V), the third buck circuit is used to convert the second buck value V2 into a third buck value V3 (for example, 1.8V), and the fourth buck circuit is used to convert the third buck value V3 into a fourth buck value V4 (for example, 1.2V). For example, the voltage output terminal of the first buck circuit outputs the first buck value V1 (for example, Figure 3 ) is used to power the FPGA unit 110.

[0047] It is understandable that the specific buck circuit structures in the first buck circuit, the second buck circuit, the third buck circuit, and the fourth buck circuit can refer to the relevant technology and will not be described in detail here.

[0048] Specifically, the first boost circuit 510 is used to convert the initial input voltage VIN into a first boost value VH_L, and the second boost circuit 520 is used to convert the initial input voltage VIN into a second boost value VH_H. The second boost value VH_H can be between 30V and 100V, such as 60V.

[0049] Alternatively, if Figure 3As shown, the voltage switching circuit 530 may include an external high voltage source interface 531, a first relay module 532, a second relay module 533, a second connector 534, and a third connector 535;

[0050] The first end of the first relay module 532 is connected to the FPGA unit 110, and the first end of the first relay module 532 receives a first high-voltage control signal sent by the FPGA unit 110;

[0051] The second end of the first relay module 532 is connected to the first end of the second connector 534, the second end of the first relay module 532 and the first end of the second connector 534 are both connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the third indicator light 536, and the second end of the third indicator light 536 is grounded;

[0052] The third end of the first relay module 532 is connected to the first end of the third connector 535, the third end of the first relay module 532 and the first end of the third connector 535 are both connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the fourth indicator light 537, and the second end of the fourth indicator light 537 is grounded;

[0053] The first voltage output terminal and the second voltage output terminal of the first relay module 532 are connected to the driving module 200;

[0054] The first end of the second relay module 533 is connected to the FPGA unit 110, and the first end of the second relay module 533 receives the second high-voltage control signal sent by the FPGA unit 110; the second end of the second relay module 533 is grounded; the voltage output end (for example, output HVDD-0) of the second relay module 533 is connected to the driving module 200;

[0055] The first end of the external high-voltage source interface 531 is connected to the first external high-voltage source; the second end of the external high-voltage source interface 531 is connected to the second external high-voltage source; the third end and the fourth end of the external high-voltage source interface 531 are grounded; the fifth end of the external high-voltage source interface 531 is connected to the second end of the second connector 534; the sixth end of the external high-voltage source interface 531 is connected to the second end of the third connector 535;

[0056] The third end of the second connector 534 is connected to the voltage output end of the first boost circuit 510; the third end of the third connector 535 is connected to the voltage output end of the second boost circuit 520;

[0057] The voltage switching circuit 530 is used to control the high voltage required by the test circuit to be the first boosted value or the second boosted value, or the zero level.

[0058] Specifically, the first relay module 532 ( Figure 3The relay module 1 shown in the figure is used to control the high voltage output of the high voltage output terminal of the power supply module 500 to be a high voltage value VOUTL or a high voltage value VOUTH, and the second relay module 533 ( Figure 3 The relay module 2 shown is used to control the output to be zero level HVDD_0 or ground, and the HVDD_L terminal is electrically connected to the FPGA unit 110 of the control module 100.

[0059] Each of the two relay modules may also include major components such as an optocoupler, a Darlington tube, and a relay. The optocoupler controls the state of the Darlington tube according to the input of the control end, thereby controlling the output voltage corresponding to the relay output.

[0060] The second connector 534 and the third connector 535 are used as connectors to select whether VOUTL and VOUTH are powered by an external high voltage source or powered by the boost circuit. The external high voltage source interface 531 directly inputs VOUTL, VOUTH and ground.

[0061] The third indicator light 536 and the fourth indicator light 537 are both LED lights, used to display the power supply conditions of VOUTL and VOUTH.

[0062] Alternatively, if Figure 2 As shown, the test module 300 may include an analog-to-digital conversion chip U1, a first matching resistor R1, a second matching resistor R2, a third matching resistor R3, a fourth matching resistor R4, a detection resistor R5, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6;

[0063] The first end of the first matching resistor R1 is connected to the first signal output end of the control module 100, and the second end of the first matching resistor R1 is connected to the first end of the analog-to-digital conversion chip U1; the first signal output end of the control module 100 outputs a first test control signal;

[0064] The first end of the second matching resistor R2 is connected to the second signal output end of the control module 100, and the second end of the second matching resistor R2 is connected to the second end of the analog-to-digital conversion chip U1; the second signal output end of the control module 100 outputs a second test control signal;

[0065] The third signal output terminal of the control module 100 and the first end of the second capacitor C1 are both connected to the third end of the analog-to-digital conversion chip U1, and the third signal output terminal of the control module 100 and the first end of the second capacitor C1 are both connected to the fourth end of the analog-to-digital conversion chip U1; the third signal output terminal of the control module 100 outputs a third test control signal;

[0066] The second end of the second capacitor C1 is grounded, and the second end of the second capacitor C1 is also connected to the first end of the second capacitor C2;

[0067] The second end of the second capacitor C2, the first end of the third capacitor C3, and the first end of the third matching resistor R3 are all connected to the fifth end of the analog-to-digital conversion chip U1;

[0068] The second end of the third capacitor C3, the first end of the fourth matching resistor R4, and the first end of the fourth capacitor C4 are all connected to the sixth end of the analog-to-digital conversion chip U1; the second end of the fourth capacitor C4 is grounded;

[0069] The second end of the third matching resistor R3 is connected to the first end of the detection resistor R5; the second end of the third matching resistor R3 is grounded;

[0070] The second end of the fourth matching resistor R4 is connected to the second end of the detection resistor R5; the second end of the detection resistor R5 is connected to the zero level.

[0071] The first power supply terminal and the second power supply terminal of the first switch chip are both connected to the power supply module 500;

[0072] The fifth capacitor C5 and the sixth capacitor C6 are connected in parallel between the power module 500 and the analog-to-digital conversion chip U1 .

[0073] Specifically, the first end of the fifth capacitor C5 is connected to the first end of the sixth capacitor C6, and the first end of the fifth capacitor C5 and the first end of the sixth capacitor C6 are both connected to the negative voltage terminal of the analog-to-digital conversion chip U1; the second end of the fifth capacitor C5 is connected to the second end of the sixth capacitor C6, and the second end of the fifth capacitor C5 and the second end of the sixth capacitor C6 are both connected to the positive voltage terminal of the analog-to-digital conversion chip U1, and the second end of the fifth capacitor C5 and the second end of the sixth capacitor C6 are also connected to the power module 500 for introducing the operating voltage required by the analog-to-digital conversion chip U1.

[0074] Specifically, the analog-to-digital conversion chip U1 is used to collect test data and transmit the data to the control module 100 .

[0075] For example, the first test control signal DOUT, the second test control signal SCLK, and the third test control signal E+ are short-circuit detection control signals, which are electrically connected to the FPGA unit 110 of the control module 100. The first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are filtering and decoupling capacitors, and the first matching resistor R1, the second matching resistor R2, the third matching resistor R3, and the fourth matching resistor R4 are matching resistors, which are used to reduce signal interference and improve signal transmission quality. V2 is the operating voltage of U1; R5 is a detection resistor, one end of which is grounded and the other end is connected to the zero level output by the high-voltage output end of the power module 500.

[0076] Optionally, the resistance of the detection resistor R5 is greater than or equal to a preset resistance value. The preset resistance value corresponds to the current threshold of the test current in the electrical performance test. For the digital sound chip, the utility model sets the current parameter threshold to, for example, 10mA, then the corresponding resistance value of the detection resistor R5 can be 1.8K ohms. In actual testing, if the test current exceeds 10mA, it means that the corresponding sound channel is working abnormally. In this way, the resistance value of the detection resistor R5 is larger than the resistance value in traditional technology. Such a design is related to the circuit properties of the digital sound chip itself, and secondly, it can improve the test sensitivity and accuracy of the digital sound chip test circuit to the digital sound chip. It can be understood that the current parameter threshold is set to 10mA, which is the data obtained by the utility model through creative repeated design and simulation testing of the digital sound chip test circuit based on the characteristics of the digital sound chip.

[0077] Alternatively, if Figure 2 As shown, the driving circuit includes a decoding chip U2 and at least two driving units; the decoding chip is connected to the at least two driving units; each driving unit is connected to a sound channel;

[0078] The decoding chip U2 is also connected to the FPGA unit 110 in the control module 100, and receives at least two groups of driving signals sent by the FPGA unit 110; wherein each group of driving signals corresponds to one driving unit.

[0079] Specifically, Figure 2 As shown, the first driving unit of the two driving units includes a first converter U3, a second converter U4 and a switch chip U5;

[0080] The first input terminal of the first converter U3 is connected to the first signal output terminal of the decoding chip; the first output terminal of the first converter U3 is connected to the first signal input terminal of the switch chip U5;

[0081] The first input terminal of the second converter U4 is connected to the second signal output terminal of the decoding chip, and the second input terminal of the second converter U4 is connected to the third signal output terminal of the decoding chip;

[0082] The first output terminal of the second converter U4 is connected to the second signal input terminal of the switch chip U5, and the second output terminal of the second converter U4 is connected to the third signal input terminal of the switch chip U5;

[0083] The first output end of the switch chip U5 is connected to the first sound channel T1 through the first current limiting resistor R6; the second output end of the switch chip U5 is connected to the first sound channel T1 through the second current limiting resistor R7; the third output end of the switch chip U5 is connected to the first sound channel T1 through the third current limiting resistor R8.

[0084] It is understandable that, for the first driving unit, the first signal input terminal of the U2 decoding chip receives FP1H in the first group of driving control signals sent by the FPGA unit 110, and the second signal input terminal of the U2 decoding chip receives FP1L in the first group of driving control signals sent by the FPGA unit 110. Then, the U2 decoding chip converts the two driving control signals FP1H and FP1L into three driving signals, which are converted by the converter and sent to the switch chip U5. U5 selectively connects one of the three voltage terminals (the first voltage terminal is connected to the high voltage HVDD, the second voltage terminal is suspended, and the third voltage terminal is connected to the 0 level) on the switch chip U5 according to the three driving signals. At the same time, the FPGA unit 110 sends a test control signal to the test module 300 to control the test module 300 to perform the test work.

[0085] The second drive unit of the two drive units includes a converter U6 and a converter U7 and a switch chip U8. The circuit structure of the second drive unit is the same as that of the first drive unit, and the specific connection relationship is not repeated. The switch chip U8 is connected to the second sound channel T2 through three different current limiting resistors. Figure 2 As shown, the circuit structure and connection relationship of other driving circuits in the driving module 200 will not be repeated.

[0086] It is understandable that, for the second driving unit, the third signal input terminal of the U2 decoding chip receives FP2H in the second group of driving control signals sent by the FPGA unit 110, and the fourth signal input terminal of the U2 decoding chip receives FP2L in the second group of driving control signals sent by the FPGA unit 110. Then, the U2 decoding chip converts the two driving control signals FP2H and FP2L into three-way driving signals and sends them to the switch chip U8. U8 selectively connects one of the three voltage terminals (the first voltage terminal is connected to the high voltage HVDD, the second voltage terminal is suspended, and the third voltage terminal is connected to the 0 level) on the switch chip U8 according to the three-way driving signals.

[0087] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other changes to the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other device may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0088] Although the utility model has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the utility model. Accordingly, this specification and the drawings are merely exemplary illustrations of the utility model as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the utility model. Obviously, those skilled in the art may make various modifications and variations to the utility model without departing from the spirit and scope of the utility model. Thus, if these modifications and variations of the utility model fall within the scope of the claims of the utility model and their equivalents, the utility model is also intended to include these modifications and variations.

Claims

1. A digital sound chip test circuit, characterized in that: include: Control module, drive module and test module; The test module and the drive module are both connected to the control module; the drive module is used to drive the digital sound chip to work; the test module is used to perform electrical tests on the working digital sound chip and send the test data obtained by the electrical tests to the control module; Wherein, the driving module includes a preset number of driving circuits; each of the driving circuits is connected to at least two sound channels in the digital sound chip.

2. The digital sound chip test circuit according to claim 1, characterized in that: The test module includes an analog-to-digital conversion chip, a first matching resistor, a second matching resistor, a third matching resistor, a fourth matching resistor, a detection resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor; The first end of the first matching resistor is connected to the first signal output end of the control module, and the second end of the first matching resistor is connected to the first end of the analog-to-digital conversion chip; the first signal output end of the control module outputs a first test control signal; The first end of the second matching resistor is connected to the second signal output end of the control module, and the second end of the second matching resistor is connected to the second end of the analog-to-digital conversion chip; the second signal output end of the control module outputs a second test control signal; The third signal output terminal of the control module and the first end of the first capacitor are both connected to the third end of the analog-to-digital conversion chip, and the third signal output terminal of the control module and the first end of the first capacitor are both connected to the fourth end of the analog-to-digital conversion chip; the third signal output terminal of the control module outputs a third test control signal; The second end of the first capacitor is grounded, and the second end of the first capacitor is also connected to the first end of the second capacitor; The second end of the second capacitor, the first end of the third capacitor, and the first end of the third matching resistor are all connected to the fifth end of the analog-to-digital conversion chip; The second end of the third capacitor, the first end of the fourth matching resistor, and the first end of the fourth capacitor are all connected to the sixth end of the analog-to-digital conversion chip; the second end of the fourth capacitor is grounded; The second end of the third matching resistor is connected to the first end of the detection resistor; the second end of the third matching resistor is grounded; The second end of the fourth matching resistor is connected to the second end of the detection resistor; the second end of the detection resistor is connected to a zero level.

3. The digital sound chip test circuit according to claim 1, characterized in that: The driving circuit includes a decoding chip and at least two driving units; the decoding chip is connected to the at least two driving units; each driving unit is connected to one of the sound channels; The decoding chip is also connected to the control module to receive at least two groups of driving signals sent by the control module; wherein each group of driving signals corresponds to one driving unit.

4. The digital sound chip test circuit according to claim 3, characterized in that: The driving unit includes a first converter, a second converter and a switch chip; The first input terminal of the first converter is connected to the first signal output terminal of the decoding chip; the first output terminal of the first converter is connected to the first signal input terminal of the switch chip; The first input terminal of the second converter is connected to the second signal output terminal of the decoding chip, and the second input terminal of the second converter is connected to the third signal output terminal of the decoding chip; The first output terminal of the second converter is connected to the second signal input terminal of the switch chip, and the second output terminal of the second converter is connected to the third signal input terminal of the switch chip; The first output end of the switch chip is connected to the first sound channel through a first current limiting resistor; the second output end of the switch chip is connected to the first sound channel through a second current limiting resistor; the third output end of the switch chip is connected to the first sound channel through a third current limiting resistor.

5. The digital sound chip test circuit according to claim 4, characterized in that: The control module includes an FPGA unit and an interaction unit; the interaction unit includes an Ethernet transceiver and a port expander; The first end of the Ethernet transceiver is connected to the FPGA unit, and the second end of the Ethernet transceiver is connected to the upper computer interface on the control module; The first end of the port expander is connected to the FPGA unit, and the second end of the port expander is connected to the SD card.

6. The digital sound chip test circuit according to claim 5, characterized in that: It also includes a contact detection module, which detects the connection relationship between the digital sound chip and the driving module.

7. The digital sound chip test circuit according to claim 6, characterized in that: The contact detection module includes a first connector, a fourth current limiting resistor, a fifth current limiting resistor, a sixth current limiting resistor, a seventh current limiting resistor, a first voltage stabilizer, a second voltage stabilizer, a first optical coupler, a second optical coupler, a first indicator light, and a second indicator light; The first connector is connected to the digital sound chip; The first end of the first indicator light and the first end of the fourth current limiting resistor are both connected to the first end of the first connector; the second end of the first indicator light is connected to the first end of the fifth current limiting resistor, and the second end of the fifth current limiting resistor is grounded; The second end of the fourth current limiting resistor is connected to the first end of the first voltage regulator, the second end of the first voltage regulator is connected to the first end of the first optical coupler; the second end of the first optical coupler is connected to the control module; The first end of the second indicator light and the first end of the sixth current limiting resistor are both connected to the second end of the first connector; the second end of the second indicator light is connected to the first end of the seventh current limiting resistor, and the second end of the seventh current limiting resistor is grounded; The second end of the sixth current limiting resistor is connected to the first end of the second voltage regulator, the second end of the second voltage regulator is connected to the first end of the second optocoupler; and the second end of the second optocoupler is connected to the control module.

8. The digital sound chip test circuit according to claim 7, characterized in that: Also includes a power supply module, the power supply module at least includes a first step-down circuit, a second step-down circuit, a third step-down circuit, a fourth step-down circuit, a first step-up circuit, a second step-up circuit and a voltage switching circuit; The voltage output end of the first step-down circuit is connected to the voltage end of the FPGA unit; the voltage output end of the second step-down circuit is connected to the voltage end of the test circuit, and the voltage output end of the second step-down circuit is also connected to the voltage end of the contact detection module; the voltage output end of the second step-down circuit is also connected to the voltage input end of the third step-down circuit; the voltage output end of the second step-down circuit is also connected to the first voltage end of the port expander; The voltage output end of the third step-down circuit is connected to the first voltage end of the Ethernet transceiver; the voltage output end of the third step-down circuit is also connected to the second voltage end of the port expander; The voltage output terminal of the fourth step-down circuit is connected to the second voltage terminal of the Ethernet transceiver; The voltage output end of the first boost circuit and the voltage output end of the second boost circuit are both connected to the voltage switching circuit, and the signal input end of the voltage switching circuit is connected to the FPGA unit.

9. The digital sound chip test circuit according to claim 8, characterized in that: The voltage switching circuit includes an external high voltage source interface, a first relay module, a second relay module, a second connector, and a third connector; The first end of the first relay module is connected to the FPGA unit, and the first end of the first relay module receives a first high-voltage control signal sent by the FPGA unit; The second end of the first relay module is connected to the first end of the second connector, the second end of the first relay module and the first end of the second connector are both connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the third indicator light, and the second end of the third indicator light is grounded; The third end of the first relay module is connected to the first end of the third connector, the third end of the first relay module and the first end of the third connector are both connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the fourth indicator light, and the second end of the fourth indicator light is grounded; The first voltage output terminal and the second voltage output terminal of the first relay module are connected to the driving module; The first end of the second relay module is connected to the FPGA unit, and the first end of the second relay module receives the second high-voltage control signal sent by the FPGA unit; the second end of the second relay module is grounded; and the voltage output end of the second relay module is connected to the driving module; The first end of the external high-voltage source interface is connected to the first external high-voltage source; the second end of the external high-voltage source interface is connected to the second external high-voltage source; the third end and the fourth end of the external high-voltage source interface are grounded; the fifth end of the external high-voltage source interface is connected to the second end of the second connector; the sixth end of the external high-voltage source interface is connected to the second end of the third connector; The third end of the second connector is connected to the voltage output end of the first boost circuit; the third end of the third connector is connected to the voltage output end of the second boost circuit.

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