Fan-out chip packaging structure

Abstract

The utility model discloses a fan-out type chip packaging structure. The fan-out type chip packaging structure comprises a rewiring layer, the performance chip and the component are inversely arranged on one side of the rewiring layer, and the other side of the rewiring layer is soldered with a tin bump; the plastic packaging layer is positioned above the rewiring layer and wraps the performance chip and the component; a metal layer is formed on the back sides of the performance chip and the component to cover the plastic package layer, so that the heat dissipation efficiency is improved; according to the packaging structure, the rewiring layer on which the bumps are soldered can be further mounted on one surface of the substrate, and tin balls are soldered on the other surface of the substrate. According to the fan-out chip packaging structure provided by the utility model, a capacitor or other components are mounted while the performance chip is inversely mounted on the rewiring layer through a surface mounting process, so that a power supply network is stabilized, signal interference between core particles is avoided, the size of the packaging structure is optimized, the design of the back metal layer is added, and the packaging efficiency is improved. The problem of difficulty in heat dissipation is effectively solved, and the design of the packaging structure greatly improves the reliability of the HDFO packaging structure.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, and more specifically to a fan-out chip packaging structure. Background Art

[0002] At present, integrated circuit chips are developing towards large size, high integration, small feature size and high I / O, in order to adapt to the development trend of multifunctional, miniaturized, portable, high speed, low power consumption and high reliability of microelectronic packaging technology. Integrating multiple functional chips and components in one package to achieve a complete function is a new system-level packaging technology with the advantages of short development cycle, multiple functions, low power consumption, excellent performance, low cost, small size and light weight.

[0003] As the integration level is improved by increasing the chip area, the mask limit is constantly challenged. Chiplet technology has been widely valued by the industry and academia due to its unique chip architecture and other excellent features.

[0004] The main feature of chiplet technology is that multiple chips are interconnected through packaging. Traditional packaging technology can no longer meet the needs of chiplet technology development. Advanced packaging technologies such as high-density substrates or adapters, high-pitch and high-density copper pillars, etc. are widely used. The packaging structure has evolved from 2D to 3D packaging, which improves the interconnection density in all dimensions, reduces the interconnection distance, and reduces costs. 2.5D packaging HDFO (high-density fan-out packaging) uses organic RDL (Redistribution layer) to achieve chip-to-chip interconnection, and then integrates the package on the substrate. It has the advantages of low cost, high integration, and high reliability, and has become a preferred choice for chiplet integrated packaging.

[0005] However, with the increase in the density of RDL (redistribution layer) power lines and signal lines and the increase in the number of chips integrated in the RDL terminal, signal interference between the power network and the core particles has become a hidden danger affecting the reliability of the package. At the same time, the package will occupy an increasingly larger area and thickness, which also brings about the problem of difficulty in heat dissipation of the package, which is not conducive to the improvement of integration. Utility Model Content

[0006] In order to solve the above problems, the utility model provides a fan-out chip packaging structure that can stabilize the power supply network and avoid signal interference between core particles, optimize the packaging size, and increase the back metal layer to provide heat dissipation capability.

[0007] According to one aspect of the utility model, a fan-out chip packaging structure is provided, comprising: a redistribution layer, the redistribution layer comprising at least one dielectric layer and at least one metal interconnection layer in the dielectric layer, the surface of the redistribution layer having solder pads; performance chips and components, the performance chips and components are flipped on one side of the redistribution layer and interconnected with the solder pads of the redistribution layer; a plastic encapsulation layer, the plastic encapsulation layer is located above the redistribution layer, and the plastic encapsulation layer wraps the performance chips and components; a metal layer, the metal layer covers the plastic encapsulation layer, the metal layer is located on the back side of the performance chip and the components to improve heat dissipation efficiency; and bumps, the bumps are soldered to the other side of the redistribution layer.

[0008] According to another aspect of the utility model, another fan-out chip packaging structure is provided, including: a redistribution layer, the redistribution layer including at least one dielectric layer and at least one metal interconnection layer located in the dielectric layer, the surface of the redistribution layer having a solder pad; performance chips and components, the performance chips and components are flipped on one side of the redistribution layer and interconnected with the solder pads of the redistribution layer; a plastic encapsulation layer, the plastic encapsulation layer is located above the redistribution layer, and the plastic encapsulation layer wraps the performance chip and components; bumps, the bumps are soldered to the other side of the redistribution layer; a substrate, the redistribution layer with the bumps soldered thereon is mounted on one side of the substrate, and the other side of the substrate is soldered with solder balls.

[0009] In some embodiments, the dielectric layer and the metal interconnection layer of the redistribution layer are a multi-layer structure, and interconnection lines are formed between the metal interconnection layers.

[0010] In some embodiments, the components include one or more of capacitors, resistors, inductors, filters, processors, memories, power amplifiers, radio frequency devices, and switches.

[0011] In some embodiments, the fan-out chip packaging structure further includes a metal layer, which covers the plastic packaging layer and is located on the back side of the performance chip and components to improve heat dissipation efficiency.

[0012] Compared with the prior art, the beneficial effects of the utility model are as follows: the fan-out chip packaging structure provided by the utility model is used to mount capacitors or other components while the performance chip is flipped on the redistribution layer through the surface mounting process, so as to stabilize the power supply network and avoid signal interference between core particles. At the same time, it can solve the problem of difficulty in reducing the packaging volume in the prior art and optimize the size of the packaging structure. In addition, a back metal layer is added to the fan-out packaging structure to effectively solve the problem of heat dissipation difficulties and improve heat dissipation efficiency. The design of the packaging structure improves the reliability of the HDFO (high-density fan-out chip packaging) packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1is a schematic diagram of a preparation process of an implementation method of a performance chip;

[0014] Figure 2 is a schematic diagram of a preparation process of an implementation method of a redistribution layer;

[0015] Figure 3 is a schematic diagram of the packaging process of the chip packaging structure before the metal layer is formed in Example 1;

[0016] Figure 4 is a schematic diagram of the packaging process of the chip packaging structure after the metal layer is formed in Example 1;

[0017] Figure 5 is a structural schematic diagram of embodiment 1 of a fan-out chip packaging structure;

[0018] Figure 6 is a schematic diagram of the packaging process of the chip packaging structure before the carrier wafer is separated in Example 2;

[0019] Figure 7 is a schematic diagram of the packaging process of the chip packaging structure after the carrier wafer is separated in Example 2;

[0020] Figure 8 is a structural schematic diagram of embodiment 2 of a fan-out chip packaging structure;

[0021] Fig. 9 The present invention is a structural schematic diagram of embodiment 3 of a fan-out chip packaging structure. DETAILED DESCRIPTION

[0022] The utility model is further described below in conjunction with specific implementation methods.

[0023] Example 1

[0024] like Figure 5 As shown, a fan-out chip packaging structure according to one embodiment of the utility model includes a redistribution layer 1, a performance chip 2 and components 3. The redistribution layer 1 includes at least one dielectric layer 11, at least one metal interconnection layer 12 located in the dielectric layer 11, and the top surface of the redistribution layer 1 has a pad 10. The performance chip 2 and the component 3 are flipped on one side of the redistribution layer 1, and the performance chip 2 and the component 3 are interconnected with the pad 10 of the redistribution layer 1; the other side of the redistribution layer 1 is soldered with a bump 6. A plastic encapsulation layer 4 is formed above the redistribution layer 1, and the plastic encapsulation layer 4 wraps the performance chip 2 and the component 3. A metal layer 5 is covered on the plastic encapsulation layer 4, and the metal layer 5 is located on the back side of the performance chip 2 and the component 3 to improve the heat dissipation efficiency.

[0025] In practical applications, the dielectric layer 11 and the metal interconnection layer 12 of the redistribution layer 1 may be a multi-layer structure, and interconnection lines, 2P2M, 4P4M, and 6P6M structures are formed between the metal interconnection layers 12 .

[0026] The components 3 include one or more of capacitors, resistors, inductors, filters, processors, memories, power amplifiers, radio frequency devices, and switches.

[0027] Combination Figures 1 to 4 , the packaging process of the fan-out chip packaging structure of this embodiment is specifically described, and the steps are as follows:

[0028] Step 1: Prepare performance chip 2: Figure 1 As shown, a micro bump (micro protrusion 21) is prepared on the reserved I / O interface on the incoming wafer through sputtering, photolithography, and electroplating processes, and the optional bump structure is Cu / Ni / SnAg; then, grinding is used to thin the wafer to meet the packaging thickness requirement, and dicing is used to cut the wafer to form the performance chip 2 to be mounted, providing material preparation for subsequent chip mounting and wafer reconstruction.

[0029] Step 2: Prepare redistribution layer 1: Figure 2 As shown, a carrier wafer (carrier wafer 100), which may be glass, is used to prepare a redistribution layer 1 (RDL) for the carrier, wherein the structure design of the redistribution layer 1 (RDL) may be based on the number of Device die I / Os, and may be a 4P4M structure, with a micro pad (pad 10) provided on the top layer.

[0030] Step 3: Die attach (DA / die attach): Figure 3 As shown in 3A and 3B, the performance chip 2 is precisely mounted to the pad 10 reserved on the redistribution layer 1 (RDL) using surface mount technology (Surface Mount Technology); at the same time, at least one component 3 is mounted to the pad 10 reserved on the redistribution layer 1 (RDL) using surface mount technology; and the bottom of the performance chip 2 and the redistribution layer 1, and the bottom of the component 3 and the redistribution layer 1 are filled with filling glue 9 to make the mounting of the performance chip 2 and the component 3 more stable.

[0031] Step 4: Molding compound: Figure 3 As shown in 3C , the performance chip 2 and the components 3 are plastic-encapsulated for protection, and a plastic-encapsulation layer 4 is formed on the redistribution layer 1 .

[0032] Step 5: Sputtering to form metal layer 5: Using physical vapor deposition process, a layer of metal material with high thermal conductivity, such as copper, is sputtered on the back of the packaging structure to form metal layer 5. Figure 4 As shown in 3D, the heat dissipation efficiency is improved.

[0033] Step 6: Thermal Debonding: Debond the carrier wafer (carrier wafer 100) Figure 4 As shown in Figure 3E.

[0034] Step 7: Solder bump 6: Use chemical plating process to form bump 6, such as Figure 4 As shown in 3F.

[0035] In this embodiment, capacitors or other components 3 are mounted at the same time as the performance chip 2 to stabilize the power supply network and avoid signal interference between core particles. At the same time, it can solve the problem of difficulty in reducing the package volume in the prior art, and add a back metal layer 5 in the fan-out packaging structure to effectively solve the problem of heat dissipation difficulties.

[0036] Example 2

[0037] like Figure 8 As shown, the present embodiment provides a fan-out chip packaging structure, which includes a substrate 7, a redistribution layer 1, a performance chip 2 and components 3. The redistribution layer 1 includes at least one dielectric layer 11, at least one metal interconnection layer 12 located in the dielectric layer 11, and the top surface of the redistribution layer 1 has a solder pad 10. The performance chip 2 and the component 3 are flipped on one side of the redistribution layer 1, and the performance chip 2 and the component 3 are interconnected with the solder pad 10 of the redistribution layer 1, and the other side of the redistribution layer 1 is soldered with a bump 6. A plastic encapsulation layer 4 is formed above the redistribution layer 1, and the plastic encapsulation layer 4 wraps the performance chip 2 and the component 3. The redistribution layer 1 with the soldered bump 6 is mounted on one side of the substrate 7, and the other side of the substrate 7 is soldered with a solder ball 8.

[0038] Combination Figure 1 , 2 , 6 and 7, specifically describe the packaging process of the fan-out chip packaging structure of this embodiment. The packaging structure of this embodiment is a HDFO (high-density fan-out chip packaging) packaging structure. The specific steps are as follows:

[0039] Step 1: Prepare performance chip 2: Figure 1As shown, a micro bump (micro protrusion 21) is prepared on the reserved I / O interface on the incoming wafer through sputtering, photolithography, and electroplating processes, and the optional bump structure is Cu / Ni / SnAg; then, grinding is used to thin the wafer to meet the packaging thickness requirement, and dicing is used to cut the wafer to form the performance chip 2 to be mounted, providing material preparation for subsequent chip mounting and wafer reconstruction.

[0040] Step 2: Prepare redistribution layer 1: Figure 2 As shown, a carrier wafer (carrier wafer 100), which may be glass, is used to prepare a redistribution layer 1 (RDL) for the carrier, wherein the structure design of the redistribution layer 1 (RDL) can be based on the number of Device die I / Os, and can be a 6P6M structure, a 2P2M structure, or a 4P4M structure. A micro pad (solder pad 10) is provided on the top layer of the redistribution layer 1.

[0041] Step 3: Die attach (DA / die attach): Figure 6 As shown in Figures 6A and 6B, the performance chip 2 is precisely mounted to the pad 10 reserved on the redistribution layer 1 (RDL) using surface mount technology; at the same time, at least one component 3 is mounted to the pad 10 reserved on the redistribution layer 1 (RDL) using surface mount technology; and the bottom of the performance chip 2 and the redistribution layer 1, and the bottom of the component 3 and the redistribution layer 1 are filled with filling glue 9 to make the mounting of the performance chip 2 and the component 3 more stable.

[0042] Step 4: Molding compound: Figure 6 As shown in FIG6C , the performance chip 2 and the components 3 are plastic-encapsulated for protection, and a plastic-encapsulation layer 4 is formed on the redistribution layer 1 .

[0043] Step 5: Thermal Debonding: Debond the carrier wafer (carrier wafer 100) Figure 7 As shown in Figure 6D.

[0044] Step 6: Forming bump 6: Using flip chip soldering (4C / Controlled Collapsed Chip Connection), complete the C4 bump process, and form bump 6 on the side of the redistribution layer 1 where the performance chip 2 and the component 3 are not mounted, such as Figure 7 As shown in Figure 6E.

[0045] Step 7: FC (Flip chip): Flip the above-made package onto the substrate 7, and complete the packaging process between the redistribution layer 1 and the substrate 7. The surface where the bump 6 is located and the substrate 7 are bottom-filled with a filling glue 9. The ball planting process is completed on the other side of the substrate 7 to form a solder ball 8. Figure 7 As shown in Figure 6F.

[0046] Example 3

[0047] The main difference between this embodiment 3 and embodiment 2 is that Fig. 9 As shown, in this embodiment, the chip packaging structure is provided with a metal layer 5. A layer of metal material with high thermal conductivity, optionally copper, is sputtered on the back of the packaging structure using a physical vapor deposition process to form a metal layer 5, which covers the plastic packaging layer 4 and is located on the back side of the performance chip 2 and the components 3.

[0048] The fan-out chip packaging structure provided by the utility model is characterized in that the performance chip 2 is flipped on the redistribution layer 1 through the surface mounting process, and capacitors or other components 3 are mounted at the same time, so as to stabilize the power supply network and avoid signal interference between core particles. At the same time, it can solve the problem of difficulty in reducing the package volume in the prior art and optimize the size of the package structure. In addition, a back metal layer 5 is added to the fan-out package structure to effectively solve the problem of heat dissipation difficulties and improve heat dissipation efficiency. The design of this package structure improves the reliability of the HDFO (high-density fan-out chip package) package structure.

[0049] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A fan-out chip packaging structure, comprising: A redistribution layer (1), the redistribution layer (1) comprising at least one dielectric layer (11), at least one metal interconnection layer (12) located in the dielectric layer (11), and a solder pad (10) being provided on a surface of the redistribution layer (1); A performance chip (2) and a component (3), wherein the performance chip (2) and the component (3) are flipped on one side of the redistribution layer (1) and interconnected with the pads (10) of the redistribution layer (1); A plastic encapsulation layer (4), the plastic encapsulation layer (4) being located above the redistribution layer (1), and the plastic encapsulation layer (4) encapsulating the performance chip (2) and the components (3); A metal layer (5), the metal layer (5) covers the plastic packaging layer (4), and the metal layer (5) is located on the back side of the performance chip (2) and the components (3) to improve heat dissipation efficiency; A bump (6) is soldered to the other side of the redistribution layer (1).

2. A fan-out chip packaging structure, comprising: A redistribution layer (1), the redistribution layer (1) comprising at least one dielectric layer (11), at least one metal interconnection layer (12) located in the dielectric layer (11), and a solder pad (10) being provided on a surface of the redistribution layer (1); A performance chip (2) and a component (3), wherein the performance chip (2) and the component (3) are flipped on one side of the redistribution layer (1) and interconnected with the pads (10) of the redistribution layer (1); A plastic encapsulation layer (4), the plastic encapsulation layer (4) being located above the redistribution layer (1), and the plastic encapsulation layer (4) encapsulating the performance chip (2) and the components (3); A bump (6), wherein the bump (6) is soldered to the other side of the redistribution layer (1); A substrate (7) is provided, wherein a redistribution layer (1) having the bumps (6) soldered thereto is mounted on one side of the substrate (7), and a solder ball (8) is soldered thereto on the other side of the substrate (7).

3. The fan-out chip packaging structure according to claim 1 or 2, characterized in that: The dielectric layer (11) and the metal interconnection layer (12) of the redistribution layer (1) are a multi-layer structure, and interconnection lines are formed between the metal interconnection layers (12).

4. The fan-out chip packaging structure according to claim 3, characterized in that: The components (3) include one or more of capacitors, resistors, inductors, filters, processors, memories, power amplifiers, radio frequency devices, and switches.

5. The fan-out chip packaging structure according to claim 2, characterized in that: It also comprises a metal layer, wherein the metal layer (5) covers the plastic packaging layer (4), and the metal layer (5) is located on the back side of the performance chip (2) and the components (3) to improve the heat dissipation efficiency.

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