Current-limited vertical resonant cavity surface-emitting laser structure capable of emitting light from back surface

Abstract

The utility model discloses a current-limited vertical resonant cavity surface-emitting laser structure capable of emitting light from the back surface. The current-limited vertical resonant cavity surface-emitting laser structure comprises a PN junction element and an active light-emitting layer which are arranged between an upper Bragg reflector layer and a lower Bragg reflector layer, a multi-quantum well space layer is arranged between a P-type space layer and an N-type space layer of the active light-emitting layer; the upper Bragg reflector layer and the lower Bragg reflector layer are of the same semiconductor type, and only the upper Bragg reflector layer is doped with annular doped regions of different semiconductor types; a current guide layer and an upper metal layer which are in contact with the annular doped region are sequentially arranged above the upper Bragg reflector layer deviating from the active light-emitting layer; a substrate layer and a lower metal layer are sequentially arranged on the lower part, deviating from the active light-emitting layer, of the lower Bragg reflector layer; the lower light-emitting opening of the lower metal layer is used for emitting laser beams with better light-emitting photoelectric characteristics.

Description

Technical Field

[0001] The utility model relates to a vertical resonant cavity surface-emitting laser structure, in particular to a current-confined vertical resonant cavity surface-emitting laser structure with light emitting from the back side. Background Art

[0002] Vertical Cavity Surface Emitting Laser (VCSEL) is a semiconductor laser having a multi-layer semiconductor laser structure, and the multi-layer semiconductor structure includes a PIN junction. In detail, a distributed Bragg reflector (DBR) can also be called a Bragg mirror. The PIN junction corresponds to an active region set between a P-type DBR and an N-type DBR, and the active region is an undoped multiple quantum well and resonant cavity structure, so the active region can also be called an intrinsic (I-type) material structure. Therefore, the PIN junction is the junction formed by the P-type DBR, the I-type material structure and the N-type DBR. In the above structure, the holes of the P-type DBR and the electrons of the N-type DBR will combine with each other in the active region and generate photons.

[0003] See also Fig.11 As shown, Fig.11 The figure shows a more primitive VCSEL, in which a metal electrode 101 conducts an electrical signal to a P-type DBR layer 110 through a current guiding layer 102. The metal electrode 101 is formed with an upper light outlet 103, and the upper light outlet 103 is formed above the P-type DBR layer 110. An active region 120 is provided below the P-type DBR layer 110, and an N-type DBR layer 130 is provided below the active region 120. A substrate layer 140 is provided below the N-type DBR layer 130 so that the substrate layer 140 can support the N-type DBR layer 130 and all structures above the N-type DBR layer 130. A metal surface layer 150 can be plated below the substrate layer 140. In this way, the P-type DBR layer 110, the active region 120 and the N-type DBR layer 130 form the aforementioned PIN junction. As shown in FIG. Fig.11As shown, the metal surface layer 150 is located below the VCSEL, while the metal electrode 101 and the upper light outlet 103 are located above the VCSEL. The VCSEL emits the laser beam generated by it from the upper light outlet 103, and since the metal surface layer 150 has no need to emit light, the metal surface layer 150 completely covers the bottom of the substrate layer 140. The problem with this VCSEL is that it cannot effectively confine the current, so the photons it generates cannot be effectively confined to a region, which makes the photoelectric characteristics of the laser beam generated by this VCSEL poor.

[0004] See also Fig.12 As shown in Figure 2, in order to improve VCSEL and make it have better current confinement effect, the current mainstream processes are as follows: Fig.12 As shown, a selective oxidation method is used to form an oxide confinement layer 115 between the P-type DBR layer 110 and the active region 120 through a wet oxidation process. The oxide confinement layer 115 forms a conductive region 115A surrounded by an oxidized insulating material through a wet oxidation process, and the conductive region 115A limits the area where current flows.

[0005] See also Fig.13 As shown in FIG. 1 , in order to improve the VCSEL so that it has a better current confinement effect, another approach is as follows Fig.13 As shown, a circle of ion implantation regions 116 are provided in the P-type DBR layer 110 by ion implantation to concentrate the current in the central region of the P-type DBR layer 110 where the ion implantation region 116 is not provided. Fig.13 As shown, the ion implantation region 116 in the P-type DBR layer 110 does not contact the current guiding layer 102 .

[0006] Overview Figures 11 to 13 , it can be seen that the current VCSEL process has the following disadvantages:

[0007] Disadvantage 1: In terms of the effect of current limitation, Fig.12 The mainstream process shown is Fig.13 The effect shown is better. However, because the oxide confinement layer 115 is an oxide insulator except for the conductive region 115A, the oxide confinement layer 115 has a very poor thermal conductivity. Therefore, the oxide confinement layer 115 can be regarded as a thermal resistor. The oxide confinement layer 115 cannot effectively dissipate the waste heat generated by the current confinement in the P-type DBR layer 110, and thus will negatively affect the optoelectronic properties of the laser beam. For example, greater waste heat will produce greater light loss, causing more photons to be absorbed by the material and unable to become part of the laser beam emitted from the VCSEL.

[0008] Disadvantage 2: Fig.13 For the process shown, the configuration of the ion implantation region 116 will cause a nonlinear current kink phenomenon, which will cause the laser beam to generate lateral side-mode noise in the P-type DBR layer 110 and negatively affect the optoelectronic characteristics of the generated laser beam.

[0009] Disadvantage 3: At present, all VCSEL processes use the upper light outlet 103 to emit light. However, due to the use of Fig.12 The single structure of the oxide confinement layer 115 confines the current, or uses Fig.13 The single structure of the circle ion implantation area 116 limits the current, and the waste heat generated by the P-type DBR layer 110 is close to the upper light outlet 103, so that the temperature near the upper light outlet 103 is higher and it is easy to cause greater light loss. Even if the photons want to leave the upper light outlet 103 are absorbed by the material with higher temperature near the upper light outlet 103 and lost. Utility Model Content

[0010] The utility model provides a back-emitting current-confined vertical cavity surface emitting laser structure, which can limit the current of the vertical cavity surface emitting laser (VCSEL) and improve the above-mentioned disadvantages 1 to 3 at the same time, so as to generate a laser beam with better photoelectric characteristics.

[0011] The utility model discloses a current-confined vertical resonant cavity surface-emitting laser structure with back-light emission, comprising:

[0012] An active light-emitting layer, comprising:

[0013] A P-type space layer;

[0014] an N-type space layer; and

[0015] A multi-quantum well space layer is disposed between the P-type space layer and the N-type space layer;

[0016] A PN junction element;

[0017] An upper Bragg reflector layer, which is a Bragg reflector layer of a first semiconductor type and includes a ring-shaped doped region doped with a second semiconductor type;

[0018] a lower Bragg reflector layer, which is a Bragg reflector layer of the first semiconductor type;

[0019] The active light-emitting layer and the PN junction element are both disposed between the upper Bragg reflector layer and the lower Bragg reflector layer, and the upper Bragg reflector layer and the lower Bragg reflector layer are both Bragg reflector layers of the same semiconductor type, and the upper Bragg reflector layer is further doped with a ring-shaped doped region of a different semiconductor type;

[0020] A current guiding layer is disposed on a side of the upper Bragg reflector layer away from the active light-emitting layer and contacts the annular doped region of the upper Bragg reflector layer;

[0021] An upper metal layer is disposed on a side of the current guiding layer away from the active light-emitting layer;

[0022] A substrate layer is disposed on a side of the lower Bragg reflector layer away from the active light-emitting layer;

[0023] A lower metal layer is arranged on a side of the substrate layer away from the active light-emitting layer and is formed with a lower light-emitting opening.

[0024] The utility model uses the annular doped region in the upper Bragg reflector layer and the PN junction element to work together to achieve the effect of limiting current, so the current limiting task is not completely undertaken by a single structure. In this way, the waste heat generated when the utility model limits the current will not be concentrated in a single current limiting structure, but will be dispersed in a wider area, that is, the waste heat is dispersed in a wide area between the annular doped region and the PN junction element.

[0025] The waste heat of the utility model will not be concentrated in one place of the oxidation confinement layer, so the problem that the oxidation confinement layer cannot effectively dissipate heat can be improved.

[0026] The utility model makes the annular doped region in the upper Bragg reflector layer touch the current guiding layer, and this method can avoid the phenomenon of current nonlinear kink when the current is confined, so that the generation of lateral side-mode noise mentioned in the background technology can be avoided, thereby improving the problem of the negative impact of side-mode noise on the photoelectric characteristics of the laser beam.

[0027] The utility model sets the lower light output opening in the lower metal layer. Because the lower metal layer is farther away from the annular doped region in the upper Bragg reflector layer and farther away from the PN junction element, the lower light output opening of the utility model can be farther away from the place where waste heat is generated, thereby reducing the light loss near the lower light output opening.

[0028] In summary, the present invention is different from the prior art and improves the above-mentioned disadvantages 1 to 3, thereby enabling the VCSEL to generate a laser beam with better photoelectric characteristics and emit the laser beam from the lower light exit opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a cross-sectional schematic diagram of a current-confined vertical cavity surface-emitting laser structure with back-light emission according to the present invention in one embodiment.

[0030] Figure 2 It is a cross-sectional schematic diagram of another embodiment of the current confined vertical cavity surface emitting laser structure with back side light emission of the utility model.

[0031] Figure 3 It is a cross-sectional schematic diagram of another embodiment of the current-confined vertical cavity surface-emitting laser structure with back-light emission of the utility model.

[0032] Figures 4 to 8 It is a cross-sectional schematic diagram of the manufacturing process of a current-confined vertical cavity surface-emitting laser structure with back-light emission according to the present invention in one embodiment.

[0033] Fig. 9 and Fig.10 It is a cross-sectional schematic diagram of the manufacturing process of another embodiment of the current confined vertical cavity surface emitting laser structure with back side light emission of the utility model.

[0034] Fig.11 Schematic diagram of the cross section of the original VCSEL.

[0035] Fig.12 A schematic cross-sectional view of a VCSEL using the current mainstream process.

[0036] Fig.13 It is a cross-sectional schematic diagram of another existing VCSEL. DETAILED DESCRIPTION

[0037] A vertical cavity surface emitting laser (VCSEL) is a semiconductor laser, and a distributed Bragg reflector (DBR) provided in the VCSEL can also be called a Bragg mirror.

[0038] See also Figure 1As shown, the utility model provides a back-emitting current-confined vertical resonant cavity surface-emitting laser structure, which includes an upper metal layer 10, a current guiding layer 20, an upper Bragg reflector layer 30, an active light-emitting layer 40, a PN junction element 50, a lower Bragg reflector layer 60, a substrate layer 70 and a lower metal layer 80. This multi-layer structure can be stacked in various embodiments. Figure 1 It is merely a schematic diagram of the stacking state of one implementation mode, that is, a schematic diagram of the cross section of the back-emitting current-confined vertical cavity surface-emitting laser structure in one embodiment of the present invention.

[0039] The active light-emitting layer 40 includes an upper space layer 41, a multiple quantum well (MQW) space layer 42 and a lower space layer 43. Structurally, the multiple quantum well space layer 42 is disposed between the upper space layer 41 and the lower space layer 43. The upper space layer 41 and the lower space layer 43 are doped into space layers of different semiconductor types, that is, one of the upper space layer 41 and the lower space layer 43 is an N-type semiconductor and the other is a P-type semiconductor. In addition, the active light-emitting layer 40 and the PN junction element 50 are both disposed between the upper Bragg reflector layer 30 and the lower Bragg reflector layer 60. The upper Bragg reflector layer 30 and the lower Bragg reflector layer 60 are respectively Bragg reflector layers of a first semiconductor type, and the upper Bragg reflector layer 30 includes a ring-shaped doped region 31 doped with a second semiconductor type. In other words, the upper Bragg reflector layer 30 and the lower Bragg reflector layer 60 are both Bragg reflector layers of the same semiconductor type, and the upper Bragg reflector layer 30 further has the annular doped region 31 doped with a different semiconductor type.

[0040] In addition, the current guiding layer 20 is disposed on a side of the upper Bragg reflector layer 30 away from the active light emitting layer 40 , and the current guiding layer 20 contacts the annular doped region 31 .

[0041] The upper metal layer 10 is disposed on a side of the current guiding layer 20 away from the active light emitting layer 40 , and the upper metal layer 10 is used to receive an electrical signal.

[0042] The substrate layer 70 is disposed on a side of the lower Bragg reflector layer 60 away from the active light emitting layer 40 to support the lower Bragg reflector layer 60 and other structures.

[0043] The lower metal layer 80 is disposed on a side of the substrate layer 70 away from the active light emitting layer 40 , and the lower metal layer 80 is formed with a lower light emitting opening 81 .

[0044] The utility model utilizes the principle of VCSEL to generate a laser beam. After receiving the electrical signal through the upper metal layer 10, the current of the electrical signal is confined and flows in a confined area. The electrons and holes in the confined area combine in an active region between the N-type semiconductor and the P-type semiconductor and generate photons. The generated photons resonate in the vertical cavity and then pass through the light outlet, such as the lower light outlet opening 81 described in the present case, to emit a laser beam.

[0045] In this embodiment, the upper space layer 41 is an N-type space layer, and the lower space layer 43 is a P-type space layer, and the multi-quantum well space layer 42 is disposed between the P-type space layer and the N-type space layer. In addition, the upper Bragg reflector layer 30 and the lower Bragg reflector layer 60 are both N-type Bragg reflector layers, and the annular doped region 31 is doped into a P-type semiconductor by ion implantation. The upper Bragg reflector layer 30 is connected to the upper space layer 41 (N-type space layer) in the active light-emitting layer 40.

[0046] Further, the PN junction element 50 includes an upper junction 51 and a lower junction 52. In the present embodiment, the upper junction 51 is a P-type junction, and the lower junction 52 is an N-type junction. The N-type junction is connected to the lower Bragg reflector layer 60, and the P-type junction is connected to the P-type space layer in the active light-emitting layer 40.

[0047] In summary, in this embodiment, the N-type upper space layer 41 is connected to the N-type upper Bragg reflector layer 30 , the P-type lower space layer 43 is connected to the P-type upper junction 51 , and the N-type lower junction 52 is connected to the N-type lower Bragg reflector layer 60 .

[0048] Preferably, the PN junction element 50 is a tunnel diode. The current guiding layer 20 is a gallium arsenide (GaAs) layer, and the annular doped region 31 is a zinc (Zn) doped region. The upper metal layer 10, the current guiding layer 20, the upper Bragg reflector layer 30, the active light emitting layer 40, the PN junction element 50 and the lower Bragg reflector layer 60 form a mesa pillar, which extends from the lower Bragg reflector layer 60 to the lower metal layer 80, and the center of the mesa pillar is aligned with the lower light exit opening 81 of the lower metal layer 80.

[0049] The doping concentration of the annular doped region 31 diffuses from the top of the current guiding layer 20 toward a bottom surface of the upper Bragg reflector layer 30 facing the active light emitting layer 40. In addition, the doping region of the semiconductor element doped in the annular doped region 31 diffuses to the bottom surface of the upper Bragg reflector layer 30. Figure 1 As shown, the area with a higher doping density in the annular doping region 31 schematically represents an area with a higher doping concentration, while the area with a lower doping density schematically represents an area with a lower doping concentration. In practice, because the area with a higher doping concentration moves to the area with a lower doping concentration by diffusion, the doping concentration of the annular doping region 31 changes in a gradient toward the bottom surface of the upper Bragg reflector layer 30. Figure 1 As shown, the annular doped region 31 forms an annular shape in a horizontal direction, that is, parallel to the stacking direction of each layer, and a vertical axis surrounded by the annular doped region 31 corresponds in position to the position of the lower light emitting opening 81 to emit the laser beam.

[0050] The annular doped region 31 in the upper Bragg reflector layer 30 and the PN junction element 50 work together to achieve the function of limiting the current, so the current limiting task is not completely undertaken by a single structure. In this way, the waste heat generated when the current is limited by the present invention will not be concentrated in a single current limiting structure, but will be dispersed in a wider area, that is, the waste heat is dispersed in a wide area between the annular doped region 31 and the PN junction element 50.

[0051] Compared with the disadvantages 1 to 3 described in the background technology section, the above structure of the utility model has the following advantages:

[0052] Advantage 1: The annular doped region 31 and the PN junction element 50 work together to limit the current to a level no less than Fig.12 In the mainstream process shown, the oxide confinement layer 115 is used to confine the current. The waste heat of the utility model will not be concentrated in one place of the oxide confinement layer 115 but can be dispersed, thereby improving the problem mentioned in the disadvantage 1 that the oxide confinement layer 115 cannot effectively dissipate heat.

[0053] Advantage 2: The present invention allows the current guiding layer 20 to contact the annular doped region 31 of the upper Bragg reflector layer 30. This approach can avoid the phenomenon of current nonlinear kink when the current is confined, thereby avoiding the generation of lateral side-mode noise mentioned in the background technology, thereby improving the problem mentioned in Disadvantage 2.

[0054] Advantage 3: The lower light exit opening 81 of the utility model is disposed in the lower metal layer 80. Since the lower metal layer 80 is farther from the annular doped region 31 in the upper Bragg reflector layer 30 and farther from the PN junction element 50, the lower light exit opening 81 of the utility model can be farther away from where the waste heat is generated, thereby reducing the light loss near the lower light exit opening 81, thereby improving the disadvantage 3. Fig.12 and Fig.13 The temperature near the upper and middle light outlet 103 is relatively high, resulting in a problem of greater light loss.

[0055] However, the advantages of the present invention are not limited thereto. In this embodiment, because there is no Fig.12 The oxide confinement layer 115 in the mainstream process is shown, so the lattice of the DBR will not contact the oxide of the insulator to cause lattice mismatch. In other words, the upper Bragg reflector layer 30 and the lower Bragg reflector layer 60 of the utility model only need to be connected to the semiconductor materials of the active light-emitting layer 40 and the PN junction element 50 respectively. The upper Bragg reflector layer 30 and the lower Bragg reflector layer 60 only need to connect the same semiconductor type structure in the active light-emitting layer 40 and the same semiconductor type structure in the PN junction element 50. For example, in this embodiment, the N-type upper Bragg reflector layer 30 is connected to the N-type upper space layer 41 for lattice matching, and the P-type lower space layer 43 is connected to the upper junction 51 of the P-type PN junction element 50 for lattice matching.

[0056] The benefit of lattice matching is that it can strengthen the connection strength between structures, making them more stable. Fig.12 The oxide confinement layer 115 shown in the figure is lattice mismatched with the connected P-type DBR layer 110, so it is possible that due to the influence of heat, the P-type DBR layer 110 and the oxide confinement layer 115 may cause structural peeling and cracking, causing structural damage to the VCSEL. Therefore, in addition to improving heat dissipation in advantage 1, the utility model also avoids the problem of possible damage to the structure due to lattice mismatch.

[0057] In addition, according to semiconductor physics, in the same semiconductor material, the hole mobility (μ h ) and the electron mobility (electron mobility; μ e) are not the same. Negatively charged electrons are more likely to escape from atoms and migrate than positively charged holes, so the electron mobility is greater than the hole mobility. In addition, the conductivity (conductivity; σ) and the hole mobility and electron mobility in semiconductor materials have the following formula relationship:

[0058] σ=e(nμ e +pμ h )

[0059] Where e is the electron charge, n is the electron density, p is the hole density, and as mentioned above, σ is the conductivity in the semiconductor material, μ e is the electron mobility, μ h is the hole mobility. As is known, conductivity is inversely proportional to resistivity.

[0060] Based on the above, N-type semiconductor materials, such as the N-type space layer described in this case, have higher conductivity σ and lower resistivity because of their higher electron density n and lower hole density p. On the contrary, P-type semiconductor materials, such as the P-type space layer described in this case, have lower conductivity σ and higher resistivity because of their lower electron density n and higher hole density p.

[0061] In this embodiment, because the upper Bragg reflector layer 30 is mainly made of N-type semiconductor material, and because the lower Bragg reflector layer 60 is made of N-type semiconductor material, the back-emitting current confined vertical cavity surface-emitting laser structure of the present invention is more likely to be made of N-type semiconductor material in terms of area or volume. This means that a larger portion of the waste heat generated by the confined current of the present invention is located in the N-type semiconductor material, thus enjoying a lower hole density, higher conductivity and lower resistivity and generating less waste heat.

[0062] On the other hand, Figures 11 to 13 As shown, the background technology mainly limits the current near the P-type DBR layer 110, so most of the waste heat generated is located in the P-type semiconductor material, so a large amount of waste heat is generated due to the higher hole density, lower conductivity and higher resistivity. Therefore, this embodiment uses the N-type upper Bragg reflector layer 30 and the lower Bragg reflector layer 60, so the generation of waste heat can be further limited and the aforementioned advantage 1 can be further highlighted.

[0063] Furthermore, the present invention can configure the upper Bragg reflector layer 30 and the lower Bragg reflector layer 60 to be the same semiconductor type material, such as N-type semiconductor, because the present invention key configures the PN junction element 50 between the upper Bragg reflector layer 30 and the lower Bragg reflector layer 60. With the PN junction element 50, such as the aforementioned tunnel diode, the present invention can generate photons in the VCSEL by relying on one of the upper Bragg reflector layer 30 or the lower Bragg reflector layer 60 to cooperate with the active light emitting layer 40 and the PN junction element 50 to form a PIN junction.

[0064] See also Figure 2 As shown, in another embodiment of the present invention, the back-emitting current-confined vertical cavity surface-emitting laser structure further has an oxide confinement layer 90. The oxide confinement layer 90 is disposed between the N-type upper space layer 41, that is, the N-type space layer, and the N-type upper Bragg reflector layer 30. In addition, the oxide confinement layer 90 includes a conductive opening 91, and the conductive opening 91 is aligned with the lower light-emitting opening 81 of the lower metal layer 80. The conductive opening 91 contains a conductive material that is not oxidized by the wet oxidation process, and the rest of the oxide confinement layer 90 except the conductive opening 91 is an insulator oxide oxidized by the wet oxidation process.

[0065] Therefore, in this embodiment, the N-type upper space layer 41 is connected to the N-type upper Bragg reflector layer 30 through the oxide confinement layer 90. The P-type lower space layer 43 is connected to the upper junction 51 of the P-type PN junction element 50. The lower junction 52 of the N-type PN junction element 50 is connected to the N-type lower Bragg reflector layer 60.

[0066] Even though this embodiment is provided with the oxide confinement layer 90 for further confining the current, the oxide confinement layer 90 of the present invention does not need to bear the responsibility of confining the current completely as in the background technology. As mentioned above, the present invention has achieved the effect of confining the current by the cooperation of the annular doped region 31 in the upper Bragg reflector layer 30 and the PN junction element 50, so the oxide confinement layer 90 only further enhances the benefit of the current confinement of the present invention. Therefore, even though this embodiment is provided with the oxide confinement layer 90, this embodiment still has the aforementioned advantages 1 to 3. This embodiment still has the aforementioned advantage 1, because this embodiment can still have a better heat dissipation effect than the background technology, and will not concentrate the heat generated only in the oxide confinement layer 90.

[0067] See also Figure 3As shown, in yet another embodiment of the present invention, the PN junction element 50 is disposed between the N-type upper Bragg reflector layer 30 and the P-type upper space layer 41 .

[0068] Specifically, the upper junction 51 of the PN junction element 50 is connected to the upper Bragg reflector layer 30 of N type, and the upper junction 51 of the PN junction element 50 is of N type. The lower junction 52 of the PN junction element 50 is connected to the upper space layer 41 of P type, and the lower junction 52 of the PN junction element 50 is of P type.

[0069] Therefore, in this embodiment, the N-type upper Bragg reflector layer 30 is connected to the upper junction 51 of the N-type PN junction element 50, the P-type lower junction 52 of the PN junction element 50 is connected to the P-type upper space layer 41, and the N-type lower space layer 43 is connected to the N-type lower Bragg reflector layer 60.

[0070] In addition, the present invention does not limit the upper Bragg reflector layer 30 and the lower Bragg reflector layer 60 to be P-type semiconductors. Please refer to the following examples.

[0071] like Figure 1 As shown, in Figure 1 Under the presented structure, an embodiment of the present invention can also connect the P-type upper Bragg reflector layer 30 with the P-type upper space layer 41. The N-type lower space layer 43 is connected to the upper junction 51 of the N-type PN junction element 50. The P-type lower junction 52 of the P-type PN junction element 50 is connected to the P-type lower Bragg reflector layer 60.

[0072] like Figure 2 As shown, in Figure 2 Under the presented structure, an embodiment of the present invention can also connect the P-type upper Bragg reflector layer 30 with the P-type upper space layer 41 through the oxide confinement layer 90. The N-type lower space layer 43 is connected to the upper junction 51 of the N-type PN junction element 50. The P-type PN junction element 50 is connected to the lower Bragg reflector layer 60 of the P-type.

[0073] like Figure 3 As shown, in Figure 3 Under the presented architecture, an embodiment of the present invention can also connect the upper junction 51 of the P-type PN junction element 50 with the P-type upper Bragg reflector layer 30, the lower junction 52 of the N-type PN junction element 50 is connected to the N-type upper space layer 41, and the P-type lower space layer 43 is connected to the P-type lower Bragg reflector layer 60.

[0074] See also Figure 1 and Figures 4 to 8 As shown, in Figure 1 In the structure shown in FIG. 1 , and in the structure where both the upper Bragg reflector layer 30 and the lower Bragg reflector layer 60 are N-type semiconductors, the structure of this embodiment is Figures 4 to 8 Produced by the presented process.

[0075] See also Figure 4 As shown, the lower Bragg reflector layer 60, the PN junction element 50 having the lower junction 52 and the upper junction 51, the active light-emitting layer 40 having the lower space layer 43, the multi-quantum well space layer 42 and the upper space layer 41, and the upper Bragg reflector layer 30 are sequentially epitaxially grown on the substrate layer 70.

[0076] See also Figure 5 As shown, zinc as a P-type semiconductor is doped into two ion implantation targets of an exposed surface layer of the upper Bragg reflector layer 30 by ion implantation. There is a gap between the ion implantation targets, and the zinc of the P-type semiconductor migrates downward to the bottom surface of the upper Bragg reflector layer 30 by diffusion, thereby forming the annular doped region 31 of the upper Bragg reflector layer 30.

[0077] See also Figure 6 As shown, the metal current guiding layer 20 is formed on the upper Bragg reflector layer 30 to cover the exposed surface layer of the upper Bragg reflector layer 30 , so that the current guiding layer 20 contacts the annular doped region 31 of the upper Bragg reflector layer 30 .

[0078] See also Figure 7 As shown, the lower Bragg reflector layer 60, the PN junction element 50, the active light emitting layer 40 and the upper Bragg reflector layer 30 are patterned on the substrate layer 70 by photolithography to form the aforementioned mesa pillar structure.

[0079] See also Figure 8 As shown, a passivation layer 100 is formed to surround and cover the cylindrical structure, and then the passivation layer 100 is patterned by photolithography to expose the portion of the current guiding layer 20 corresponding to the annular doped region 31 as the location where the metal contact is to be set. In this embodiment, the passivation layer 100 can be, for example, a silicon nitride (SiN) material or a silicon dioxide (SiO 2 ) and other insulating materials.

[0080] See also Figure 1As shown, a metal layer is formed to surround and cover the protective layer 100, and the metal layer is patterned by a lithography process to form Figure 1 This step forms the upper metal layer 10 electrically connected to the current guiding layer 20 and forms the lower metal layer 80 having the lower light emitting opening 81, so that the upper metal layer 10 transmits the electrical signal to the current guiding layer 20 and the lower light emitting opening 81 emits the laser beam of the VCSEL.

[0081] In addition, Figure 2 In the structure shown, and in the structure where both the upper Bragg reflector layer 30 and the lower Bragg reflector layer 60 are N-type semiconductors, the structure of this embodiment enables Fig. 9 The epitaxial step is shown.

[0082] See also Fig. 9 As shown, the lower Bragg reflector layer 60, the PN junction element 50 having the lower junction 52 and the upper junction 51, the active light-emitting layer 40 having the lower space layer 43, the multi-quantum well space layer 42 and the upper space layer 41, a conductive layer 92 and the upper Bragg reflector layer 30 are sequentially epitaxially grown on the substrate layer 70.

[0083] Next, as described above, after sequentially forming the annular doped region 31, the current guiding layer 20, and the mesa pillar structure, the embodiment further performs Fig.10 The wet oxidation process is shown.

[0084] See also Fig.10 As shown, by performing a wet oxidation process on the conductive layer 92, the conductive layer 92 is oxidized in the horizontal direction to form the oxidized confinement layer 90, and the middle of the oxidized confinement layer 90 is the conductive opening 91 formed by the portion of the conductive layer 92 that is not oxidized. In this embodiment, the conductive layer 92 is aluminum (Al), and the oxidized confinement layer 90 is aluminum oxide (Al 2 O 3 ), the material of the conductive opening 91 which is not oxidized in the oxidation confinement layer 90 and the conductive layer 92 are aluminum (Al).

[0085] Then, as mentioned above, after the steps of sequentially forming the protective layer 100 and forming the metal layer on the protective layer 100, the present embodiment can present the same Figure 2 The structure shown.

[0086] The other embodiments mentioned in the present invention can be prepared by simply changing the above-mentioned process steps. Currently, in the technical field of VCSEL, there is no structure described in the present invention for improving the laser generation of VCSEL, so the structure described in the present invention should be protected.

[0087] The above description is only a preferred embodiment of the present invention, and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A current-confined vertical cavity surface-emitting laser structure with back-light emission, characterized in that: include: An active light-emitting layer, comprising: A P-type space layer; an N-type space layer; and A multi-quantum well space layer is disposed between the P-type space layer and the N-type space layer; A PN junction element; an upper Bragg reflector layer, which is a Bragg reflector layer of a first semiconductor type and includes a ring-shaped doped region doped with a second semiconductor type; a lower Bragg reflector layer, which is a Bragg reflector layer of the first semiconductor type; Wherein, the active light-emitting layer and the PN junction element are both disposed between the upper Bragg reflector layer and the lower Bragg reflector layer; A current guiding layer is disposed on a side of the upper Bragg reflector layer away from the active light-emitting layer and contacts the annular doped region of the upper Bragg reflector layer; An upper metal layer is disposed on a side of the current guiding layer away from the active light-emitting layer; A substrate layer is disposed on a side of the lower Bragg reflector layer away from the active light-emitting layer; A lower metal layer is arranged on a side of the substrate layer away from the active light-emitting layer and is formed with a lower light-emitting opening.

2. The back-emitting current-confined vertical cavity surface-emitting laser structure according to claim 1, characterized in that: The first semiconductor type is N-type, and the second semiconductor type is P-type, that is, the upper Bragg reflector layer and the lower Bragg reflector layer are both N-type Bragg reflector layers, and the annular doped region in the upper Bragg reflector layer is doped with a P-type semiconductor; The upper Bragg reflector layer is connected to the N-type space layer in the active light-emitting layer; The PN junction element includes a P-type junction and an N-type junction, the N-type junction is connected to the lower Bragg reflector layer, and the P-type junction is connected to the P-type space layer in the active light-emitting layer.

3. The current confined vertical cavity surface emitting laser structure with back-light emission as claimed in claim 2, characterized in that: Further including: An oxidized confinement layer is disposed between the N-type space layer and the upper Bragg reflector layer; wherein the oxidized confinement layer includes a conductive opening, and the conductive opening is aligned with the lower light exit opening of the lower metal layer.

4. The current confined vertical cavity surface emitting laser structure with back-light emission as claimed in claim 1, characterized in that: The first semiconductor type is N-type, and the second semiconductor type is P-type, that is, the upper Bragg reflector layer and the lower Bragg reflector layer are both N-type Bragg reflector layers, and the annular doped region in the upper Bragg reflector layer is doped with a P-type semiconductor; The PN junction element includes a P-type junction and an N-type junction, the N-type junction is connected to the upper Bragg reflector layer, and the P-type junction is connected to the P-type space layer in the active light-emitting layer; The lower Bragg reflector layer is connected to the N-type space layer in the active light-emitting layer.

5. The current confined vertical cavity surface emitting laser structure with back-light emission according to claim 1, characterized in that: The first semiconductor type is P-type, and the second semiconductor type is N-type, that is, the upper Bragg reflector layer and the lower Bragg reflector layer are both P-type Bragg reflector layers, and the annular doped region in the upper Bragg reflector layer is doped with N-type semiconductor; The upper Bragg reflector layer is connected to the P-type space layer in the active light-emitting layer; The PN junction element includes a P-type junction and an N-type junction, the P-type junction is connected to the lower Bragg reflector layer, and the N-type junction is connected to the N-type space layer in the active light-emitting layer.

6. The current confined vertical cavity surface emitting laser structure with back-light emission as claimed in claim 5, characterized in that: Further including: An oxidized confinement layer is disposed between the P-type space layer and the upper Bragg reflector layer; wherein the oxidized confinement layer includes a conductive opening, and the conductive opening is aligned with the lower light-emitting opening of the lower metal layer.

7. The current confined vertical cavity surface emitting laser structure with back-light emission according to claim 1, characterized in that: The first semiconductor type is P-type, and the second semiconductor type is N-type, that is, the upper Bragg reflector layer and the lower Bragg reflector layer are both P-type Bragg reflector layers, and the annular doped region in the upper Bragg reflector layer is doped with N-type semiconductor; The PN junction element includes a P-type junction and an N-type junction, the P-type junction is connected to the upper Bragg reflector layer, and the N-type junction is connected to the N-type space layer in the active light-emitting layer; The lower Bragg reflector layer is connected to the P-type space layer in the active light-emitting layer.

8. The current confined vertical cavity surface emitting laser structure with back-light emission as claimed in claim 1, characterized in that: The current guiding layer is a gallium arsenide layer.

9. The back-emitting current-confined vertical cavity surface-emitting laser structure according to any one of claims 2 to 4, characterized in that: The annular doped region in the upper Bragg reflector layer is a zinc doped region.

10. The back-emitting current-confined vertical cavity surface-emitting laser structure according to any one of claims 1 to 8, characterized in that: The PN junction element is a tunnel diode.

11. The back-emitting current-confined vertical cavity surface-emitting laser structure according to any one of claims 1 to 8, characterized in that: The doping concentration of the annular doped region diffuses from a top portion contacting the current guiding layer toward a bottom surface of the upper Bragg reflector layer facing the active light emitting layer.

12. The back-emitting current-confined vertical cavity surface-emitting laser structure according to claim 11, characterized in that: The annular doped region is diffused to the bottom surface of the upper Bragg reflector layer.

13. The back-emitting current-confined vertical cavity surface-emitting laser structure according to any one of claims 1 to 8, characterized in that: The upper metal layer, the current guiding layer, the upper Bragg reflector layer, the active light emitting layer, the PN junction element and the lower Bragg reflector layer form a cylindrical structure, which extends from the lower Bragg reflector layer to the lower metal layer, and the center of the cylindrical structure is aligned with the lower light emitting opening of the lower metal layer.

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