Differential mode surge protection circuit and Ethernet equipment

Abstract

The utility model provides a differential mode surge protection circuit and Ethernet equipment. The differential mode surge protection circuit is arranged between a PHY chip and a differential signal end. The differential mode surge protection circuit comprises a transient voltage suppression diode, a current limiting module and an isolation module. The first end of the transient voltage suppression diode is connected with the signal positive end of the PHY chip, the second end of the transient voltage suppression diode is connected with the signal negative end of the PHY chip, the two ends of the transient voltage suppression diode are connected with the differential signal end through the isolation module, and the current limiting module is arranged between the transient voltage suppression diode and the isolation module. The current limiting module is arranged between the transient voltage suppression diode and the isolation module, so that the current flowing through the transient voltage suppression diode can be suppressed, the smaller the current on the transient voltage suppression diode is, the smaller the clamping voltage of the transient voltage suppression diode is, and the differential mode surge resistance of the Ethernet equipment can be greatly improved.

Description

Technical Field

[0001] The utility model relates to the field of electronic technology, in particular to a differential mode surge protection circuit and Ethernet equipment. Background Art

[0002] With the development of integrated circuit technology, the integration of Ethernet devices is getting higher and higher, and differential signals are more susceptible to interference voltage. In the existing technology, TVS (Transient Voltage Suppressor) is usually used to achieve PHY's differential mode interference resistance. However, most of the existing TVS can only achieve a clamping voltage of 8 / 20us and 10A / 10V. If only TVS is used for differential mode interference resistance, it cannot meet higher-level differential mode surge test requirements. Utility Model Content

[0003] The main purpose of the utility model is to provide a differential mode surge protection circuit and Ethernet equipment, aiming to solve the problem that TVS in the prior art cannot meet the standard differential mode surge test requirements.

[0004] To achieve the above-mentioned purpose, the utility model provides a differential mode surge protection circuit, which is arranged between a PHY chip and a differential signal end; the differential mode surge protection circuit includes a transient voltage suppression diode, a current limiting module and an isolation module; the first end of the transient voltage suppression diode is connected to the signal positive end of the PHY chip, the second end of the transient voltage suppression diode is connected to the signal negative end of the PHY chip, the two ends of the transient voltage suppression diode are connected to the differential signal end through the isolation module, and the current limiting module is arranged between the transient voltage suppression diode and the isolation module.

[0005] Optionally, the current limiting module includes a first resistor; wherein:

[0006] The first end of the first resistor is connected to the first end of the transient voltage suppression diode, and the second end of the first resistor is connected to the positive signal end of the isolation module.

[0007] Optionally, the current limiting module includes a second resistor; wherein:

[0008] The first end of the second resistor is connected to the second end of the transient voltage suppression diode, and the second end of the second resistor is connected to the negative signal terminal of the isolation module.

[0009] Optionally, the current limiting module includes a first resistor and a second resistor; wherein:

[0010] The first end of the first resistor is connected to the first end of the transient voltage suppression diode, and the second end of the first resistor is connected to the positive signal end of the isolation module;

[0011] The first end of the second resistor is connected to the second end of the transient voltage suppression diode, and the second end of the second resistor is connected to the negative signal terminal of the isolation module.

[0012] Optionally, the first resistor and the second resistor have the same resistance value.

[0013] Optionally, the isolation module includes a transformer; wherein:

[0014] The first end of the first side of the transformer is connected to the positive electrode of the differential signal end, and the second end of the first side of the transformer is connected to the negative electrode of the differential signal end;

[0015] The first end of the second side of the transformer is connected to the current limiting module as a positive signal end, wherein the first end of the second side of the transformer and the first end of the first side of the transformer are the same end;

[0016] The second end of the second side of the transformer is connected to the current limiting module as a negative signal terminal.

[0017] Optionally, the differential mode surge protection circuit further includes a common mode protection module, and the common mode protection module includes a common mode inductor; wherein:

[0018] The first coil of the common mode inductor is connected between the first end of the second side of the transformer and the current limiting module;

[0019] The second coil of the common mode inductor is connected between the second end of the second side of the transformer and the current limiting module.

[0020] Optionally, the common-mode protection module further includes a common-mode protection device, a third resistor, a first capacitor and a second capacitor; wherein:

[0021] The common-mode inductor also includes an intermediate coil, a first end of the intermediate coil of the common-mode inductor is grounded through the first capacitor, a second end of the intermediate coil of the common-mode inductor is connected to a center tap of a second side of the transformer, a center tap of a first side of the transformer is grounded through the first resistor and the second capacitor in sequence, and the common-mode protection device is connected in parallel with the third resistor and the second capacitor.

[0022] In addition, to achieve the above-mentioned purpose, the utility model also provides an Ethernet device, which includes a PHY chip, a differential signal terminal and the differential mode surge protection circuit as described above.

[0023] Optionally, there are multiple differential signal terminals, and there are multiple differential-mode surge protection circuits, and each of the differential signal terminals is connected to the PHY chip via the corresponding differential-mode surge protection circuit.

[0024] The utility model proposes a differential mode surge protection circuit and Ethernet equipment, wherein the differential mode surge protection circuit is arranged between a PHY chip and a differential signal terminal; the differential mode surge protection circuit comprises a transient voltage suppressor diode, a current limiting module and an isolation module; the first end of the transient voltage suppressor diode is connected to the positive signal terminal of the PHY chip, the second end of the transient voltage suppressor diode is connected to the negative signal terminal of the PHY chip, the two ends of the transient voltage suppressor diode are connected to the differential signal terminal through the isolation module, and the current limiting module is arranged between the transient voltage suppressor diode and the isolation module. By arranging the current limiting module between the transient voltage suppressor diode and the isolation module, the current on the loop, that is, the current flowing through the transient voltage suppressor diode, can be suppressed. The smaller the current on the transient voltage suppressor diode, the smaller the clamping voltage of the transient voltage suppressor diode. At the same time, the transient voltage suppressor diode is connected in parallel between the positive signal terminal and the negative signal terminal of the PHY chip, so that the clamping voltage on the PHY chip can be reduced, and the ability of the Ethernet equipment to resist differential mode surges can be greatly improved, which can meet the standard requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0026] Figure 1 This is a functional module diagram of an embodiment of a differential mode surge protection circuit of the utility model;

[0027] Figure 2 It is a schematic diagram of the principle that the current limiting module in the differential mode surge protection circuit of the utility model includes a first resistor;

[0028] Figure 3 It is a schematic diagram of the principle that the current limiting module in the differential mode surge protection circuit of the utility model includes a second resistor;

[0029] Figure 4 This is a schematic diagram of the principle that the current limiting module in the differential mode surge protection circuit of the utility model includes a first resistor and a second resistor;

[0030] Figure 5This is a circuit structure diagram of the differential mode surge protection circuit of the utility model;

[0031] Figure 6 This is a circuit structure diagram of the Ethernet chip of the utility model.

[0032] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings.

[0033] Description of Figure Numbers:

[0034] 100, current limiting module; 200, isolation module; R1, first resistor; R2, second resistor; R3, third resistor; C1, first capacitor; C2, second capacitor; tvs, transient voltage suppression diode; T1, transformer; CMC, common mode inductor; CP, common mode protection device. DETAILED DESCRIPTION

[0035] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0036] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0037] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0038] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

[0039] The utility model provides a differential mode surge protection circuit, which is applied to Ethernet equipment. Figure 1 , Figure 1This is a functional module diagram of an embodiment of the differential mode surge protection circuit of the utility model. In this embodiment, the differential mode surge protection circuit is arranged between the PHY chip and the differential signal end; the differential mode surge protection circuit includes a transient voltage suppression diode TVS, a current limiting module 100 and an isolation module 200; the first end of the transient voltage suppression diode TVS is connected to the signal positive end of the PHY chip, the second end of the transient voltage suppression diode TVS is connected to the signal negative end of the PHY chip, the two ends of the transient voltage suppression diode TVS are connected to the differential signal end through the isolation module 200, and the current limiting module 100 is arranged between the transient voltage suppression diode TVS and the isolation module 200.

[0040] The PHY (Physical Layer) chip is used to receive and send Ethernet data frames.

[0041] The differential signal end is used to receive a differential signal or send a differential signal; it can be understood that the differential signal end usually includes two ports, namely a positive pole and a negative pole, the positive pole receives or sends a TX+ signal, and the negative pole receives or sends a TX- signal.

[0042] The transient voltage suppression diode TVS is connected between the PHY chip and the differential signal end, and the transient voltage suppression diode TVS is connected in parallel between the signal positive end and the signal negative end of the PHY chip. Therefore, the transient voltage suppression diode TVS can clamp the voltage of the PHY chip to the clamping voltage of the transient voltage suppression diode TVS when a differential mode surge occurs, thereby achieving resistance to the differential mode surge.

[0043] The isolation module 200 is used to isolate the PHY chip side from the differential signal end.

[0044] The current limiting module 100 is arranged between the transient voltage suppression diode TVS and the isolation module 200; it can be understood that when the differential signal end receives the differential signal, the voltage signal of the differential signal end is transmitted through the isolation module 200, and the isolation module 200, the current limiting module 100, and the transient voltage suppression diode TVS constitute a current loop; after adding the current limiting module 100, the current value in the current loop is reduced, so when a smaller current value is applied to the transient voltage suppression diode, the clamping voltage of the transient voltage suppression diode TVS is also smaller, and the transient voltage suppression diode TVS is connected in parallel between the signal positive terminal and the signal negative terminal of the PHY chip, therefore, the clamping voltage of the PHY chip can be reduced, thereby greatly improving the resistance to differential mode surges, meeting the surge protection requirements of 2KV and above, and can be applied to surge sensitive equipment.

[0045] Under normal circumstances, after the differential signal is input, it is transmitted to the signal end of the PHY chip through the isolation module 200 and the current limiting module 100;

[0046] In the event of a differential mode surge, the presence of the current limiting module 100 can reduce the current value in the current loop, thereby reducing the clamping voltage on the transient voltage suppression diode, thereby reducing the clamping voltage at both ends of the PHY chip, and greatly improving the ability to resist differential mode surges.

[0047] This embodiment sets a current limiting module 100 between the transient voltage suppression diode TVS and the isolation module 200, so that the current in the loop, that is, the current flowing through the transient voltage suppression diode TVS, can be suppressed. The smaller the current on the transient voltage suppression diode TVS, the smaller the clamping voltage of the transient voltage suppression diode TVS. At the same time, the transient voltage suppression diode TVS is connected in parallel between the signal positive terminal and the signal negative terminal of the PHY chip. Therefore, the clamping voltage on the PHY chip can be reduced, and the ability of the Ethernet device to resist differential mode surges can be greatly improved, which can meet the standard requirements.

[0048] Further, see Figure 2 , the current limiting module 100 includes a first resistor R1; wherein:

[0049] A first end of the first resistor R1 is connected to a first end of the transient voltage suppression diode tvs, and a second end of the first resistor R1 is connected to a positive signal end of the isolation module 200 .

[0050] In this embodiment, the current limiting of the loop is achieved by setting the first resistor R1.

[0051] At this time, the current in the loop is output from the positive signal end of the isolation module 200, passes through the parallel loop of the first resistor R1, the transient voltage suppression diode tvs and the PHY chip in sequence, and is output to the negative signal end of the isolation module 200 to form a loop.

[0052] At this time, the equivalent resistance in the loop is:

[0053] R t =R1+R tvs / / R phy

[0054] Among them, R t is the equivalent resistance, R1 is the resistance value of the first resistor R1, R tvs is the actual resistance of the transient voltage suppression diode TVS, R phyis the equivalent resistance of the PHY chip; the actual resistance of the transient voltage suppression diode TVS can be selected based on actual needs, such as the actual resistance of the transient voltage suppression diode TVS can be dynamically changed between 0.5 and 5Ω.

[0055] Based on Ohm's law, the loop current is:

[0056]

[0057] Among them, I s is the loop current, V s is the voltage across the isolation module 200.

[0058] It can be seen from the above formula that when the resistance of the first resistor R1 increases, the loop current decreases accordingly. Therefore, after the first resistor R1 is provided in this embodiment, the loop current can be effectively reduced.

[0059] The clamping voltage on the PHY chip is:

[0060] V d =R tvs ×I s

[0061] Among them, V d is the clamping voltage on the PHY chip; it can be understood that the PHY chip is connected in parallel with the transient voltage suppression diode TVS through the signal positive terminal and the signal negative terminal, so the voltage across the PHY chip and the transient voltage suppression diode TVS is the same.

[0062] It can be seen from the above formula that when the resistance of the first resistor R1 increases, the loop current decreases accordingly, and at the same time, the clamping voltage on the PHY chip decreases accordingly. Therefore, setting the first resistor R1 can effectively reduce the transient voltage suppression diode tvs and the clamping voltage on the PHY chip.

[0063] Further, see Figure 3 , the current limiting module 100 includes a second resistor R2; wherein:

[0064] The first end of the second resistor R2 is connected to the second end of the transient voltage suppression diode tvs, and the second end of the second resistor R2 is connected to the negative signal terminal of the isolation module 200 .

[0065] In this embodiment, the current limiting of the loop is achieved by setting the second resistor R2.

[0066] At this time, the current in the loop is output from the positive signal end of the isolation module 200, passes through the parallel loop of the transient voltage suppression diode tvs and the PHY chip, and the second resistor R2, and then output to the negative signal end of the isolation module 200 to form a loop.

[0067] At this time, the equivalent resistance in the loop is:

[0068] R t =R tvs / / R phy +R2

[0069] Wherein, R2 is the resistance value of the second resistor R2;

[0070] Based on Ohm's law, the loop current is:

[0071]

[0072] It can be seen from the above formula that when the resistance of the second resistor R2 increases, the loop current decreases accordingly. Therefore, after the second resistor R2 is provided in this embodiment, the loop current can be effectively reduced.

[0073] The clamping voltage on the PHY chip is:

[0074] V d =R tvs ×I s

[0075] Among them, V d is the clamping voltage on the PHY chip; it can be understood that the PHY chip is connected in parallel with the transient voltage suppression diode TVS through the signal positive terminal and the signal negative terminal, so the voltage across the PHY chip and the transient voltage suppression diode TVS is the same.

[0076] It can be seen from the above formula that when the resistance of the second resistor R2 increases, the loop current decreases accordingly, and at the same time, the clamping voltage on the PHY chip decreases accordingly. Therefore, setting the second resistor R2 can effectively reduce the transient voltage suppression diode tvs and the clamping voltage on the PHY chip.

[0077] Further, see Figure 4 , the current limiting module 100 includes a first resistor R1 and a second resistor R2; wherein:

[0078] The first end of the first resistor R1 is connected to the first end of the transient voltage suppression diode tvs, and the second end of the first resistor R1 is connected to the positive signal end of the isolation module 200;

[0079] The first end of the second resistor R2 is connected to the second end of the transient voltage suppression diode tvs, and the second end of the second resistor R2 is connected to the negative signal terminal of the isolation module 200 .

[0080] In this embodiment, current limiting of the loop is achieved by simultaneously providing the first resistor R1 and the second resistor R2.

[0081] At this time, the current in the loop is output from the positive signal end of the isolation module 200, passes through the first resistor R1, the parallel loop of the transient voltage suppression diode tvs and the PHY chip, and the second resistor R2, and then output to the negative signal end of the isolation module 200 to form a loop.

[0082] At this time, the equivalent resistance in the loop is:

[0083] R t =R1+R tvs / / R phy +R2=(R1+R2)+R tvs / / R phy

[0084] Based on Ohm's law, the loop current is:

[0085]

[0086] It can be seen from the above formula that when the sum of the resistance values ​​of the first resistor R1 and the second resistor R2 increases, the loop current decreases accordingly. Therefore, after the first resistor R1 and the second resistor R2 are provided in this embodiment, the loop current can be effectively reduced.

[0087] The clamping voltage on the PHY chip is:

[0088] V d =R tvs ×I s

[0089] Among them, V d is the clamping voltage on the PHY chip; it can be understood that the PHY chip is connected in parallel with the transient voltage suppression diode TVS at the negative end of the signal through the positive end of the signal, so the voltage across the PHY chip and the transient voltage suppression diode TVS is the same.

[0090] It can be seen from the above formula that when the sum of the resistance values ​​of the first resistor R1 and the second resistor R2 increases, the loop current decreases accordingly, and at the same time, the clamping voltage on the PHY chip decreases accordingly. Therefore, setting the first resistor R1 and the second resistor R2 can effectively reduce the transient voltage suppression diode TVS and the clamping voltage on the PHY chip.

[0091] Furthermore, the resistance values ​​of the first resistor R1 and the second resistor R2 are equal.

[0092] In this embodiment, the first resistor R1 and the second resistor R2 with equal resistance values ​​are set. At the same time, the first resistor R1 and the second resistor R2 are respectively set at the positive signal end and the negative signal end of the isolation module 200, that is, the first resistor R1 and the second resistor R2 are symmetrically set, so that the circuit structure is balanced and the stability of the circuit is guaranteed.

[0093] It should be noted that the larger the resistance of the first resistor R1 and the second resistor R2, the stronger the protection capability against differential mode surges, but the insertion loss will also increase. Therefore, the resistance of the first resistor R1 and the second resistor R2 can be set based on actual needs, such as 0.5 to 2.5Ω; in order to avoid excessive insertion loss, generally, the resistance of the first resistor R1 and the second resistor R2 is less than or equal to 3Ω.

[0094] Further, see Figure 5 , the isolation module 200 includes a transformer T1; wherein:

[0095] The first end of the first side of the transformer T1 is connected to the positive electrode of the differential signal end, and the second end of the first side of the transformer T1 is connected to the negative electrode of the differential signal end;

[0096] The first end of the second side of the transformer T1 is connected to the current limiting module 100 as a positive signal end, wherein the first end of the second side of the transformer T1 and the first end of the first side of the transformer T1 are the same end;

[0097] The second end of the second side of the transformer T1 is connected to the current limiting module 100 as a negative signal terminal.

[0098] When receiving a signal at the differential signal end, the first side of the transformer T1 serves as the primary side and the second side as the secondary side; the positive pole of the differential signal end, the primary side of the transformer T1, and the negative pole of the differential signal end form a loop; the secondary side of the transformer T1 corresponds to the output voltage; the first end of the secondary side of the transformer T1 forms a loop through the parallel loop of the transient voltage suppression diode tvs and the PHY chip, and the second end of the secondary side of the transformer T1 (the current limiting module 100 is set based on a specific method).

[0099] Furthermore, the differential mode surge protection circuit further includes a common mode protection module, and the common mode protection module includes a common mode inductor CMC; wherein:

[0100] The first coil of the common mode inductor CMC is connected between the first end of the second side of the transformer T1 and the current limiting module 100;

[0101] The second coil of the common mode inductor CMC is connected between the second end of the second side of the transformer T1 and the current limiting module 100 .

[0102] The current of the transformer T1 flows into the first coil of the common-mode inductor CMC and flows out from the second coil to form a loop; specifically, the first end of the secondary side of the transformer T1 passes through the first coil of the common-mode inductor CMC, the parallel loop of the transient voltage suppression diode TVS and the PHY chip, the second coil of the common-mode inductor CMC, and the second end of the secondary side of the transformer T1 to form a loop.

[0103] When the first resistor R1 and the second resistor R2 are set, the first resistor R1 and the second resistor R2 are set between the common mode inductor CMC and the transient voltage suppression diode tvs.

[0104] When the normal current in the circuit flows through the common-mode inductor CMC, the current generates opposite magnetic fields in the inductor coils wound in the same phase and cancel each other out; when a common-mode current flows through the coil, due to the isotropic nature of the common-mode current, a magnetic field in the same direction is generated in the coil, increasing the inductive reactance of the coil, making the coil exhibit high impedance and producing a strong damping effect, thereby attenuating the common-mode current and achieving the purpose of filtering.

[0105] Furthermore, the common mode protection module further includes a common mode protection device CP, a third resistor R3, a first capacitor C1 and a second capacitor C2; wherein:

[0106] The common-mode inductor CMC also includes an intermediate coil, a first end of the intermediate coil of the common-mode inductor CMC is grounded through the first capacitor C1, a second end of the intermediate coil of the common-mode inductor CMC is connected to the center tap of the second side of the transformer T1, the center tap of the first side of the transformer T1 is grounded through the third resistor R3 and the second capacitor C2 in sequence, and the common-mode protection device CP is connected in parallel with the third resistor R3 and the second capacitor C2.

[0107] The common-mode protection device CP, the third resistor R3, the first capacitor C1 and the second capacitor C2 are used to discharge the energy in the circuit when a surge occurs, thereby protecting the circuit; the specific type of the common-mode protection device CP can be selected based on actual needs, such as GDT (Gas Discharge Tube), TSS (Thyristor Surge Suppressors) or MOV (Metal Oxide Varistors).

[0108] The values ​​of specific components can be set based on actual needs. For example, the capacitance of the first capacitor C1 can be selected from 10 pF to 2.2 nF, and the capacitance of the second capacitor C2 can be selected from 470 pF to 470 nF.

[0109] It should be noted that, in actual applications, the common-mode inductor CMC can be set to two-wire or three-wire. When the common-mode inductor CMC is set to three-wire, it has an intermediate coil, and the first capacitor C1 can be set based on the above method. When the common-mode inductor CMC is set to two-wire, it does not have an intermediate coil, and the first capacitor C1 may not be set.

[0110] The overall implementation principle of this application is described below:

[0111] When receiving a signal at the differential signal end, the first side of the transformer T1 is used as the primary side, and the second side is used as the secondary side; the positive electrode of the differential signal end, the primary side of the transformer T1, and the negative electrode of the differential signal end form a loop; the secondary side of the transformer T1 corresponds to the output voltage;

[0112] The first end of the secondary side of the transformer T1 sequentially forms a loop through the first coil of the common mode inductor CMC, the first resistor R1, the parallel loop of the transient voltage suppression diode TVS and the PHY chip, the second resistor R2, the second coil of the common mode inductor CMC, and the second end of the secondary side of the transformer T1;

[0113] At this time, the equivalent resistance in the loop is:

[0114] R t =R1+R tvs / / R phy +R2=(R1+R2)+R tvs / / R phy

[0115] Based on Ohm's law, the loop current is:

[0116]

[0117] It can be seen from the above formula that when the sum of the resistance values ​​of the first resistor R1 and the second resistor R2 increases, the loop current decreases accordingly. Therefore, after the first resistor R1 and the second resistor R2 are provided in this embodiment, the loop current can be effectively reduced.

[0118] The clamping voltage on the PHY chip is:

[0119] V d =R tvs ×I s

[0120] Among them, V d is the clamping voltage on the PHY chip; it can be understood that the PHY chip is connected in parallel with the transient voltage suppression diode TVS through the signal positive terminal and the signal negative terminal, so the voltage across the PHY chip and the transient voltage suppression diode TVS is the same.

[0121] It can be seen from the above formula that when the sum of the resistance values ​​of the first resistor R1 and the second resistor R2 increases, the loop current decreases accordingly, and at the same time, the clamping voltage on the PHY chip decreases accordingly. Therefore, setting the first resistor R1 and the second resistor R2 can effectively reduce the transient voltage suppression diode TVS and the clamping voltage on the PHY chip.

[0122] The utility model also protects an Ethernet device, which includes an Ethernet device, the Ethernet device includes a PHY chip, a differential signal terminal and a differential mode surge protection circuit, the structure of the differential mode surge protection circuit can refer to the above embodiment, and will not be repeated here. As a matter of course, since the Ethernet device of this embodiment adopts the technical solution of the above differential mode surge protection circuit, the Ethernet device has all the beneficial effects of the above differential mode surge protection circuit.

[0123] Further, see Figure 6 , the number of the differential signal terminals is multiple, the number of the differential-mode surge protection circuits is multiple, and each of the differential signal terminals is connected to the PHY chip through the corresponding differential-mode surge protection circuit.

[0124] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, method, article or system including the element. The serial numbers of the above-mentioned embodiments of the utility model are for description only and do not represent the advantages and disadvantages of the embodiments.

[0125] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A differential mode surge protection circuit, characterized in that: The differential mode surge protection circuit is arranged between the PHY chip and the differential signal end; the differential mode surge protection circuit includes a transient voltage suppression diode, a current limiting module and an isolation module; the first end of the transient voltage suppression diode is connected to the signal positive end of the PHY chip, the second end of the transient voltage suppression diode is connected to the signal negative end of the PHY chip, the two ends of the transient voltage suppression diode are connected to the differential signal end through the isolation module, and the current limiting module is arranged between the transient voltage suppression diode and the isolation module.

2. The differential mode surge protection circuit according to claim 1, characterized in that: The current limiting module includes a first resistor; wherein: The first end of the first resistor is connected to the first end of the transient voltage suppression diode, and the second end of the first resistor is connected to the positive signal end of the isolation module.

3. The differential mode surge protection circuit according to claim 1, characterized in that: The current limiting module includes a second resistor; wherein: The first end of the second resistor is connected to the second end of the transient voltage suppression diode, and the second end of the second resistor is connected to the negative signal terminal of the isolation module.

4. The differential mode surge protection circuit according to claim 1, characterized in that: The current limiting module includes a first resistor and a second resistor; wherein: The first end of the first resistor is connected to the first end of the transient voltage suppression diode, and the second end of the first resistor is connected to the positive signal end of the isolation module; The first end of the second resistor is connected to the second end of the transient voltage suppression diode, and the second end of the second resistor is connected to the negative signal terminal of the isolation module.

5. The differential mode surge protection circuit according to claim 4, characterized in that: The resistance values ​​of the first resistor and the second resistor are equal.

6. The differential mode surge protection circuit according to claim 1, characterized in that: The isolation module includes a transformer; wherein: The first end of the first side of the transformer is connected to the positive electrode of the differential signal end, and the second end of the first side of the transformer is connected to the negative electrode of the differential signal end; The first end of the second side of the transformer is connected to the current limiting module as a positive signal end, wherein the first end of the second side of the transformer and the first end of the first side of the transformer are the same end; The second end of the second side of the transformer is connected to the current limiting module as a negative signal terminal.

7. The differential mode surge protection circuit according to claim 6, characterized in that: The differential mode surge protection circuit further includes a common mode protection module, and the common mode protection module includes a common mode inductor; wherein: The first coil of the common mode inductor is connected between the first end of the second side of the transformer and the current limiting module; The second coil of the common mode inductor is connected between the second end of the second side of the transformer and the current limiting module.

8. The differential mode surge protection circuit according to claim 7, characterized in that: The common mode protection module further includes a common mode protection device, a third resistor, a first capacitor and a second capacitor; wherein: The common-mode inductor also includes an intermediate coil, a first end of the intermediate coil of the common-mode inductor is grounded through the first capacitor, a second end of the intermediate coil of the common-mode inductor is connected to the center tap of the second side of the transformer, the center tap of the first side of the transformer is grounded through the third resistor and the second capacitor in sequence, and the common-mode protection device is connected in parallel with the third resistor and the second capacitor.

9. An Ethernet device, characterized in that: The Ethernet device comprises a PHY chip, a differential signal terminal and a differential mode surge protection circuit as claimed in any one of claims 1 to 8.

10. The Ethernet device according to claim 9, characterized in that: There are multiple differential signal terminals, and there are multiple differential mode surge protection circuits. Each of the differential signal terminals is connected to the PHY chip via the corresponding differential mode surge protection circuit.

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