Light-emitting module

Abstract

The utility model discloses a light-emitting module which comprises a substrate and a chip array arranged on the substrate, the chip array comprises a chip main body structure, and a plurality of P electrodes, a plurality of N electrodes and a plurality of transition electrodes are formed in the chip main body structure; the plurality of P electrodes form a P electrode array, the plurality of N electrodes are arranged on the side edge of at least one side of the P electrode array, the plurality of transition electrodes are arranged between the P electrode array and the plurality of N electrodes, and the plurality of transition electrodes form a transition column. Transition columns are arranged between a P electrode array and a plurality of N electrodes of a chip array, so that enough insulation distance is formed between the P electrodes and the N electrodes, the risk of short circuit between the N electrodes and the P electrodes is reduced, meanwhile, the distances between the electrodes in a light-emitting module are uniform, and the fluidity and the packaging effect of packaging glue are ensured.

Description

Technical Field

[0001] The utility model mainly relates to the field of display technology, and in particular to a light-emitting module. Background Art

[0002] In order to achieve high-precision lighting projection effects, current light-emitting modules mainly integrate multiple light-emitting chips in a small-sized optical structure. The existing method realizes a simple structure integrating multiple light-emitting chips by setting a common-pole connection.

[0003] Since a large number of light-emitting chips are integrated in this tiny structure, the distance between the electrodes of multiple light-emitting chips is too small, which can easily lead to a short circuit between the P electrode and the N electrode, affecting the light output efficiency of the light-emitting module. When the distance between the P electrode and the N electrode is too large, it affects the flow uniformity of the packaging glue inside the light-emitting module and affects the packaging effect of the light-emitting module. Utility Model Content

[0004] The purpose of the utility model is to overcome the shortcomings of the prior art. The utility model provides a light-emitting module. By setting a transition column between a P electrode array and a plurality of N electrodes in a chip array, a sufficient distance is provided between the P electrode and the N electrode to reduce the risk of short circuit. At the same time, the spacing between each electrode is uniform to ensure the fluidity of the packaging glue and the packaging effect.

[0005] The utility model provides a light-emitting module, which comprises: a substrate and a chip array arranged on the substrate, wherein the chip array comprises a chip main body structure and a current guiding layer, wherein a plurality of P electrodes, a plurality of N electrodes and a plurality of transition electrodes are formed in the chip main body structure;

[0006] The plurality of P electrodes form a P electrode array, the plurality of N electrodes are arranged on the side of the P electrode array, and the plurality of transition columns are arranged between the P electrode array and the plurality of N electrodes.

[0007] Furthermore, support glue is filled between the plurality of P electrodes and the plurality of N electrodes of the chip array.

[0008] Furthermore, the substrate is a silicon-based circuit board, a driving circuit is provided on the silicon-based circuit board, and the chip array is electrically connected to the driving circuit.

[0009] Furthermore, the driving circuit is provided with a plurality of conduction points, and the plurality of conduction points are arranged in a one-to-one correspondence with the plurality of N electrodes and the plurality of P electrodes of the chip array;

[0010] The plurality of N electrodes and the plurality of P electrodes are electrically connected to the plurality of conduction points in a one-to-one correspondence.

[0011] Furthermore, a plurality of connection bumps are arranged on the substrate, and the plurality of N electrodes, the plurality of P electrodes and the plurality of transition electrodes are connected to the plurality of connection bumps in a one-to-one correspondence.

[0012] Furthermore, the connection bumps on the substrate corresponding to the positions of the plurality of N electrodes and the plurality of P electrodes are electrically connected to the internal driving circuit to form the plurality of conduction points.

[0013] Furthermore, the connection bumps on the substrate corresponding to the positions of the plurality of transition electrodes are arranged in an insulating area of ​​the substrate.

[0014] Furthermore, a plurality of wire grooves are provided on the chip main body structure, and the current guiding layer is arranged in at least one of the plurality of wire grooves.

[0015] Furthermore, a groove is provided at the bottom of the wire trough, and the current guiding layer is snap-fitted into the groove.

[0016] Furthermore, the chip main body structure forms a plurality of bosses arranged in an array based on the wire grooves, and the array structure of the plurality of bosses includes a plurality of N-pole bosses and a plurality of P-pole bosses, a P electrode is formed on the P-pole boss, and the plurality of P electrodes form a P electrode array, an N electrode is formed on the N-pole boss, and the plurality of N electrodes are arranged on the outer edge of the P electrode array.

[0017] Furthermore, a plurality of transition bosses are arranged between the P-electrode array and the plurality of N-pole bosses, the plurality of transition electrodes are formed on the plurality of transition bosses, and the plurality of transition electrodes form a transition column.

[0018] Furthermore, the plurality of P electrodes in the P electrode array are independently distributed, the plurality of N electrodes are connected in series, and any one of the P electrodes is connected to the N electrode to form a light-emitting chip.

[0019] Furthermore, the plurality of N electrodes are arranged on the side of at least one side of the P electrode array.

[0020] Furthermore, the light-emitting module also includes: a dam covering the chip array, a light conversion layer arranged above the chip array, and a packaging layer covering the dam, wherein the light conversion layer is used to convert the light color of the chip array.

[0021] The utility model provides a light-emitting module, which provides a transition column between a P electrode array and a plurality of N electrodes of a chip array, so that a sufficient insulation distance is provided between the P electrodes and the N electrodes, thereby reducing the risk of a short circuit between the N electrodes and the P electrodes, and at the same time making the spacing between the electrodes in the light-emitting module uniform, thereby ensuring the fluidity of the packaging glue and the packaging effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 It is a structural schematic diagram of the light-emitting module in an embodiment of the utility model;

[0024] Figure 2 It is a top view of the structure of the chip array in the embodiment of the utility model;

[0025] Figure 3 It is a top view of another structural state of the chip array in the embodiment of the utility model;

[0026] Figure 4 It is a top view of another structural state of the chip array in the embodiment of the utility model;

[0027] Figure 5 This is a schematic diagram of the connection structure between the chip array and the substrate in the embodiment of the utility model;

[0028] Figure 6 is a cross-sectional view of a chip array structure in an embodiment of the utility model;

[0029] Figure 7 is a schematic diagram of the current guiding layer structure in an embodiment of the utility model;

[0030] Figure 8 It is a schematic diagram of another structural state of the current guiding layer in the embodiment of the utility model. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0032] Figure 1 The schematic diagram of the structure of the light-emitting module in the embodiment of the utility model is shown; Figure 2 A top view of the structure of the chip array in an embodiment of the utility model is shown; Figure 3 Another top view of the chip array in another structural state in the embodiment of the utility model is shown; Figure 4 A top view of another structural state of the chip array in an embodiment of the utility model is shown; Figure 5 The schematic diagram of the chip array and substrate connection structure in the embodiment of the utility model is shown; the light-emitting module comprises: a substrate 2 and a chip array 3 arranged on the substrate 2, the chip array 3 comprises a chip main body structure 33 and a current guiding layer 35, and a plurality of P electrodes 32, a plurality of N electrodes 31 and a plurality of transition electrodes 34 are formed in the chip main body structure 33;

[0033] The plurality of P electrodes 32 form a P electrode array, the plurality of N electrodes 31 are arranged on the side of the P electrode array, and the plurality of transition columns are arranged between the P electrode array and the plurality of N electrodes.

[0034] Specifically, the chip main body structure 33 includes: a buffer layer 331 , an N-type semiconductor layer 332 , a quantum well layer 333 , a P-type semiconductor layer 334 and an electrode transition layer 335 which are stacked in sequence.

[0035] Furthermore, the electrode transition layer 335 may be a single-layer structure or a multi-layer structure, wherein the multi-layer structure includes one or more layers of indium tin oxide (ITO) or other conductive oxides and metal silver layers to meet the light emission requirements of the light-emitting module.

[0036] Specifically, a plurality of wire grooves are opened on the chip main body structure 33, and the chip main body structure 33 forms a plurality of bosses arranged in an array based on the wire grooves. The array structure of the plurality of bosses includes a plurality of N-pole bosses and a plurality of P-pole bosses. P electrodes 32 are formed on the P-pole bosses, and the plurality of P electrodes 32 form a P-electrode array. N electrodes 31 are formed on the N-pole bosses, and the plurality of N electrodes 31 are arranged on the outer edge of the P-electrode array.

[0037] Furthermore, when preparing the chip array 3, the chip array 3 can be formed on a substrate 7, wherein the substrate 7 is used to support the chip array 3, and the buffer layer 331 is used to grow the N-type semiconductor layer 332 to prevent the N-type semiconductor layer 332 from growing directly on the substrate 7, thereby reducing the growth defect density of the N-type semiconductor layer 332.

[0038] Furthermore, the substrate 7 may be made of a sapphire substrate, a silicon substrate, a silicon carbide substrate or the like, to meet the preparation requirements of the chip array 3 .

[0039] Furthermore, after the chip array 3 is connected to the substrate 2 through a bonding process, the substrate 7 can be separated from the chip array 3 by a laser stripping method, or the substrate 7 can be stripped by chemical etching.

[0040] Furthermore, the substrate 7 is preferably stripped by chemical etching, which can prevent the gas generated during laser stripping from causing impact damage to the chip array 3.

[0041] Specifically, the substrate 2 is a silicon-based circuit board, a driving circuit is provided on the silicon-based circuit board, the chip array 3 is electrically connected to the driving circuit, and the driving circuit can independently drive any light-emitting chip in the chip array 3 to realize lighting control of the chip array 3.

[0042] Furthermore, a plurality of conduction points are provided on the driving circuit, and the plurality of conduction points are arranged one-to-one with the plurality of N electrodes 31 and the plurality of P electrodes 32 of the chip array 3, and the plurality of N electrodes 31 and the plurality of P electrodes 32 are electrically connected to the plurality of conduction points one-to-one, thereby realizing electrical connection between the plurality of N-pole welding points 311 and the plurality of P-pole welding points 321 and the substrate 2.

[0043] Furthermore, the plurality of conducting points on the substrate 2 are arranged away from the position of the transition electrode 34 , so that the transition electrode 34 is in a non-conducting state, thereby avoiding a short circuit between the P electrode 32 and the N electrode 31 .

[0044] Specifically, a plurality of connection bumps are provided on the substrate 2, and the plurality of N electrodes 31, the plurality of P electrodes 32 and the plurality of transition electrodes 34 are connected to the plurality of connection bumps one by one. Based on the connection bumps, the structural height consistency between the plurality of N electrodes 31, the plurality of P electrodes 32 and the plurality of transition electrodes 34 can be ensured, thereby ensuring the structural stability of the light-emitting module.

[0045] Furthermore, the several connecting bumps are metal connecting bumps, so that the electrodes of the chip structure are electrically connected to the connecting bumps, and the connecting bumps corresponding to the positions of the several N electrodes 31 and the several P electrodes 32 on the substrate 2 are electrically connected to the internal driving circuit to form the several conduction points, so that the several N electrodes 31 and the several P electrodes 32 of the chip array 3 are connected to the driving circuit of the substrate 2; the connecting bumps corresponding to the positions of the several transition electrodes 34 on the substrate 2 are arranged in the insulating area of ​​the substrate 2, so that the several transition electrodes 34 are in a non-conducting state, so as to ensure that there is sufficient electrical insulation distance between the several N electrodes 31 and the P electrode array, so as to avoid a short circuit between the N electrodes 31 and the P electrodes 32.

[0046] Specifically, the chip array 3 also includes a chip main structure 33 and a current guiding layer 35, wherein the plurality of P electrodes 32, the plurality of N electrodes 31 and the plurality of transition electrodes 34 are formed in the chip main structure 33, and a plurality of wire grooves are opened on the chip main structure 33, and the current guiding layer 35 is arranged in at least one of the plurality of wire grooves.

[0047] Furthermore, the current guiding layer 35 may be a metal conductive material, such as one or more of gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni) and iron (Fe), or the current guiding layer 35 may be an alloy.

[0048] Furthermore, the shape of the current guiding layer 35 can be a longitudinal strip, a transverse strip, a ring, a grid, etc.

[0049] Furthermore, the current guiding layer 35 may be a metal grid, and the metal grid may improve the uniformity of current transmission between a plurality of P electrodes and a plurality of N electrodes.

[0050] A plurality of transition bosses are disposed between the P electrode array and the plurality of N pole bosses, the transition electrodes 34 are formed on the transition bosses, and the plurality of transition electrodes 34 form a transition column.

[0051] Furthermore, several P electrodes 32 in the P electrode array are distributed independently of each other, and the several N electrodes 31 are connected in series. Any of the P electrodes 32 is connected to the N electrode 31 to form a light-emitting chip, that is, several light-emitting chips with a common N-pole design are formed in the chip array 3. Based on the common N-pole structure design, the electrical connection structure of the chip array 3 can be simplified, and the convenience of electrical connection of the chip array 3 can be improved.

[0052] For details, please refer to Figures 2 to 4The plurality of N electrodes 31 are arranged on the side of at least one side of the P electrode array, that is, the plurality of N electrodes 31 can be arranged on one or more of the upper side, lower side, left side and right side of the P electrode array. Based on the current guiding layer 35, the convenience of electrical connection between the P electrode 32 and the N electrode 31 is improved, so that the chip array 3 forms a common N-pole array arrangement.

[0053] Furthermore, the arrangement structure of the plurality of N electrodes 31 is preferably a ring arrangement, that is, the plurality of N electrodes 31 are arranged on four sides of the P electrode array to form a ring arrangement structure, so that the current between the P electrodes 32 distributed on the periphery of the P electrode array and the plurality of N electrodes 31 is evenly distributed. Based on the ring arrangement structure of the plurality of N electrodes 31, in cooperation with the current guiding layer 35, the current of each P electrode 32 in the P electrode array can be evenly distributed.

[0054] Specifically, the N-electrode 31 includes: the N-pole boss, a first electrode layer 312 arranged on the top surface of the N-pole boss, and an N-pole welding point 311 arranged on the first electrode layer 312, one side of the first electrode layer 312 extends along the side wall of the N-pole boss to the bottom of the wire groove, so that the first electrode layer 312 is connected to the N-type semiconductor layer 332 of the chip structure, thereby realizing the electrical connection between the P-electrode 32 and the N-electrode 31.

[0055] Furthermore, a first insulating layer 313 is provided on the N-electrode 31, and the first insulating layer 313 covers the side wall of the N-pole boss and the surface of the first electrode. A first matching groove is formed on the top surface of the first electrode, and the N-pole welding point 311 is arranged in the first matching groove.

[0056] Specifically, the P-electrode 32 includes: the P-pole boss, a second electrode layer 322 arranged on the P-pole boss, a P-pole welding point 321 arranged on the second electrode layer 322, and a second insulating layer 323, the second insulating layer 323 covers the side wall of the P-pole boss, and the second insulating layer 323 covers the surface of the second electrode layer 322, based on the second insulating layer 323, a second matching groove is formed on the top of the second electrode layer 322, and the P-pole welding point 321 is arranged in the second matching groove.

[0057] Furthermore, the N-pole solder joint 311 and the P-pole solder joint 321 are both Au-Sn solder joints (gold-tin alloy solder joints), and the N-pole solder joint 311 and the P-pole solder joint 321 are used to realize the electrical connection between the chip array 3 and the working circuit board. Based on the structural design of the common N-pole, the electrical circuit integration of the driving circuit can be simplified.

[0058] Furthermore, the N-electrode 31 and the P-electrode 32 have the same structural height, so that the N-pole solder joint 311 and the P-pole solder joint 321 of the chip array 3 are located in the same horizontal plane, so that the chip array 3 is electrically connected to the working circuit board.

[0059] Specifically, Figure 6 A cross-sectional view of a chip array structure in an embodiment of the present utility model is shown; Figure 7 A schematic diagram of a current guiding layer structure in an embodiment of the utility model is shown; Figure 8 A schematic diagram of another structural state of the current guiding layer in an embodiment of the utility model is shown, wherein a plurality of transition electrodes 34 are arranged on the transition column, and the transition column is used to separate the P electrode array and the plurality of N electrodes 31, so that there can be a sufficient electrical protection distance between the N electrode 31 and the P electrode 32, thereby avoiding a short circuit between the N electrode 31 and the P electrode 32 during the use of the chip array 3.

[0060] Furthermore, the electrode structure of the transition electrode 34 is consistent with the electrode structure of the N electrode 31, and the P electrode 32, the N electrode 31 and the transition electrode 34 have the same height, which improves the convenience of electrical connection between the light-emitting module and the working circuit board.

[0061] Specifically, based on the structural design of the transition column, the sizes of several wire grooves on the chip array 3 are the same. When the black primer is filled at the bottom, the flow uniformity of the black primer in the wire groove can be ensured, so that the black primer can be evenly laid between several N electrodes 31 and several P electrodes 32 of the chip array 3, avoiding the occurrence of glue jams and uneven distribution of the black primer, thereby improving the light output reliability of the chip array 3.

[0062] Specifically, the groove depth of any of the wire grooves extends to the N-type semiconductor layer 332, and the first electrode layer 312 of the N-electrode 31 extends to the N-type semiconductor layer 332, so that any of the P-electrodes 32 can be connected to the first electrode layer 312 of the N-electrode 31 based on the N-type semiconductor layer 332, thereby forming a light-emitting chip structure.

[0063] Specifically, grooves are provided at positions of the N-type semiconductor layer 332 corresponding to the plurality of wire slots, and the current guiding layer 35 is snap-fitted into the grooves. The grooves can improve the convenience of installing the current guiding layer 35 and the accuracy of installing and positioning.

[0064] Furthermore, the current guiding layer 35 is partially embedded in the N-type semiconductor layer 332, so that the current guiding layer 35 can block the light in the N-type semiconductor layer 332, that is, reduce the lateral propagation of the light between the multiple light-emitting chips in the chip array 3 in the N-type semiconductor layer 332, thereby reducing the risk of cross-talk between the light-emitting chips.

[0065] Specifically, the thickness of the current guiding layer 35 is greater than the depth of the groove, so that part of the current guiding layer 35 is exposed on the N-type semiconductor layer 332, so that the first electrode layer 312 of the N-electrode 31 can be connected with the current guiding layer 35 when extending to the N-type semiconductor layer 332, and the current guiding layer 35 can limit the first electrode layer 312, thereby improving the convenience of setting the first electrode layer 312.

[0066] Furthermore, based on the current guiding layer 35 , an interconnection path between the N-electrode 31 and the P-electrode 32 can be realized, and based on the current guiding layer 35 , the conductivity of the N-type semiconductor layer 332 is improved, thereby improving the current uniformity between the N-electrode 31 and the P-electrode 32 .

[0067] Furthermore, the surface of the current guiding layer 35 is covered with a third insulating layer 36 , and the third insulating layer 36 is used to protect the current guiding layer 35 to avoid short circuits between the light-emitting chips in the chip array 3 .

[0068] Specifically, the light-emitting module also includes: a dam 4 covering the chip array 3 , a light conversion layer 5 arranged above the chip array 3 , and a packaging layer 6 covering the dam 4 , wherein the light conversion layer 5 is used to convert the light color of the chip array 3 .

[0069] Specifically, the dam 4 is a transparent adhesive layer, and the dam 4 is formed based on the transparent adhesive layer to avoid the situation where the dam 4 absorbs heat and causes excessive heat accumulation on the light-emitting surface of the light-emitting module when a black dam 4 is used. At the same time, it is avoided that when a white wall dam 4 is used, the dam 4 reflects the light emitted by the chip array 3 and causes stray light.

[0070] Furthermore, the encapsulation layer 6 may be a black glue layer, and the black glue layer may be silica gel doped with carbon powder. The black glue layer can protect the reliability of the light emitting module and improve the contrast of the light emitted by the light emitting module.

[0071] Furthermore, the encapsulation layer 6 may be a white adhesive layer, which can improve the reflection effect of the light emitted by the light-emitting module and improve the light-emitting efficiency of the light-emitting module.

[0072] Support glue 8 is filled between the plurality of P electrodes 32 and the plurality of N electrodes 31 of the chip array 3 . The support glue 8 can avoid cross-talk between the light-emitting chips in the chip array 3 , thereby improving the light output efficiency of the chip array 3 .

[0073] Furthermore, the supporting glue 8 may be a black base glue, which can effectively avoid the cross-lighting between the chips and improve the light output contrast of the light-emitting chip.

[0074] Specifically, the dam 4 may be made of silicone, that is, the dam 4 is a transparent silicone layer, and the chip array 3 and the light conversion layer 5 are coated and protected by the transparent adhesive layer to prevent the chip array 3 and the light conversion layer 5 from being damaged.

[0075] Furthermore, the material of the dam 4 may also be resin, which has good plastic sealing and curing performance.

[0076] Specifically, the height of the dam 4 is h1, the height of the light conversion layer 5 is h2, and the constraint relationship between h1 and h2 is: h1≥h2, so that the dam 4 can completely cover the LED chip array 3 and the side wall of the light conversion layer 5, avoid direct contact between the light conversion layer 5 and the LED chip array 3 and the packaging layer 6, and avoid the black packaging layer 6 absorbing heat, causing heat damage to the light conversion layer 5, that is, the dam 4 formed based on the transparent adhesive layer can complete the covering support of the light conversion layer 5, reduce the influence of the dam 4 on the light emitting light of the chip array 3, and ensure that the chip array 3 has good light emitting effect.

[0077] Furthermore, the height of the dam 4 can be higher than the light conversion layer 5, and the dam 4 can cover the top edge area of ​​the light conversion layer 5, so that the dam 4 can protect the light conversion layer 5, reduce the risk of damage to the light conversion layer 5, and improve the light output efficiency of the chip array 3.

[0078] Furthermore, the light conversion layer 5 includes at least one of fluorescent powder, quantum dots and organic dyes.

[0079] Specifically, in this embodiment, the light conversion layer 5 is provided with phosphor, and the light color of the light emitted by the chip array 3 is converted based on the phosphor. In this embodiment, the phosphor is a YAG series yellow phosphor or a nitride yellow phosphor. In this embodiment, the phosphor is Y3Al5O 12 :Ce 3+ , used to convert the blue light of the chip array 3 into white light.

[0080] Specifically, the light-emitting module also includes a transition carrier 1, the substrate 2 is arranged on the transition carrier 1, the transition carrier 1 is used to connect the substrate 2 and the external circuit board, the material of the transition carrier 1 can be ceramic, the thermal expansion coefficient of the transition carrier 1 is between the thermal expansion coefficient of the substrate 2 and the thermal expansion coefficient of the external circuit board, and the transition carrier 1 is arranged between the substrate 2 and the external circuit board so that the thermal expansion coefficients of the external circuit board, the transition carrier 1 and the substrate 2 are matched, thereby avoiding direct contact between the substrate 2 and the external circuit board, thereby avoiding cracking caused by thermal expansion between the substrate 2 and the external circuit board, and improving the structural stability of the light-emitting module.

[0081] Furthermore, in the present embodiment, the material of the transition carrier 1 is AlN (aluminum nitride) ceramic material, which has good thermal conductivity and electrical insulation, can meet the installation requirements of the light-emitting module, and improve the heat dissipation efficiency of the light-emitting module.

[0082] Specifically, a metal electrode 11 is provided on the transition carrier 1, and a connecting electrode 21 is provided on the substrate 2. The metal electrode 11 of the transition carrier 1 and the connecting electrode 21 on the substrate 2 are electrically connected based on a welding wire, that is, the substrate 2 and the transition carrier 1 are connected based on a welding wire. A pin pad is provided at the bottom of the transition carrier 1, and the pin pad is provided corresponding to the metal electrode 11. The transition carrier 1 can be electrically connected to an external circuit board based on the pin pad.

[0083] Furthermore, based on the transition carrier 1, the wire bonding connection mode of the substrate 2 is converted into a solder point connection mode of the pin pad, thereby improving the convenience of the integrated packaging of the light-emitting module and the external circuit board.

[0084] Furthermore, the metal electrode 11, the connecting electrode 21 and the welding wire are contained in the packaging layer 6. The packaging layer 6 formed based on the black glue layer can shield and protect the metal electrode 11, the connecting electrode 21 and the welding wire, thereby ensuring the reliability of the electrical connection structure between the substrate 2 and the transition carrier 1.

[0085] An embodiment of the utility model provides a light-emitting module, which forms a chip array 3 structure by setting a plurality of N electrodes 31 in cooperation with a P electrode array, and a transition electrode 34 is set between the plurality of N electrodes 31 and the P electrode array. The transition electrode 34 is used to expand the distance between the N electrode 31 and the P electrode array, and reduce the risk of short circuit between the P electrode 32 and the N electrode 31, thereby improving the reliability of the light-emitting module, and at the same time making the distance between each electrode in the light-emitting module uniform, thereby ensuring the fluidity of the packaging glue and the packaging effect.

[0086] In addition, the above is a detailed introduction to a light-emitting module provided in an embodiment of the utility model. Specific examples are used herein to illustrate the principle and implementation mode of the utility model. The description of the above embodiments is only used to help understand the method and core idea of ​​the utility model. At the same time, for general technical personnel in this field, according to the idea of ​​the utility model, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as a limitation on the utility model.

Claims

1. A light emitting module, characterized in that: The light-emitting module comprises: a substrate and a chip array arranged on the substrate, wherein the chip array comprises a chip main body structure, and a plurality of P electrodes, a plurality of N electrodes and a plurality of transition electrodes are formed in the chip main body structure; The plurality of P electrodes form a P electrode array, the plurality of N electrodes are arranged on at least one side of the P electrode array, the plurality of transition electrodes are arranged between the P electrode array and the plurality of N electrodes, and the plurality of transition electrodes form a transition column.

2. The light emitting module according to claim 1, characterized in that: Support glue is filled between the plurality of P electrodes and the plurality of N electrodes of the chip array.

3. The light emitting module according to claim 1, characterized in that: The substrate is a silicon-based circuit board, a driving circuit is arranged on the silicon-based circuit board, and the chip array is electrically connected to the driving circuit.

4. The light emitting module according to claim 3, characterized in that: The driving circuit is provided with a plurality of conduction points, and the plurality of conduction points are arranged in one-to-one correspondence with the plurality of N electrodes and the plurality of P electrodes of the chip array; The plurality of N electrodes and the plurality of P electrodes are electrically connected to the plurality of conduction points in a one-to-one correspondence.

5. The light emitting module according to claim 4, characterized in that: A plurality of connection bumps are arranged on the substrate, and the plurality of N electrodes, the plurality of P electrodes and the plurality of transition electrodes are connected to the plurality of connection bumps in a one-to-one correspondence.

6. The light emitting module according to claim 5, characterized in that: The connection bumps on the substrate corresponding to the positions of the plurality of N electrodes and the plurality of P electrodes are electrically connected to the internal driving circuit to form the plurality of conduction points.

7. The light emitting module according to claim 5, characterized in that: The connection bumps on the substrate corresponding to the positions of the plurality of transition electrodes are arranged in the insulating area of ​​the substrate.

8. The light emitting module according to claim 1, characterized in that: The chip array further comprises a current guiding layer. A plurality of wire grooves are provided on the chip main body structure. The current guiding layer is arranged in at least one of the plurality of wire grooves.

9. The light emitting module according to claim 8, characterized in that: A groove is provided at the bottom of the wire slot, and the current guiding layer is snap-fitted in the groove.

10. The light emitting module according to claim 8, characterized in that: The chip main body structure forms a plurality of bosses arranged in an array based on the wire grooves, and the array structure of the plurality of bosses includes a plurality of N-pole bosses and a plurality of P-pole bosses, a P electrode is formed on the P-pole boss, and the plurality of P electrodes form a P electrode array, an N electrode is formed on the N-pole boss, and the plurality of N electrodes are arranged on the outer edge of the P electrode array.

11. The light emitting module according to claim 10, characterized in that: A plurality of transition bosses are arranged between the P electrode array and the plurality of N pole bosses, the plurality of transition electrodes are formed on the plurality of transition bosses, and the plurality of transition electrodes form a transition column.

12. The light emitting module according to claim 1, characterized in that: The plurality of P electrodes in the P electrode array are independently distributed, the plurality of N electrodes are connected in series, and any one of the P electrodes is connected to the N electrode to form a light-emitting chip.

13. The light emitting module according to claim 1, characterized in that: The light-emitting module further includes: a dam covering the chip array, a light conversion layer arranged above the chip array, and a packaging layer covering the dam, wherein the light conversion layer is used to convert the light color of the chip array.

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