Packaging structure of semiconductor device
By adopting a mold-independent design in the packaging structure of semiconductor devices, and using the combination of substrate, fence, chip, bonding wire, protective layer and packaging glue, the problems of high packaging costs and material forming cooling and shrinkage in the prior art are solved, and a low-cost and high-reliability packaging effect is achieved.
Patent Information
- Application Number
- CN202421134702.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-22
- Publication Date
- 2025-05-09
- Estimated Expiration
- 2034-05-22
AI Technical Summary
The packaging structure of existing optoelectronic semiconductor devices relies on molds, which leads to high costs and has product failure problems caused by material molding, cooling and shrinkage.
The packaging structure that does not rely on molds is adopted, including a substrate, a first fence, a control chip, an optoelectronic chip, a bonding wire, a protective layer or a wavelength converter and a packaging glue, the first fence and the substrate are bonded through glue, and the gap is filled with the packaging glue and key components are covered to form a high-reliability and low-cost packaging design.
It realizes low-cost and high-reliability semiconductor device packaging, avoids high cost of mold dependence and product damage caused by material molding cooling and shrinkage, and improves the mechanical stability of the packaging structure and the brightness of the optoelectronic chip.
Smart Images
Figure CN222851446U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and more specifically, to a packaging structure of a semiconductor device. Background Art
[0002] The packaging structure of existing optoelectronic semiconductor devices is usually composed of structures and components made of a variety of different materials, and relies on molds for final packaging molding. The corresponding cost of the molds is relatively high. The product may involve multiple sets of molds from the beginning of design to the final shaping, which leads to high manufacturing costs of the product.
[0003] Furthermore, since different materials have different expansion coefficients, when rigid materials are used to wrap bonding wires and chips, there is a risk of chips falling off and bonding wires tearing. Using softer materials can avoid such risks, but softer materials cannot provide mechanical protection for the packaging structure, and the product may deform and components may be damaged.
[0004] At present, the packaging structure of optoelectronic semiconductor devices needs to be manufactured using molds, which is not only too expensive, but also faces problems such as product failure caused by shrinkage during material molding and cooling.
[0005] Therefore, there is an urgent need for a semiconductor device packaging structure that is independent of molds and has higher reliability to meet market demand. Utility Model Content
[0006] In view of this, the utility model provides a packaging structure of a semiconductor device, which avoids dependence on a mold, reduces packaging costs, and achieves the requirements of low cost and high reliability.
[0007] To achieve this object, the utility model provides a packaging structure of a semiconductor device, comprising: a substrate; a first enclosure located on the first surface of the substrate, the first enclosure being arranged around the edge of the substrate; a control chip located on the first surface of the substrate, the control chip being located in a cavity surrounded by the first enclosure; an optoelectronic chip located on the control chip and covering a portion of the surface of the control chip; a bonding wire, the bonding wire electrically connecting the control chip to the substrate; a protective layer or a wavelength converter covering the optoelectronic chip; an encapsulation glue located on the first surface of the substrate, the encapsulation glue filling a gap between the first enclosure and the control chip, and extending to cover one of the following partial top surfaces: (1) the encapsulation glue extending to cover a portion of the top surface of the control chip; (2) the encapsulation glue extending to cover a portion of the top surface of the protective layer; (3) the encapsulation glue extending to cover a portion of the top surface of the wavelength converter.
[0008] Optionally, the first enclosure is bonded to the base plate by glue.
[0009] Optionally, the first enclosure includes a plurality of structural members stacked up and down, and adjacent structural members are bonded by glue.
[0010] Optionally, the first enclosure is a single-layer structure.
[0011] Optionally, the first enclosure is a resin enclosure, a silicone enclosure or a metal enclosure.
[0012] Optionally, the first enclosure is made of the same material as that of the substrate.
[0013] Optionally, the protective layer is a transparent layer.
[0014] Optionally, the wavelength converter is a phosphor layer.
[0015] Optionally, the thickness of the packaging glue is smaller than the height of the first enclosure, and the packaging glue completely covers the bonding wire.
[0016] Optionally, the protective layer or the wavelength converter further extends to cover a portion or the entire surface of the control chip.
[0017] Optionally, a second enclosure is further included, and the second enclosure is arranged around the light-emitting area of the optoelectronic chip.
[0018] Optionally, when the packaging glue extends to cover a portion of the top surface of the control chip, the second enclosure is located on the surface of the control chip.
[0019] Optionally, when the packaging glue extends to cover a portion of the top surface of the protective layer, the second barrier is located on the surface of the protective layer.
[0020] Optionally, when the packaging glue extends to cover a portion of the top surface of the wavelength converter, the second enclosure is located on the surface of the wavelength converter.
[0021] Optionally, an upper surface of the packaging glue is lower than an upper surface of the second enclosure, and the packaging glue is located between the first enclosure and the second enclosure.
[0022] Optionally, a heat conducting block is further provided on the substrate in a region corresponding to the control chip.
[0023] Optionally, the heat conductive block is a plurality of separate heat conductive blocks.
[0024] Optionally, a projection of the packaging adhesive toward the substrate does not overlap with a projection of the optoelectronic chip toward the substrate.
[0025] The beneficial effects of the utility model are as follows: the packaging structure of the semiconductor device of the utility model, the protective layer or the wavelength converter covers the optoelectronic chip, which can protect the optoelectronic chip. The protective layer attached to the optoelectronic chip can make the packaging structure more reliable; the wavelength converter attached to the optoelectronic chip is easier to dissipate heat of the wavelength converter, and the better the heat dissipation, the higher the conversion efficiency of the wavelength converter.
[0026] Furthermore, by using glue to bond the first enclosure to the substrate, the processing of the packaging structure is freed from the need for a mold, which can effectively reduce costs while achieving a flat packaging design; the packaging glue will hinder the light emission of the optoelectronic chip, and the packaging glue does not cover the light-emitting area of the optoelectronic chip to ensure the brightness of the optoelectronic chip.
[0027] Furthermore, the packaging structure adopts a combination of a hard first enclosure on the outside and an elastic packaging glue on the inside, which not only provides a good external protection frame for the chip, but the softer packaging glue on the inside also reduces the risk of chip falling off and bonding wire tearing. The packaging structure of the semiconductor device can not only avoid damage to the chip caused by cooling shrinkage during material molding, but its structure also has high mechanical stability, thereby improving the stability of the packaging structure of the semiconductor device.
[0028] Furthermore, the second enclosure can prevent the packaging glue from overflowing into the light-emitting area of the optoelectronic chip, thereby ensuring the brightness of the optoelectronic chip.
[0029] Furthermore, conductive blocks may be used in the substrate to replace through holes, thereby improving the heat dissipation performance of the packaging structure of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0031] Figure 1 is a cross-sectional schematic diagram of a packaging structure of a semiconductor device according to a first embodiment of the utility model;
[0032] Figure 2 It is a schematic top view layout diagram of the packaging structure of the semiconductor device of the first embodiment of the utility model;
[0033] Figure 3 is a cross-sectional schematic diagram of a packaging structure of a semiconductor device according to a second embodiment of the utility model;
[0034] Figure 4 is a schematic top view layout diagram of a semiconductor device packaging structure according to a second embodiment of the utility model;
[0035] Figure 5A schematic diagram showing the manufacturing process of a packaging structure of a semiconductor device according to a second embodiment of the present invention;
[0036] Figures 6a to 6e Schematic cross-sectional views showing the various manufacturing steps of the packaging structure of the semiconductor device of the second embodiment of the utility model;
[0037] Figure 7 is a schematic cross-sectional view of a packaging structure of a semiconductor device according to a third embodiment of the present utility model;
[0038] Figure 8 is a schematic cross-sectional view of a packaging structure of a semiconductor device according to a fourth embodiment of the present utility model;
[0039] Fig. 9 It is a schematic diagram of the arrangement of the heat conducting blocks of the packaging structure of the semiconductor device according to the fourth embodiment of the utility model. DETAILED DESCRIPTION
[0040] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. For those skilled in the art, the present invention can be fully understood without the description of these details. In order to avoid confusing the essence of the present invention, well-known methods, processes, procedures, and components are not described in detail.
[0041] In the description of the present invention, it is necessary to understand that the orientation or position relationship indicated by the terms such as "upper", "lower", "left", "right", "inside", "outside", "horizontal" and "longitudinal" is based on the orientation or position relationship shown in the corresponding drawings. It is for the convenience of describing the shape, position and connection relationship of each component in the present invention, rather than indicating or implying that the components must be located in a specific orientation and morphological structure in the whole, and should not be understood as a limitation on the present invention.
[0042] Figure 1 It is a cross-sectional schematic diagram of the packaging structure of the semiconductor device of the first embodiment of the utility model. The packaging structure 100 of the semiconductor device of the first embodiment includes a substrate 1 and a chip 2 located on the first surface 10 (the front side of the substrate) of the substrate 1. A first enclosure 3 is also provided on the first surface 10 around the edge of the substrate 1. The inner area of the first enclosure forms a cavity 30. The chip 2 is located in the cavity 30. The chip 2 includes, for example, a control chip 21 and an optoelectronic chip 22. The optoelectronic chip 22 is electrically connected to the control chip 21. The control chip 21 is located on the first surface 10 of the substrate 1, and the optoelectronic chip 22 is located on the control chip 21 and covers part of the surface of the control chip 21.
[0043] The optoelectronic chip 22 is, for example, a light emitting diode chip or a laser diode chip, etc. The optoelectronic chip 22 has, for example, a plurality of light emitting areas that can be independently controlled and these light emitting areas can be arranged in a matrix form. For example, the optoelectronic chip 22 includes a matrix composed of 80*320 light emitting areas, but is not limited thereto, and can be applied to adaptive lighting in the automotive field. The control chip 21 is, for example, a chip for controlling the optoelectronic chip 22.
[0044] The second surface of the substrate 1 is arranged opposite to the first surface 10, and both the first surface and the second surface of the substrate 1 are planes. Further, the substrate 1 can be a single-layer or multi-layer structure, that is, a layer made of one material or a multi-layer structure made of one or more materials. The substrate 1 is made of plastic or ceramic material, for example, and the substrate 1 can be a single-layer or multi-layer PCB board, a single-layer or multi-layer ceramic substrate, etc. A plurality of conductive layers 12 are also arranged on the first surface 10 of the substrate 1, and the first surface (upper surface) of the control chip 21 is electrically connected to the corresponding conductive layer 12 on the substrate 1 through the bonding wire 4. Figure 1 Two bonding wires 4 are shown in the figure. In other embodiments, the control chip 21 can be electrically connected to the conductive layer 12 through at least one bonding wire 4. The second surface (back side of the substrate) of the substrate 1 is also provided with a pad 11, which is used, for example, for mounting and external electrical connection of the packaging structure 100 of the semiconductor device. The substrate 1 is also provided with a through hole 13 connecting the first surface 10 and the second surface. The through hole 13, for example, includes a plurality of through holes. By filling the side wall of the through hole 13 or in the through hole 13 with conductive material, the conductive layer 12 or other conductive wiring structure on the first surface 10 can be connected to the pad 13 on the second surface to achieve electrical connection; further, the heat in the chip 2 can be timely discharged through the through hole 13 to achieve good heat dissipation capability.
[0045] The first enclosure 3 is bonded to the first surface 10 of the substrate 1 by glue 32, for example. The first enclosure 3 is an annular structure. The outer boundary of the first enclosure 3 matches the outer boundary of the substrate 1, for example. The inner side of the first enclosure 3 forms a cavity 30. The first enclosure 3 can be a single-layer structure. Of course, the first enclosure 3 can also include a plurality of structural members 31 stacked up and down, and the adjacent structural members 31 are bonded by glue 32. Specifically, Figure 1 As shown, the edge of the substrate 1 includes, for example, a first enclosure 3 formed by two layers of stacked structural members 31, and the first enclosure 3 is made of, for example, a hard material to provide protection for the chip 2. The material of the first enclosure 3 is, for example, one of plastic or metal materials, wherein the plastic material is, for example, BT (resin) material, epoxy resin or silicone grease, and the first enclosure 3 may be colored. Furthermore, the material of the first enclosure 3 may be the same as that of the substrate 1.
[0046] See also Figure 2As shown, the size of the control chip 21 is, for example, larger than the size of the optoelectronic chip 22, and a pad may be provided in the edge area of the control chip 21 for bonding or increasing the area to enhance heat dissipation. A protective layer or wavelength converter 5 is provided on the optoelectronic chip 22, and the protective layer or wavelength converter 5 at least covers the surface of the optoelectronic chip 22. In this embodiment, the protective layer or wavelength converter 5 covers the surface of the optoelectronic chip 22 and the exposed surface of the control chip 21. The protective layer or wavelength converter 5 may be made of, for example, silicone, ceramic, glass, and the like. Optionally, the protective layer 5 is a transparent layer that only protects the optoelectronic chip 22 without changing the light color of the optoelectronic chip 22, and the optoelectronic chip 22 emits, for example, red, green, blue, and other colors of light. Optionally, the wavelength converter 5 is a phosphor layer that has a wavelength conversion function and can convert the light emitted by the optoelectronic chip 22 into white light. The encapsulation glue 6 is filled between the first frame 3 and the chip 2 (control chip 22), covering the bonding wire 4 to protect the bonding wire 4. Furthermore, the encapsulation glue 6 also extends to cover the edge of the protective layer or wavelength converter 5 to prevent water vapor in the external environment from entering from the interface between the protective layer or wavelength converter 5 and the control chip 21 to affect the reliability of the chip 2. The projection of the encapsulation glue 6 in the direction of the substrate 1 does not overlap with the projection of the optoelectronic chip 22 in the direction of the substrate 1, which can ensure the brightness of the optoelectronic chip 22. The protective layer or wavelength converter 5 is generally arranged on the control chip 21 and the optoelectronic chip 22 before the encapsulation glue 6. After the bonding wire 4 and the protective layer or wavelength converter 5 are arranged, the encapsulation glue 6 is filled into the cavity 30 to cover the exposed surface of the substrate 1, the bonding wire 4, the chip 2 and the edge of the protective layer or wavelength converter 5. The chip 2 and the bonding wire 4 are sealed and protected by the encapsulation glue 6 and the protective layer or wavelength converter 5. In order to reduce the impact on the bonding wire 4, the encapsulation glue 6 can be applied by dispensing or injection molding, for example. The encapsulation glue 6 is made of elastic materials, such as silicone, silica gel, epoxy resin, etc., and its hardness is less than the first enclosure 3. The encapsulation glue 6 can not only achieve sealing and waterproofing, but also reduce the mechanical load and stress of the bonding wire 4 and the chip 2, and avoid the risk of the bonding wire 4 tearing and the chip 2 falling off. Of course, in order to ensure that the function of the optoelectronic chip 22 is not affected, the encapsulation glue 6 only covers the edge area of the protective layer or the wavelength converter 5, and the encapsulation glue 6 is not set in the light-emitting area of the optoelectronic chip 22 to ensure the light-emitting brightness of the optoelectronic chip 22. In order to avoid the overflow of the encapsulation glue 6, the height of the first enclosure 3 is, for example, not less than the height of the chip 2 and the protective layer or the wavelength converter 5 combined, that is, the thickness of the encapsulation glue 6 is less than the height of the first enclosure 3.
[0047] Figure 3 is a schematic cross-sectional view of a packaging structure of a semiconductor device according to a second embodiment of the present utility model, Figure 41 is a schematic diagram of a top view layout of a semiconductor device packaging structure of a second embodiment of the present invention; the overall packaging structure of the semiconductor device of the second embodiment is similar to that of the first embodiment, except that a second enclosure 7 is further provided in the edge region on the protective layer or the wavelength converter 5, and the second enclosure 7 surrounds the edge region of the protective layer or the wavelength converter 5 and is not provided above the optoelectronic chip 22, such as Figure 3 and Figure 4 As shown, it can be avoided that the encapsulation glue 6 spreads to the light-emitting area of the optoelectronic chip 22 when filling the encapsulation glue 6, affecting the brightness of the optoelectronic chip 22, that is, the projection of the encapsulation glue 6 in the direction of the substrate 1 does not overlap with the projection of the optoelectronic chip 22 in the direction of the substrate 1, which can ensure the brightness of the optoelectronic chip 22. The second enclosure 7 is, for example, set before the encapsulation glue 6, and the second enclosure 7 also has a certain height. The second enclosure 7 is, for example, made of the same material as the encapsulation glue 6, and the second enclosure 7 is, for example, formed by a dispensing process; of course, the second enclosure 7 can also be formed of other materials. The second enclosure 7 is, for example, an opaque material, which can not only block the flow of the encapsulation glue 6, but also reduce unnecessary light scattering and reduce the interference of stray light.
[0048] The manufacturing process of the packaging structure of the semiconductor device of the second embodiment is as follows: Figure 5 As shown, including:
[0049] Step S10, setting a first enclosure on the substrate; specifically, Figure 6a As shown, glue 32 is applied to the edge of the first surface 10 of the substrate 1 and the area corresponding to the first enclosure 3, and the first enclosure 3 is pasted on the substrate 1. When the first enclosure 3 includes a multi-layer structure, the structural member 31 is mounted on the substrate 1, and then glue 32 is applied to the upper surface of the structural member 31, and another layer of structural member 31 is stacked on the structural member 31. Of course, the multi-layer structural members 31 can also be first bonded by glue 32 and then bonded to the first surface 10 of the substrate 1 together.
[0050] Step S20, placing a chip on a substrate and electrically connecting the chip to the substrate via bonding wires; specifically, Figure 6b As shown, a chip 2 is arranged in a cavity 30 surrounded by a first enclosure 3 on a first surface 10 of a substrate 1. The chip 2 includes a control chip 21 and an optoelectronic chip 22. The optoelectronic chip 22 is located above the control chip 21. The pad on the upper surface of the control chip 21 is electrically connected to the substrate 1 through a bonding wire 4.
[0051] Step S30: setting a protective layer or a wavelength converter; specifically, Figure 6c As shown, a protection layer or a wavelength converter 5 is disposed on the control chip 21 to cover the exposed area of the control chip 21 and the optoelectronic chip 22 .
[0052] Step S40 forms a second enclosure; specifically, Figure 6d As shown, on the protective layer or the wavelength converter 5, a second enclosure 7 is arranged around the light emitting area of the optoelectronic chip 22, and the second enclosure 7 can be arranged, for example, by a glue dispensing process.
[0053] Step S50 forms a packaging glue; specifically, Figure 6e As shown, encapsulation glue 6 is filled between the first enclosure 3 and the second enclosure 7 to cover the exposed surface of the substrate 1, the bonding wires 4, the chip 2 and the edge of the protective layer or the wavelength converter 5, and the chip 2 and the bonding wires 4 are sealed and protected by the encapsulation glue 6 and the protective layer or the wavelength converter 5.
[0054] Figure 7 : is a cross-sectional schematic diagram of the packaging structure of the semiconductor device of the third embodiment of the utility model. The packaging structure of the semiconductor device of the third embodiment is similar to that of the second embodiment as a whole, except that the protective layer or wavelength converter 5 covers the surface of the optoelectronic chip 22 and extends to cover part of the surface of the control chip 21, the second enclosure 7 is located on the control chip 21, the packaging glue 6 covers the edge of the control chip 21, and there is a gap between the protective layer or wavelength converter 5 and the second enclosure 7. In other embodiments, the protective layer or wavelength converter 5 may also only cover the surface of the optoelectronic chip 22 without extending to cover the surface of the control chip 21, or the protective layer or wavelength converter 5 covers the surface of the optoelectronic chip 22 and extends to cover part of the surface of the control chip 21, and the protective layer or wavelength converter 5 extends to contact with the second enclosure 7. The projection of the packaging glue 6 in the direction of the substrate 1 does not overlap with the projection of the optoelectronic chip 22 in the direction of the substrate 1, so that the brightness of the optoelectronic chip 22 can be guaranteed.
[0055] Figure 8 is a schematic cross-sectional view of a packaging structure of a semiconductor device according to a fourth embodiment of the present utility model, Fig. 9 1 is a schematic diagram of the arrangement of the heat conducting blocks of the semiconductor device packaging structure of the fourth embodiment of the utility model; the fourth embodiment is also similar to the first embodiment, except that the heat conduction of the chip 2 in the semiconductor device packaging structure of the fourth embodiment is not achieved by the through hole 13. In the fourth embodiment, the substrate 1 is provided with a heat conducting block 14 in the area corresponding to the chip 2. For example, the heat conducting block 14 may be one or more. See Figure 8 and Fig. 9 A plurality of heat-conducting blocks 14 are arranged in an array below the chip 2. The edge of the heat-conducting block 14 is, for example, larger than the edge of the chip 2. The heat-conducting blocks 14 enhance the heat-conducting and heat-dissipating capacity of the semiconductor device packaging structure, thereby further improving its stability and reliability.
[0056] The beneficial effects of the utility model are as follows: the packaging structure of the semiconductor device of the utility model, the protective layer or the wavelength converter covers the optoelectronic chip, which can protect the optoelectronic chip. The protective layer attached to the optoelectronic chip can make the packaging structure more reliable; the wavelength converter attached to the optoelectronic chip is easier to dissipate heat of the wavelength converter, and the better the heat dissipation, the higher the conversion efficiency of the wavelength converter.
[0057] Furthermore, by using glue to bond the first enclosure to the substrate, the processing of the packaging structure is freed from the need for a mold, which can effectively reduce costs while achieving a flat packaging design; the packaging glue will hinder the light emission of the optoelectronic chip, and the packaging glue does not cover the light-emitting area of the optoelectronic chip to ensure the brightness of the optoelectronic chip.
[0058] Furthermore, the packaging structure adopts a combination of a hard first enclosure on the outside and an elastic packaging glue on the inside, which not only provides a good external protection frame for the chip, but the softer packaging glue on the inside also reduces the risk of chip falling off and bonding wire tearing. The packaging structure of the semiconductor device can not only avoid damage to the chip caused by cooling shrinkage during material molding, but its structure also has high mechanical stability, thereby improving the stability of the packaging structure of the semiconductor device.
[0059] Furthermore, the second enclosure can prevent the packaging glue from overflowing into the light-emitting area of the optoelectronic chip, thereby ensuring the brightness of the optoelectronic chip.
[0060] Furthermore, conductive blocks may be used in the substrate to replace through holes, thereby improving the heat dissipation performance of the packaging structure of the semiconductor device.
[0061] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.
[0062] At the same time, it should be understood that example embodiments are provided so that the present disclosure is comprehensive and its scope is fully conveyed to those skilled in the art. Many specific details (such as examples of specific components, devices and methods) are given to provide a comprehensive understanding of the present disclosure. It will be understood by those skilled in the art that specific details need not be adopted, that example embodiments can be implemented in many different forms, and that example embodiments should not be construed as limiting the scope of the present disclosure. In some example embodiments, well-known device structures and well-known technologies are not described in detail.
[0063] When an element or layer is referred to as being "on," "engaged to," "connected to," or "coupled to" another element or layer, it may be directly on, directly engaged to, connected to, or coupled to another element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly" "on," "directly engaged to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). As used herein, the term "and / or" includes any or all combinations of one or more of the associated listed items.
[0064] Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another element, region, layer or section. Terms such as "first", "second" and other numerical terms do not mean order or sequence when used here, unless the context clearly indicates. Thus, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section, without departing from the teaching of the exemplary embodiment. In addition, in the description of the utility model, unless otherwise stated, the meaning of "multiple" is two or more.
[0065] The above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. For those skilled in the art, the utility model may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.
Claims
1. A semiconductor device packaging structure, characterized in that: include: substrate; A first enclosure, located on a first surface of the substrate, the first enclosure being arranged around an edge of the substrate; A control chip is located on the first surface of the substrate, and the control chip is located in the cavity surrounded by the first enclosure; an optoelectronic chip, located on the control chip and covering a portion of the surface of the control chip; A bonding wire electrically connecting the control chip to the substrate; A protective layer or a wavelength converter, covering the optoelectronic chip; The packaging glue is located on the first surface of the substrate, the packaging glue fills the gap between the first enclosure and the control chip, and extends to cover one of the following partial top surfaces: (1) The packaging glue extends to cover a portion of the top surface of the control chip; (2) the encapsulation adhesive extends to cover a portion of the top surface of the protective layer; (3) The packaging glue extends to cover a portion of the top surface of the wavelength converter.
2. The packaging structure according to claim 1, characterized in that: The first enclosure is bonded to the base plate by glue.
3. The packaging structure according to claim 1 or 2, characterized in that: The first enclosure includes a plurality of structural members stacked up and down, and adjacent structural members are bonded by glue.
4. The packaging structure according to claim 1 or 2, characterized in that: The first enclosure is a single-layer structure.
5. The packaging structure according to claim 1 or 2, characterized in that: The first enclosure is a resin enclosure, a silicone enclosure or a metal enclosure.
6. The packaging structure according to claim 1 or 2, characterized in that: The first enclosure is made of the same material as that of the base plate.
7. The packaging structure according to claim 1, characterized in that: The protective layer is a transparent layer.
8. The packaging structure according to claim 1, characterized in that: The wavelength converter is a phosphor layer.
9. The packaging structure according to claim 1, characterized in that: The thickness of the packaging glue is smaller than the height of the first enclosure, and the packaging glue completely covers the bonding wire.
10. The packaging structure according to claim 1, characterized in that: The protection layer or the wavelength converter also extends to cover a portion or the entire surface of the control chip.
11. The packaging structure according to claim 1 or 10, characterized in that: It also includes a second enclosure, which is arranged around the light-emitting area of the optoelectronic chip.
12. The packaging structure according to claim 11, characterized in that: When the packaging glue extends to cover a portion of the top surface of the control chip, the second enclosure is located on the surface of the control chip.
13. The packaging structure according to claim 11, characterized in that: When the packaging glue extends to cover a portion of the top surface of the protection layer, the second barrier is located on the surface of the protection layer.
14. The packaging structure according to claim 11, characterized in that: When the packaging glue extends to cover a portion of the top surface of the wavelength converter, the second enclosure is located on the surface of the wavelength converter.
15. The packaging structure according to claim 11, characterized in that: The upper surface of the packaging glue is lower than the upper surface of the second enclosure, and the packaging glue is located between the first enclosure and the second enclosure.
16. The packaging structure according to claim 1, characterized in that: The substrate is further provided with a heat conducting block in a region corresponding to the control chip.
17. The packaging structure according to claim 16, characterized in that: The heat conducting block is a plurality of separate heat conducting blocks.
18. The packaging structure according to claim 1, characterized in that: The projection of the packaging glue toward the substrate does not overlap with the projection of the optoelectronic chip toward the substrate.